OpenCores
URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [log/] [gmac_test_2.log] - Blame information for rev 71

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 62 dinesha
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
2
 
3
# 6.6d
4
 
5
# vsim +gmac_test_2 -do run.do -c tb_top
6
# //  ModelSim ACTEL 6.6d Nov  2 2010
7
# //
8
# //  Copyright 1991-2010 Mentor Graphics Corporation
9
# //              All Rights Reserved.
10
# //
11
# //  THIS WORK CONTAINS TRADE SECRET AND
12
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
13
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
14
# //  AND IS SUBJECT TO LICENSE TERMS.
15
# //
16
# Loading sv_std.std
17
# Loading work.tb_top
18
# Loading work.turbo8051
19
# Loading work.clkgen
20
# Loading work.clk_ctl
21
# Loading work.wb_crossbar
22
# Loading work.g_mac_top
23
# Loading work.g_dpath_ctrl
24
# Loading work.g_eth_parser
25
# Loading work.g_mac_core
26
# Loading work.g_rx_top
27
# Loading work.g_rx_fsm
28
# Loading work.half_dup_dble_reg
29
# Loading work.g_rx_crc32
30
# Loading work.g_deferral_rx
31
# Loading work.g_md_intf
32
# Loading work.g_tx_top
33
# Loading work.g_deferral
34
# Loading work.g_tx_fsm
35
# Loading work.g_tx_crc32
36
# Loading work.toggle_sync
37
# Loading work.g_cfg_mgmt
38
# Loading work.s2f_sync
39
# Loading work.generic_register
40
# Loading work.req_register
41
# Loading work.stat_counter
42
# Loading work.generic_intr_stat_reg
43
# Loading work.g_mii_intf
44
# Loading work.async_fifo
45
# Loading work.wb_rd_mem2mem
46
# Loading work.wb_wr_mem2mem
47
# Loading work.uart_core
48
# Loading work.uart_cfg
49
# Loading work.stat_register
50
# Loading work.uart_txfsm
51
# Loading work.uart_rxfsm
52
# Loading work.double_sync_low
53
# Loading work.spi_core
54
# Loading work.spi_if
55
# Loading work.spi_ctl
56
# Loading work.spi_cfg
57
# Loading work.oc8051_top
58
# Loading work.oc8051_decoder
59
# Loading work.oc8051_alu
60
# Loading work.oc8051_multiply
61
# Loading work.oc8051_divide
62
# Loading work.oc8051_ram_top
63
# Loading work.oc8051_ram_256x8_two_bist
64
# Loading work.oc8051_alu_src_sel
65
# Loading work.oc8051_comp
66
# Loading work.oc8051_cy_select
67
# Loading work.oc8051_indi_addr
68
# Loading work.oc8051_memory_interface
69
# Loading work.oc8051_sfr
70
# Loading work.oc8051_acc
71
# Loading work.oc8051_b_register
72
# Loading work.oc8051_sp
73
# Loading work.oc8051_dptr
74
# Loading work.oc8051_psw
75
# Loading work.oc8051_ports
76
# Loading work.oc8051_int
77
# Loading work.oc8051_tc
78
# Loading work.oc8051_tc2
79
# Loading work.oc8051_xrom
80
# Loading work.oc8051_xram
81
# Loading work.tb_eth_top
82
# Loading work.tb_mii
83
# Loading work.tb_rmii
84
# Loading work.uart_agent
85
# Loading work.m25p20
86
# Loading work.memory_access
87
# Loading work.acdc_check
88
# Loading work.internal_logic
89
# Loading work.AT45DB321
90
# Loading work.tb_glbl
91
# Loading work.bit_register
92
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
93
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
94
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
95
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
96
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
97
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
98
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
99
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
100
# do run.do
101 71 dinesha
# i : 02
102 62 dinesha
# i : 00
103 71 dinesha
# i : 08
104
# i : 12
105 62 dinesha
# i : 00
106 71 dinesha
# i : 64
107
# i : 80
108
# i : fe
109
# i : 75
110
# i : 81
111 62 dinesha
# NOTE : Load memory with Initial delivery content
112
# NOTE : Initial Load End
113
# NOTE: COMMUNICATION (RE)STARTED
114
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 00114501
115 71 dinesha
# Config-Write: Id: 1 Addr = 0008, Cfg. Data = 00001616
116 62 dinesha
# Clock period configured = 40 ns, data width = 4
117
# Config-Write: Id: 1 Addr = 0024, Cfg. Data = 70407000
118
# Status: End of Transmission Loop
119 71 dinesha
# 1260 ns: Starting packet transmission to MAC, size = 64
120 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
121
# Contents:
122
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 24 81
123
# 09 63 0d 8d 65 12 01 0d 76 3d ed 8c f9 c6 c5 aa
124
# e5 77 12 8f f2 ce e8 c5 5c bd 2d 65 63 0a 80 20
125
# aa 9d 96 13 0d 53 6b d5 02 ae 1d cf 21 4c 4b 3d
126
# ****
127 71 dinesha
#              7020000 ns: Completed packet transmission to MAC
128
# 8060 ns: Starting packet transmission to MAC, size = 65
129 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
130
# Contents:
131
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 23 0a
132
# ca 3c f2 8a 41 d8 78 89 eb b6 c6 ae bc 2a 0b 71
133
# 85 4f 3b 3a 7e 15 f1 d9 62 4c 9f 8f f8 b7 9f 5c
134
# 5b 89 49 d0 d7 51 96 0c c2 c8 77 3d 12 fb 72 d9
135
# bb
136
# ****
137 71 dinesha
#             13900000 ns: Completed packet transmission to MAC
138 62 dinesha
# Status: End of Waiting Event Loop
139 71 dinesha
# 14940 ns: Starting packet transmission to MAC, size = 66
140 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
141
# Contents:
142
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 7e 6d
143
# 39 1f d3 85 78 5b 49 3f 2a 58 86 8e 9c fa 26 73
144
# a3 2f b3 5f 44 f7 cb e6 5a 29 ed da 65 b5 df 79
145
# 44 d0 2a ab 0e dc 9a fd c3 56 4e 67 0a b6 6f 99
146
# f0 ca
147
# ****
148 71 dinesha
#             20860000 ns: Completed packet transmission to MAC
149
# 21900 ns: Starting packet transmission to MAC, size = 67
150 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
151
# Contents:
152
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 38 79
153
# b8 94 93 04 59 db 4d d9 6d 76 ca b6 95 46 04 f7
154
# 69 b4 88 28 2d c7 2e 08 1c fd 29 1c 86 da 3d 66
155
# 70 73 ba 5e fa d5 1a b9 37 96 c0 26 b6 7d dc e1
156
# d6 98 d3
157
# ****
158 71 dinesha
#             27900000 ns: Completed packet transmission to MAC
159
# 28940 ns: Starting packet transmission to MAC, size = 68
160 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
161
# Contents:
162
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 86 78
163
# 7e db cf 79 fa 61 17 a1 86 50 f5 35 29 c1 c5 98
164
# 4b 73 ec 8a 4e a8 a9 a1 0e e6 9f 2a 2a 8d 9e 38
165
# 79 c8 ca 13 6b c7 b6 ba c4 b9 92 b4 7f 86 fa f2
166
# d8 8a 95 46
167
# ****
168 71 dinesha
#             35020000 ns: Completed packet transmission to MAC
169
# 36060 ns: Starting packet transmission to MAC, size = 69
170 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
171
# Contents:
172
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 32 bd
173
# 84 e4 ca a9 a1 8e fb 0b ef c9 36 75 8f 6b 88 ae
174
# 9b 92 28 2d 4b c2 1e 0d ec 18 d1 86 41 3b d8 53
175
# 56 5b e2 04 73 d8 12 b8 39 e5 a1 2b 81 c8 27 a1
176
# 1f dd 21 ca 31
177
# ****
178 71 dinesha
#             42220000 ns: Completed packet transmission to MAC
179
# 43260 ns: Starting packet transmission to MAC, size = 70
180 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
181
# Contents:
182
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 04 58
183
# 96 14 12 96 b1 55 ed 2b f5 ad 27 84 a7 e7 b9 49
184
# db c9 51 a1 2a fa 45 83 7c 72 fe 68 6f 86 f0 38
185
# 40 28 f6 c5 c0 74 39 b0 3c 2a 62 15 e1 17 43 c9
186
# 86 25 ec 93 f7 b6
187
# ****
188 71 dinesha
#             49500000 ns: Completed packet transmission to MAC
189
# 50540 ns: Starting packet transmission to MAC, size = 71
190 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
191
# Contents:
192
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 c1 8d
193
# 5a 07 2c 0c 71 3b b6 f7 9e 5c 55 20 a0 72 b4 dd
194
# 0d 4b 79 9e fd 7b 8f 03 e3 1d b1 44 95 e0 ed 52
195
# f8 8d 52 84 46 8c 90 17 6a 84 aa 7c 60 ba 8b a6
196
# 25 32 a2 b2 82 de 56
197
# ****
198 71 dinesha
#             56860000 ns: Completed packet transmission to MAC
199
# 57900 ns: Starting packet transmission to MAC, size = 72
200 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
201
# Contents:
202
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 49 14
203
# 3d 4b 5c 47 86 39 b4 d0 2c 8c 07 6a 11 e8 4b 73
204
# ec 23 a4 c9 39 df d4 67 9d b0 82 49 d9 20 1c 93
205
# e3 2a c8 5d 3a 84 2b 39 12 52 59 d0 6e 97 db a6
206
# bb 00 0f 69 16 8d 9c 08
207
# ****
208 71 dinesha
#             64300000 ns: Completed packet transmission to MAC
209
# 65340 ns: Starting packet transmission to MAC, size = 73
210 62 dinesha
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
211
# Contents:
212
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 0c 59
213
# c5 cf 90 51 69 77 4a d8 9b c4 b8 b7 86 30 77 b5
214
# d4 07 76 e9 8b 01 db 80 c2 c5 30 af 66 af e9 f8
215
# 06 ef e1 95 ee 60 e5 28 64 29 e1 77 6e 81 d5 68
216
# f0 aa 0f f1 7d 1f 08 38 e7
217
# ****
218 71 dinesha
#             71820000 ns: Completed packet transmission to MAC
219 62 dinesha
# Status: End of Waiting Delay Loop
220
#############################
221
#    TB MII Statistic
222
#  TB TO DUT :
223
#      Frm cnt       :          10
224
#      Byte cnt      :         685
225
#  DUT TO TB :
226 71 dinesha
#      Frm cnt       :           0
227
#      Byte cnt      :           0
228 62 dinesha
#      Pause Frm  cnt:           0
229
#      Alig Err   cnt:           0
230
#      usized Err cnt:           0
231
#      crc Err    cnt:           0
232 71 dinesha
#      Length Err cnt:           0
233 62 dinesha
#############################
234 71 dinesha
# A200 TB =>            171820000 ns ERROR :: tb_top.tb_glbl.test_err ERROR detected          1
235
# A200 TB =>            171820000 ns ERROR :: tb_top.tb_glbl.test_err ERROR detected          2
236 62 dinesha
#
237
# -------------------------------------------------
238
# Test Status
239 71 dinesha
# warnings: 0, errors: 2
240 62 dinesha
#
241
# -------------------------------------------------
242
# Test Status
243 71 dinesha
# warnings: 0, errors: 2
244 62 dinesha
#
245
# =========
246 71 dinesha
# Test Status: TEST FAILED
247 62 dinesha
# =========
248
#
249
# ** Note: $finish    : ../../verif/lib/tb_glbl.v(64)
250 71 dinesha
#    Time: 172821 ns  Iteration: 0  Instance: /tb_top

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.