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[/] [turbo8051/] [trunk/] [verif/] [log/] [int_divmul.log] - Blame information for rev 76

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Line No. Rev Author Line
1 76 dinesha
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
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# 10.1b
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# vsim +INTERNAL_ROM -do run.do -c tb_top
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# //  ModelSim ACTEL 10.1b Apr 27 2012
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# //
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# //  Copyright 1991-2012 Mentor Graphics Corporation
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# //  All Rights Reserved.
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# //
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# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
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# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
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# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
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# //
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# Loading sv_std.std
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# Loading work.tb_top
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# Loading work.digital_core
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# Loading work.clkgen
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# Loading work.clk_ctl
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# Loading work.wb_crossbar
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# Loading work.g_mac_top
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# Loading work.g_dpath_ctrl
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# Loading work.g_eth_parser
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# Loading work.g_mac_core
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# Loading work.g_rx_top
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# Loading work.g_rx_fsm
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# Loading work.half_dup_dble_reg
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# Loading work.g_rx_crc32
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# Loading work.g_deferral_rx
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# Loading work.g_md_intf
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# Loading work.g_tx_top
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# Loading work.g_deferral
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# Loading work.g_tx_fsm
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# Loading work.g_tx_crc32
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# Loading work.toggle_sync
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# Loading work.g_cfg_mgmt
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# Loading work.s2f_sync
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# Loading work.generic_register
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# Loading work.req_register
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# Loading work.stat_counter
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# Loading work.generic_intr_stat_reg
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# Loading work.g_mii_intf
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# Loading work.async_fifo
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# Loading work.wb_rd_mem2mem
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# Loading work.wb_wr_mem2mem
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# Loading work.uart_core
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# Loading work.uart_cfg
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# Loading work.stat_register
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# Loading work.uart_txfsm
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# Loading work.uart_rxfsm
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# Loading work.double_sync_low
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# Loading work.spi_core
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# Loading work.spi_if
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# Loading work.spi_ctl
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# Loading work.spi_cfg
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# Loading work.oc8051_top
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# Loading work.oc8051_decoder
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# Loading work.oc8051_alu
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# Loading work.oc8051_multiply
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# Loading work.oc8051_divide
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# Loading work.oc8051_ram_top
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# Loading work.oc8051_ram_256x8_two_bist
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# Loading work.oc8051_alu_src_sel
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# Loading work.oc8051_comp
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# Loading work.oc8051_cy_select
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# Loading work.oc8051_indi_addr
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# Loading work.oc8051_memory_interface
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# Loading work.oc8051_sfr
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# Loading work.oc8051_acc
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# Loading work.oc8051_b_register
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# Loading work.oc8051_sp
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# Loading work.oc8051_dptr
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# Loading work.oc8051_psw
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# Loading work.oc8051_ports
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# Loading work.oc8051_int
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# Loading work.oc8051_tc
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# Loading work.oc8051_tc2
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# Loading work.oc8051_xrom
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# Loading work.oc8051_xram
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# Loading work.tb_eth_top
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# Loading work.tb_mii
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# Loading work.tb_rmii
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# Loading work.uart_agent
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# Loading work.m25p20
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# Loading work.memory_access
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# Loading work.acdc_check
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# Loading work.internal_logic
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# Loading work.AT45DB321
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# Loading work.tb_glbl
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# Loading work.bit_register
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# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(397): [TOFD] - System task or function '$shm_open' is not defined.
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#
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#         Region: /tb_top
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# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(398): [TOFD] - System task or function '$shm_probe' is not defined.
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#
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#         Region: /tb_top
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# ** Warning: (vsim-3017) ../tb/tb_top.v(235): [TFMPC] - Too few port connections. Expected 50, found 44.
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#
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#         Region: /tb_top/u_core
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# ** Warning: (vsim-3015) ../tb/tb_top.v(235): [PCDPC] - Port size (8 or 8) does not match connection size (4) for port 'phy_txd'. The port definition is at: ../../rtl/core/digital_core.v(29).
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#
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#         Region: /tb_top/u_core
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# ** Warning: (vsim-3015) ../tb/tb_top.v(235): [PCDPC] - Port size (8 or 8) does not match connection size (4) for port 'phy_rxd'. The port definition is at: ../../rtl/core/digital_core.v(35).
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#
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#         Region: /tb_top/u_core
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'scan_mode'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'scan_enable'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_clk'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_in'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_out'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_out_en'.
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#
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# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(214): [TFMPC] - Too few port connections. Expected 14, found 12.
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#
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#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(214): [TFMPC] - Missing connection for port 'afull'.
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#
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(214): [TFMPC] - Missing connection for port 'aempty'.
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#
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# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(230): [TFMPC] - Too few port connections. Expected 14, found 12.
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#
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#         Region: /tb_top/u_core/u_uart_core/u_txfifo
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(230): [TFMPC] - Missing connection for port 'afull'.
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#
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(230): [TFMPC] - Missing connection for port 'aempty'.
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#
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# do run.do
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# i : 02
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# i : 00
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# i : 08
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# i : 12
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# i : 00
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# i : 64
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# i : 80
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# i : fe
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# i : 75
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# i : 81
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# NOTE : Load memory with Initial delivery content
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# NOTE : Initial Load End
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# --> Dumpping the design
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# NOTE: COMMUNICATION (RE)STARTED
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################################
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# time                45976 Passed
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################################

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