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[/] [turbo8051/] [trunk/] [verif/] [log/] [run_modelsim.log] - Blame information for rev 78

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Line No. Rev Author Line
1 62 dinesha 
 Compiling with MODELSIM
2 
Model Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov  2 2010
3 
-- Compiling module tb_top
4 
-- Compiling module tb_glbl
5 
-- Compiling module tb_eth_top
6 
-- Compiling module tb_mii
7 
-- Compiling module tb_rmii
8 
-- Compiling module uart_agent
9 
-- Compiling module AT45DB321
10 
-- Compiling module acdc_check
11 
-- Compiling module internal_logic
12 
-- Compiling module memory_access
13 
-- Compiling module m25p20
14 
-- Compiling module oc8051_xram
15 
-- Compiling module oc8051_xrom
16 
-- Compiling module turbo8051
17 
-- Compiling module g_mac_top
18 
-- Compiling module half_dup_dble_reg
19 
-- Compiling module g_tx_fsm
20 
-- Compiling module g_deferral
21 
-- Compiling module g_tx_top
22 
-- Compiling module g_rx_fsm
23 
-- Compiling module g_cfg_mgmt
24 
-- Compiling module s2f_sync
25 
-- Compiling module g_md_intf
26 
-- Compiling module g_deferral_rx
27 
-- Compiling module g_rx_top
28 
-- Compiling module g_mii_intf
29 
-- Compiling module g_mac_core
30 
-- Compiling module g_eth_parser
31 
-- Compiling module g_rx_crc32
32 
-- Compiling module g_tx_crc32
33 
-- Compiling module async_fifo
34 
-- Compiling module g_dpath_ctrl
35 
-- Compiling module spi_core
36 
-- Compiling module spi_ctl
37 
-- Compiling module spi_if
38 
-- Compiling module spi_cfg
39 
-- Compiling module uart_rxfsm
40 
-- Compiling module uart_txfsm
41 
-- Compiling module uart_core
42 
-- Compiling module uart_cfg
43 
-- Compiling module clkgen
44 
-- Compiling module clk_ctl
45 
-- Compiling module wb_crossbar
46 
-- Compiling module wb_rd_mem2mem
47 
-- Compiling module wb_wr_mem2mem
48 
-- Compiling module oc8051_top
49 
-- Compiling module oc8051_rom
50 
-- Compiling module oc8051_alu_src_sel
51 
-- Compiling module oc8051_alu
52 
-- Compiling module oc8051_decoder
53 
-- Compiling module oc8051_divide
54 
-- Compiling module oc8051_multiply
55 
-- Compiling module oc8051_memory_interface
56 
-- Compiling module oc8051_ram_top
57 
-- Compiling module oc8051_acc
58 
-- Compiling module oc8051_comp
59 
-- Compiling module oc8051_sp
60 
-- Compiling module oc8051_dptr
61 
-- Compiling module oc8051_cy_select
62 
-- Compiling module oc8051_psw
63 
-- Compiling module oc8051_indi_addr
64 
-- Compiling module oc8051_ports
65 
-- Compiling module oc8051_b_register
66 
-- Compiling module oc8051_uart
67 
-- Compiling module oc8051_int
68 
-- Compiling module oc8051_tc
69 
-- Compiling module oc8051_tc2
70 
-- Compiling module oc8051_sfr
71 
-- Compiling module oc8051_ram_256x8_two_bist
72 
-- Scanning library file '../../rtl/lib/registers.v'
73 
-- Compiling module req_register
74 
-- Compiling module stat_register
75 
-- Compiling module generic_register
76 
-- Compiling module generic_intr_stat_reg
77 
-- Scanning library file '../../rtl/lib/stat_counter.v'
78 
-- Compiling module stat_counter
79 
-- Scanning library file '../../rtl/lib/toggle_sync.v'
80 
-- Compiling module toggle_sync
81 
-- Scanning library file '../../rtl/lib/double_sync_low.v'
82 
-- Compiling module double_sync_low
83 
-- Scanning library file '../../rtl/lib/async_fifo.v'
84 
-- Scanning library file '../../rtl/lib/registers.v'
85 
-- Compiling module bit_register
86 
-- Scanning library file '../../rtl/lib/stat_counter.v'
87 
-- Scanning library file '../../rtl/lib/toggle_sync.v'
88 
-- Scanning library file '../../rtl/lib/double_sync_low.v'
89 
-- Scanning library file '../../rtl/lib/async_fifo.v'
90 
 
91 
Top level modules:
92 
        tb_top
93 
        oc8051_uart
94 
#### Compile : PASSED
95 
 
96 
###########################################
97 
 Runing GMAC/SPI/UART test programs
98 
###########################################
99 
###########################################
100 
### Running test 1: gmac_test_2
101 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
102 
 
103 
# 6.6d
104 
 
105 
# vsim +gmac_test_2 -do run.do -c tb_top
106 
# //  ModelSim ACTEL 6.6d Nov  2 2010
107 
# //
108 
# //  Copyright 1991-2010 Mentor Graphics Corporation
109 
# //              All Rights Reserved.
110 
# //
111 
# //  THIS WORK CONTAINS TRADE SECRET AND
112 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
113 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
114 
# //  AND IS SUBJECT TO LICENSE TERMS.
115 
# //
116 
# Loading sv_std.std
117 
# Loading work.tb_top
118 
# Loading work.turbo8051
119 
# Loading work.clkgen
120 
# Loading work.clk_ctl
121 
# Loading work.wb_crossbar
122 
# Loading work.g_mac_top
123 
# Loading work.g_dpath_ctrl
124 
# Loading work.g_eth_parser
125 
# Loading work.g_mac_core
126 
# Loading work.g_rx_top
127 
# Loading work.g_rx_fsm
128 
# Loading work.half_dup_dble_reg
129 
# Loading work.g_rx_crc32
130 
# Loading work.g_deferral_rx
131 
# Loading work.g_md_intf
132 
# Loading work.g_tx_top
133 
# Loading work.g_deferral
134 
# Loading work.g_tx_fsm
135 
# Loading work.g_tx_crc32
136 
# Loading work.toggle_sync
137 
# Loading work.g_cfg_mgmt
138 
# Loading work.s2f_sync
139 
# Loading work.generic_register
140 
# Loading work.req_register
141 
# Loading work.stat_counter
142 
# Loading work.generic_intr_stat_reg
143 
# Loading work.g_mii_intf
144 
# Loading work.async_fifo
145 
# Loading work.wb_rd_mem2mem
146 
# Loading work.wb_wr_mem2mem
147 
# Loading work.uart_core
148 
# Loading work.uart_cfg
149 
# Loading work.stat_register
150 
# Loading work.uart_txfsm
151 
# Loading work.uart_rxfsm
152 
# Loading work.double_sync_low
153 
# Loading work.spi_core
154 
# Loading work.spi_if
155 
# Loading work.spi_ctl
156 
# Loading work.spi_cfg
157 
# Loading work.oc8051_top
158 
# Loading work.oc8051_decoder
159 
# Loading work.oc8051_alu
160 
# Loading work.oc8051_multiply
161 
# Loading work.oc8051_divide
162 
# Loading work.oc8051_ram_top
163 
# Loading work.oc8051_ram_256x8_two_bist
164 
# Loading work.oc8051_alu_src_sel
165 
# Loading work.oc8051_comp
166 
# Loading work.oc8051_rom
167 
# Loading work.oc8051_cy_select
168 
# Loading work.oc8051_indi_addr
169 
# Loading work.oc8051_memory_interface
170 
# Loading work.oc8051_sfr
171 
# Loading work.oc8051_acc
172 
# Loading work.oc8051_b_register
173 
# Loading work.oc8051_sp
174 
# Loading work.oc8051_dptr
175 
# Loading work.oc8051_psw
176 
# Loading work.oc8051_ports
177 
# Loading work.oc8051_int
178 
# Loading work.oc8051_tc
179 
# Loading work.oc8051_tc2
180 
# Loading work.oc8051_xrom
181 
# Loading work.oc8051_xram
182 
# Loading work.tb_eth_top
183 
# Loading work.tb_mii
184 
# Loading work.tb_rmii
185 
# Loading work.uart_agent
186 
# Loading work.m25p20
187 
# Loading work.memory_access
188 
# Loading work.acdc_check
189 
# Loading work.internal_logic
190 
# Loading work.AT45DB321
191 
# Loading work.tb_glbl
192 
# Loading work.bit_register
193 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
194 
#           File in use by:   Hostname:   ProcessID: 14
195 
#           Attempting to use alternate WLF file "./wlftqqzjr8".
196 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
197 
#           Using alternate file: ./wlftqqzjr8
198 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
199 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
200 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
201 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
202 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
203 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
204 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
205 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
206 
# do run.do
207 
# i : 00
208 
# i : 00
209 
# i : 00
210 
# i : 00
211 
# i : 00
212 
# i : 00
213 
# i : 00
214 
# i : 00
215 
# i : 00
216 
# i : 00
217 
# NOTE : Load memory with Initial delivery content
218 
# NOTE : Initial Load End
219 
# NOTE: COMMUNICATION (RE)STARTED
220 
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 00114501
221 
# Clock period configured = 40 ns, data width = 4
222 
# Config-Write: Id: 1 Addr = 0008, Cfg. Data = 00001616
223 
# Config-Write: Id: 1 Addr = 0024, Cfg. Data = 70407000
224 
# Status: End of Transmission Loop
225 
# 1300 ns: Starting packet transmission to MAC, size = 64
226 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
227 
# Contents:
228 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 24 81
229 
# 09 63 0d 8d 65 12 01 0d 76 3d ed 8c f9 c6 c5 aa
230 
# e5 77 12 8f f2 ce e8 c5 5c bd 2d 65 63 0a 80 20
231 
# aa 9d 96 13 0d 53 6b d5 02 ae 1d cf 21 4c 4b 3d
232 
# ****
233 
#              7060000 ns: Completed packet transmission to MAC
234 
# 8100 ns: Starting packet transmission to MAC, size = 65
235 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
236 
# Contents:
237 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 23 0a
238 
# ca 3c f2 8a 41 d8 78 89 eb b6 c6 ae bc 2a 0b 71
239 
# 85 4f 3b 3a 7e 15 f1 d9 62 4c 9f 8f f8 b7 9f 5c
240 
# 5b 89 49 d0 d7 51 96 0c c2 c8 77 3d 12 fb 72 d9
241 
# bb
242 
# ****
243 
#             13940000 ns: Completed packet transmission to MAC
244 
# Status: End of Waiting Event Loop
245 
# 14980 ns: Starting packet transmission to MAC, size = 66
246 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
247 
# Contents:
248 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 7e 6d
249 
# 39 1f d3 85 78 5b 49 3f 2a 58 86 8e 9c fa 26 73
250 
# a3 2f b3 5f 44 f7 cb e6 5a 29 ed da 65 b5 df 79
251 
# 44 d0 2a ab 0e dc 9a fd c3 56 4e 67 0a b6 6f 99
252 
# f0 ca
253 
# ****
254 
#             20900000 ns: Completed packet transmission to MAC
255 
# 21940 ns: Starting packet transmission to MAC, size = 67
256 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
257 
# Contents:
258 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 38 79
259 
# b8 94 93 04 59 db 4d d9 6d 76 ca b6 95 46 04 f7
260 
# 69 b4 88 28 2d c7 2e 08 1c fd 29 1c 86 da 3d 66
261 
# 70 73 ba 5e fa d5 1a b9 37 96 c0 26 b6 7d dc e1
262 
# d6 98 d3
263 
# ****
264 
#             27940000 ns: Completed packet transmission to MAC
265 
# 28980 ns: Starting packet transmission to MAC, size = 68
266 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
267 
# Contents:
268 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 86 78
269 
# 7e db cf 79 fa 61 17 a1 86 50 f5 35 29 c1 c5 98
270 
# 4b 73 ec 8a 4e a8 a9 a1 0e e6 9f 2a 2a 8d 9e 38
271 
# 79 c8 ca 13 6b c7 b6 ba c4 b9 92 b4 7f 86 fa f2
272 
# d8 8a 95 46
273 
# ****
274 
#             35060000 ns: Completed packet transmission to MAC
275 
# 35180 ns: Preamble detected, last IFG = 3518 bits
276 
# 35781 ns: SFD received, last IFG = 3518 bits
277 
# 36100 ns: Starting packet transmission to MAC, size = 69
278 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
279 
# Contents:
280 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 32 bd
281 
# 84 e4 ca a9 a1 8e fb 0b ef c9 36 75 8f 6b 88 ae
282 
# 9b 92 28 2d 4b c2 1e 0d ec 18 d1 86 41 3b d8 53
283 
# 56 5b e2 04 73 d8 12 b8 39 e5 a1 2b 81 c8 27 a1
284 
# 1f dd 21 ca 31
285 
# ****
286 
# 40900 ns: Received packet, size = 64
287 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
288 
# Length error, type/length field = 1792, expected value = 46
289 
# Contents:
290 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 24 81
291 
# 09 63 0d 8d 65 12 01 0d 76 3d ed 8c f9 c6 c5 aa
292 
# e5 77 12 8f f2 ce e8 c5 5c bd 2d 65 63 0a 80 20
293 
# aa 9d 96 13 0d 53 6b d5 02 ae 1d cf 21 4c 4b 3d
294 
# ****
295 
# 41900 ns: Preamble detected, last IFG = 96 bits
296 
#             42260000 ns: Completed packet transmission to MAC
297 
# 42501 ns: SFD received, last IFG = 96 bits
298 
# 43300 ns: Starting packet transmission to MAC, size = 70
299 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
300 
# Contents:
301 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 04 58
302 
# 96 14 12 96 b1 55 ed 2b f5 ad 27 84 a7 e7 b9 49
303 
# db c9 51 a1 2a fa 45 83 7c 72 fe 68 6f 86 f0 38
304 
# 40 28 f6 c5 c0 74 39 b0 3c 2a 62 15 e1 17 43 c9
305 
# 86 25 ec 93 f7 b6
306 
# ****
307 
# 47700 ns: Received packet, size = 65
308 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
309 
# Length error, type/length field = 1792, expected value = 47
310 
# Contents:
311 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 23 0a
312 
# ca 3c f2 8a 41 d8 78 89 eb b6 c6 ae bc 2a 0b 71
313 
# 85 4f 3b 3a 7e 15 f1 d9 62 4c 9f 8f f8 b7 9f 5c
314 
# 5b 89 49 d0 d7 51 96 0c c2 c8 77 3d 12 fb 72 d9
315 
# bb
316 
# ****
317 
# 48700 ns: Preamble detected, last IFG = 96 bits
318 
# 49301 ns: SFD received, last IFG = 96 bits
319 
#             49540000 ns: Completed packet transmission to MAC
320 
# 50580 ns: Starting packet transmission to MAC, size = 71
321 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
322 
# Contents:
323 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 c1 8d
324 
# 5a 07 2c 0c 71 3b b6 f7 9e 5c 55 20 a0 72 b4 dd
325 
# 0d 4b 79 9e fd 7b 8f 03 e3 1d b1 44 95 e0 ed 52
326 
# f8 8d 52 84 46 8c 90 17 6a 84 aa 7c 60 ba 8b a6
327 
# 25 32 a2 b2 82 de 56
328 
# ****
329 
# 54580 ns: Received packet, size = 66
330 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
331 
# Length error, type/length field = 1792, expected value = 48
332 
# Contents:
333 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 7e 6d
334 
# 39 1f d3 85 78 5b 49 3f 2a 58 86 8e 9c fa 26 73
335 
# a3 2f b3 5f 44 f7 cb e6 5a 29 ed da 65 b5 df 79
336 
# 44 d0 2a ab 0e dc 9a fd c3 56 4e 67 0a b6 6f 99
337 
# f0 ca
338 
# ****
339 
# 55580 ns: Preamble detected, last IFG = 96 bits
340 
# 56181 ns: SFD received, last IFG = 96 bits
341 
#             56900000 ns: Completed packet transmission to MAC
342 
# 57940 ns: Starting packet transmission to MAC, size = 72
343 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
344 
# Contents:
345 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 49 14
346 
# 3d 4b 5c 47 86 39 b4 d0 2c 8c 07 6a 11 e8 4b 73
347 
# ec 23 a4 c9 39 df d4 67 9d b0 82 49 d9 20 1c 93
348 
# e3 2a c8 5d 3a 84 2b 39 12 52 59 d0 6e 97 db a6
349 
# bb 00 0f 69 16 8d 9c 08
350 
# ****
351 
# 61540 ns: Received packet, size = 67
352 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
353 
# Length error, type/length field = 1792, expected value = 49
354 
# Contents:
355 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 38 79
356 
# b8 94 93 04 59 db 4d d9 6d 76 ca b6 95 46 04 f7
357 
# 69 b4 88 28 2d c7 2e 08 1c fd 29 1c 86 da 3d 66
358 
# 70 73 ba 5e fa d5 1a b9 37 96 c0 26 b6 7d dc e1
359 
# d6 98 d3
360 
# ****
361 
# 62540 ns: Preamble detected, last IFG = 96 bits
362 
# 63141 ns: SFD received, last IFG = 96 bits
363 
#             64340000 ns: Completed packet transmission to MAC
364 
# 65380 ns: Starting packet transmission to MAC, size = 73
365 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
366 
# Contents:
367 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 0c 59
368 
# c5 cf 90 51 69 77 4a d8 9b c4 b8 b7 86 30 77 b5
369 
# d4 07 76 e9 8b 01 db 80 c2 c5 30 af 66 af e9 f8
370 
# 06 ef e1 95 ee 60 e5 28 64 29 e1 77 6e 81 d5 68
371 
# f0 aa 0f f1 7d 1f 08 38 e7
372 
# ****
373 
# 68580 ns: Received packet, size = 68
374 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
375 
# Length error, type/length field = 1792, expected value = 50
376 
# Contents:
377 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 86 78
378 
# 7e db cf 79 fa 61 17 a1 86 50 f5 35 29 c1 c5 98
379 
# 4b 73 ec 8a 4e a8 a9 a1 0e e6 9f 2a 2a 8d 9e 38
380 
# 79 c8 ca 13 6b c7 b6 ba c4 b9 92 b4 7f 86 fa f2
381 
# d8 8a 95 46
382 
# ****
383 
# 69580 ns: Preamble detected, last IFG = 96 bits
384 
# 70181 ns: SFD received, last IFG = 96 bits
385 
#             71860000 ns: Completed packet transmission to MAC
386 
# 75700 ns: Received packet, size = 69
387 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
388 
# Length error, type/length field = 1792, expected value = 51
389 
# Contents:
390 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 32 bd
391 
# 84 e4 ca a9 a1 8e fb 0b ef c9 36 75 8f 6b 88 ae
392 
# 9b 92 28 2d 4b c2 1e 0d ec 18 d1 86 41 3b d8 53
393 
# 56 5b e2 04 73 d8 12 b8 39 e5 a1 2b 81 c8 27 a1
394 
# 1f dd 21 ca 31
395 
# ****
396 
# 76700 ns: Preamble detected, last IFG = 96 bits
397 
# 77301 ns: SFD received, last IFG = 96 bits
398 
# 82900 ns: Received packet, size = 70
399 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
400 
# Length error, type/length field = 1792, expected value = 52
401 
# Contents:
402 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 04 58
403 
# 96 14 12 96 b1 55 ed 2b f5 ad 27 84 a7 e7 b9 49
404 
# db c9 51 a1 2a fa 45 83 7c 72 fe 68 6f 86 f0 38
405 
# 40 28 f6 c5 c0 74 39 b0 3c 2a 62 15 e1 17 43 c9
406 
# 86 25 ec 93 f7 b6
407 
# ****
408 
# 83900 ns: Preamble detected, last IFG = 96 bits
409 
# 84501 ns: SFD received, last IFG = 96 bits
410 
# 90180 ns: Received packet, size = 71
411 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
412 
# Length error, type/length field = 1792, expected value = 53
413 
# Contents:
414 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 c1 8d
415 
# 5a 07 2c 0c 71 3b b6 f7 9e 5c 55 20 a0 72 b4 dd
416 
# 0d 4b 79 9e fd 7b 8f 03 e3 1d b1 44 95 e0 ed 52
417 
# f8 8d 52 84 46 8c 90 17 6a 84 aa 7c 60 ba 8b a6
418 
# 25 32 a2 b2 82 de 56
419 
# ****
420 
# 91180 ns: Preamble detected, last IFG = 96 bits
421 
# 91781 ns: SFD received, last IFG = 96 bits
422 
# 97540 ns: Received packet, size = 72
423 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
424 
# Length error, type/length field = 1792, expected value = 54
425 
# Contents:
426 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 49 14
427 
# 3d 4b 5c 47 86 39 b4 d0 2c 8c 07 6a 11 e8 4b 73
428 
# ec 23 a4 c9 39 df d4 67 9d b0 82 49 d9 20 1c 93
429 
# e3 2a c8 5d 3a 84 2b 39 12 52 59 d0 6e 97 db a6
430 
# bb 00 0f 69 16 8d 9c 08
431 
# ****
432 
# 98540 ns: Preamble detected, last IFG = 96 bits
433 
# 99141 ns: SFD received, last IFG = 96 bits
434 
# 104980 ns: Received packet, size = 73
435 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
436 
# Length error, type/length field = 1792, expected value = 55
437 
# Contents:
438 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 0c 59
439 
# c5 cf 90 51 69 77 4a d8 9b c4 b8 b7 86 30 77 b5
440 
# d4 07 76 e9 8b 01 db 80 c2 c5 30 af 66 af e9 f8
441 
# 06 ef e1 95 ee 60 e5 28 64 29 e1 77 6e 81 d5 68
442 
# f0 aa 0f f1 7d 1f 08 38 e7
443 
# ****
444 
# Status: End of Waiting Delay Loop
445 
#############################
446 
#    TB MII Statistic
447 
#  TB TO DUT :
448 
#      Frm cnt       :          10
449 
#      Byte cnt      :         685
450 
#  DUT TO TB :
451 
#      Frm cnt       :          10
452 
#      Byte cnt      :         685
453 
#      Pause Frm  cnt:           0
454 
#      Alig Err   cnt:           0
455 
#      usized Err cnt:           0
456 
#      crc Err    cnt:           0
457 
#      Length Err cnt:          10
458 
#############################
459 
#
460 
# -------------------------------------------------
461 
# Test Status
462 
# warnings: 0, errors: 0
463 
#
464 
# -------------------------------------------------
465 
# Test Status
466 
# warnings: 0, errors: 0
467 
#
468 
# =========
469 
# Test Status: TEST PASSED
470 
# =========
471 
#
472 
# ** Note: $finish    : ../../verif/lib/tb_glbl.v(64)
473 
#    Time: 172861 ns  Iteration: 0  Instance: /tb_top
474 
### test 1: gmac_test_2 --> PASSED
475 
### Running test 2: gmac_test_1
476 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
477 
 
478 
# 6.6d
479 
 
480 
# vsim +gmac_test_1 -do run.do -c tb_top
481 
# //  ModelSim ACTEL 6.6d Nov  2 2010
482 
# //
483 
# //  Copyright 1991-2010 Mentor Graphics Corporation
484 
# //              All Rights Reserved.
485 
# //
486 
# //  THIS WORK CONTAINS TRADE SECRET AND
487 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
488 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
489 
# //  AND IS SUBJECT TO LICENSE TERMS.
490 
# //
491 
# Loading sv_std.std
492 
# Loading work.tb_top
493 
# Loading work.turbo8051
494 
# Loading work.clkgen
495 
# Loading work.clk_ctl
496 
# Loading work.wb_crossbar
497 
# Loading work.g_mac_top
498 
# Loading work.g_dpath_ctrl
499 
# Loading work.g_eth_parser
500 
# Loading work.g_mac_core
501 
# Loading work.g_rx_top
502 
# Loading work.g_rx_fsm
503 
# Loading work.half_dup_dble_reg
504 
# Loading work.g_rx_crc32
505 
# Loading work.g_deferral_rx
506 
# Loading work.g_md_intf
507 
# Loading work.g_tx_top
508 
# Loading work.g_deferral
509 
# Loading work.g_tx_fsm
510 
# Loading work.g_tx_crc32
511 
# Loading work.toggle_sync
512 
# Loading work.g_cfg_mgmt
513 
# Loading work.s2f_sync
514 
# Loading work.generic_register
515 
# Loading work.req_register
516 
# Loading work.stat_counter
517 
# Loading work.generic_intr_stat_reg
518 
# Loading work.g_mii_intf
519 
# Loading work.async_fifo
520 
# Loading work.wb_rd_mem2mem
521 
# Loading work.wb_wr_mem2mem
522 
# Loading work.uart_core
523 
# Loading work.uart_cfg
524 
# Loading work.stat_register
525 
# Loading work.uart_txfsm
526 
# Loading work.uart_rxfsm
527 
# Loading work.double_sync_low
528 
# Loading work.spi_core
529 
# Loading work.spi_if
530 
# Loading work.spi_ctl
531 
# Loading work.spi_cfg
532 
# Loading work.oc8051_top
533 
# Loading work.oc8051_decoder
534 
# Loading work.oc8051_alu
535 
# Loading work.oc8051_multiply
536 
# Loading work.oc8051_divide
537 
# Loading work.oc8051_ram_top
538 
# Loading work.oc8051_ram_256x8_two_bist
539 
# Loading work.oc8051_alu_src_sel
540 
# Loading work.oc8051_comp
541 
# Loading work.oc8051_rom
542 
# Loading work.oc8051_cy_select
543 
# Loading work.oc8051_indi_addr
544 
# Loading work.oc8051_memory_interface
545 
# Loading work.oc8051_sfr
546 
# Loading work.oc8051_acc
547 
# Loading work.oc8051_b_register
548 
# Loading work.oc8051_sp
549 
# Loading work.oc8051_dptr
550 
# Loading work.oc8051_psw
551 
# Loading work.oc8051_ports
552 
# Loading work.oc8051_int
553 
# Loading work.oc8051_tc
554 
# Loading work.oc8051_tc2
555 
# Loading work.oc8051_xrom
556 
# Loading work.oc8051_xram
557 
# Loading work.tb_eth_top
558 
# Loading work.tb_mii
559 
# Loading work.tb_rmii
560 
# Loading work.uart_agent
561 
# Loading work.m25p20
562 
# Loading work.memory_access
563 
# Loading work.acdc_check
564 
# Loading work.internal_logic
565 
# Loading work.AT45DB321
566 
# Loading work.tb_glbl
567 
# Loading work.bit_register
568 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
569 
#           File in use by:   Hostname:   ProcessID: 14
570 
#           Attempting to use alternate WLF file "./wlft7gx1ee".
571 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
572 
#           Using alternate file: ./wlft7gx1ee
573 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
574 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
575 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
576 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
577 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
578 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
579 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
580 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
581 
# do run.do
582 
# i : 00
583 
# i : 00
584 
# i : 00
585 
# i : 00
586 
# i : 00
587 
# i : 00
588 
# i : 00
589 
# i : 00
590 
# i : 00
591 
# i : 00
592 
# NOTE : Load memory with Initial delivery content
593 
# NOTE : Initial Load End
594 
# NOTE: COMMUNICATION (RE)STARTED
595 
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 00114501
596 
# Clock period configured = 40 ns, data width = 4
597 
# Config-Write: Id: 1 Addr = 0008, Cfg. Data = 00001616
598 
# Config-Write: Id: 1 Addr = 0024, Cfg. Data = 70407000
599 
# 1300 ns: Starting packet transmission to MAC, size = 64
600 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
601 
# Contents:
602 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 24 81
603 
# 09 63 0d 8d 65 12 01 0d 76 3d ed 8c f9 c6 c5 aa
604 
# e5 77 12 8f f2 ce e8 c5 5c bd 2d 65 63 0a 80 20
605 
# aa 9d 96 13 0d 53 6b d5 02 ae 1d cf 21 4c 4b 3d
606 
# ****
607 
#              7060000 ns: Completed packet transmission to MAC
608 
# 8100 ns: Starting packet transmission to MAC, size = 65
609 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
610 
# Contents:
611 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 23 0a
612 
# ca 3c f2 8a 41 d8 78 89 eb b6 c6 ae bc 2a 0b 71
613 
# 85 4f 3b 3a 7e 15 f1 d9 62 4c 9f 8f f8 b7 9f 5c
614 
# 5b 89 49 d0 d7 51 96 0c c2 c8 77 3d 12 fb 72 d9
615 
# bb
616 
# ****
617 
# Config-Write: Id: 4 Addr = 7040, Cfg. Data = 28400040
618 
# 9740 ns: Preamble detected, last IFG = 974 bits
619 
# 10341 ns: SFD received, last IFG = 974 bits
620 
#             13940000 ns: Completed packet transmission to MAC
621 
# 14980 ns: Starting packet transmission to MAC, size = 66
622 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
623 
# Contents:
624 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 7e 6d
625 
# 39 1f d3 85 78 5b 49 3f 2a 58 86 8e 9c fa 26 73
626 
# a3 2f b3 5f 44 f7 cb e6 5a 29 ed da 65 b5 df 79
627 
# 44 d0 2a ab 0e dc 9a fd c3 56 4e 67 0a b6 6f 99
628 
# f0 ca
629 
# ****
630 
# Config-Write: Id: 4 Addr = 7044, Cfg. Data = 28410041
631 
# 15460 ns: Received packet, size = 64
632 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
633 
# Length error, type/length field = 1792, expected value = 46
634 
# Contents:
635 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 24 81
636 
# 09 63 0d 8d 65 12 01 0d 76 3d ed 8c f9 c6 c5 aa
637 
# e5 77 12 8f f2 ce e8 c5 5c bd 2d 65 63 0a 80 20
638 
# aa 9d 96 13 0d 53 6b d5 02 ae 1d cf 21 4c 4b 3d
639 
# ****
640 
# 16460 ns: Preamble detected, last IFG = 96 bits
641 
# 17061 ns: SFD received, last IFG = 96 bits
642 
#             20900000 ns: Completed packet transmission to MAC
643 
# 21940 ns: Starting packet transmission to MAC, size = 67
644 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
645 
# Contents:
646 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 38 79
647 
# b8 94 93 04 59 db 4d d9 6d 76 ca b6 95 46 04 f7
648 
# 69 b4 88 28 2d c7 2e 08 1c fd 29 1c 86 da 3d 66
649 
# 70 73 ba 5e fa d5 1a b9 37 96 c0 26 b6 7d dc e1
650 
# d6 98 d3
651 
# ****
652 
# Config-Write: Id: 4 Addr = 7048, Cfg. Data = 28421042
653 
# 22260 ns: Received packet, size = 65
654 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
655 
# Length error, type/length field = 1792, expected value = 47
656 
# Contents:
657 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 23 0a
658 
# ca 3c f2 8a 41 d8 78 89 eb b6 c6 ae bc 2a 0b 71
659 
# 85 4f 3b 3a 7e 15 f1 d9 62 4c 9f 8f f8 b7 9f 5c
660 
# 5b 89 49 d0 d7 51 96 0c c2 c8 77 3d 12 fb 72 d9
661 
# bb
662 
# ****
663 
# 23260 ns: Preamble detected, last IFG = 96 bits
664 
# 23861 ns: SFD received, last IFG = 96 bits
665 
#             27940000 ns: Completed packet transmission to MAC
666 
# 28980 ns: Starting packet transmission to MAC, size = 68
667 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
668 
# Contents:
669 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 86 78
670 
# 7e db cf 79 fa 61 17 a1 86 50 f5 35 29 c1 c5 98
671 
# 4b 73 ec 8a 4e a8 a9 a1 0e e6 9f 2a 2a 8d 9e 38
672 
# 79 c8 ca 13 6b c7 b6 ba c4 b9 92 b4 7f 86 fa f2
673 
# d8 8a 95 46
674 
# ****
675 
# 29140 ns: Received packet, size = 66
676 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
677 
# Length error, type/length field = 1792, expected value = 48
678 
# Contents:
679 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 7e 6d
680 
# 39 1f d3 85 78 5b 49 3f 2a 58 86 8e 9c fa 26 73
681 
# a3 2f b3 5f 44 f7 cb e6 5a 29 ed da 65 b5 df 79
682 
# 44 d0 2a ab 0e dc 9a fd c3 56 4e 67 0a b6 6f 99
683 
# f0 ca
684 
# ****
685 
# Config-Write: Id: 4 Addr = 704c, Cfg. Data = 28432043
686 
# 30580 ns: Preamble detected, last IFG = 140 bits
687 
# 31181 ns: SFD received, last IFG = 140 bits
688 
#             35060000 ns: Completed packet transmission to MAC
689 
# 36100 ns: Starting packet transmission to MAC, size = 69
690 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
691 
# Contents:
692 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 32 bd
693 
# 84 e4 ca a9 a1 8e fb 0b ef c9 36 75 8f 6b 88 ae
694 
# 9b 92 28 2d 4b c2 1e 0d ec 18 d1 86 41 3b d8 53
695 
# 56 5b e2 04 73 d8 12 b8 39 e5 a1 2b 81 c8 27 a1
696 
# 1f dd 21 ca 31
697 
# ****
698 
# Config-Write: Id: 4 Addr = 7050, Cfg. Data = 28443044
699 
# 36540 ns: Received packet, size = 67
700 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
701 
# Length error, type/length field = 1792, expected value = 49
702 
# Contents:
703 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 38 79
704 
# b8 94 93 04 59 db 4d d9 6d 76 ca b6 95 46 04 f7
705 
# 69 b4 88 28 2d c7 2e 08 1c fd 29 1c 86 da 3d 66
706 
# 70 73 ba 5e fa d5 1a b9 37 96 c0 26 b6 7d dc e1
707 
# d6 98 d3
708 
# ****
709 
# 37540 ns: Preamble detected, last IFG = 96 bits
710 
# 38141 ns: SFD received, last IFG = 96 bits
711 
#             42260000 ns: Completed packet transmission to MAC
712 
# 43300 ns: Starting packet transmission to MAC, size = 70
713 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
714 
# Contents:
715 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 04 58
716 
# 96 14 12 96 b1 55 ed 2b f5 ad 27 84 a7 e7 b9 49
717 
# db c9 51 a1 2a fa 45 83 7c 72 fe 68 6f 86 f0 38
718 
# 40 28 f6 c5 c0 74 39 b0 3c 2a 62 15 e1 17 43 c9
719 
# 86 25 ec 93 f7 b6
720 
# ****
721 
# 43580 ns: Received packet, size = 68
722 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
723 
# Length error, type/length field = 1792, expected value = 50
724 
# Contents:
725 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 86 78
726 
# 7e db cf 79 fa 61 17 a1 86 50 f5 35 29 c1 c5 98
727 
# 4b 73 ec 8a 4e a8 a9 a1 0e e6 9f 2a 2a 8d 9e 38
728 
# 79 c8 ca 13 6b c7 b6 ba c4 b9 92 b4 7f 86 fa f2
729 
# d8 8a 95 46
730 
# ****
731 
# Config-Write: Id: 4 Addr = 7054, Cfg. Data = 28454045
732 
# 44860 ns: Preamble detected, last IFG = 124 bits
733 
# 45461 ns: SFD received, last IFG = 124 bits
734 
#             49540000 ns: Completed packet transmission to MAC
735 
# Config-Write: Id: 4 Addr = 7058, Cfg. Data = 28466046
736 
# 50580 ns: Starting packet transmission to MAC, size = 71
737 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
738 
# Contents:
739 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 c1 8d
740 
# 5a 07 2c 0c 71 3b b6 f7 9e 5c 55 20 a0 72 b4 dd
741 
# 0d 4b 79 9e fd 7b 8f 03 e3 1d b1 44 95 e0 ed 52
742 
# f8 8d 52 84 46 8c 90 17 6a 84 aa 7c 60 ba 8b a6
743 
# 25 32 a2 b2 82 de 56
744 
# ****
745 
# 50980 ns: Received packet, size = 69
746 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
747 
# Length error, type/length field = 1792, expected value = 51
748 
# Contents:
749 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 32 bd
750 
# 84 e4 ca a9 a1 8e fb 0b ef c9 36 75 8f 6b 88 ae
751 
# 9b 92 28 2d 4b c2 1e 0d ec 18 d1 86 41 3b d8 53
752 
# 56 5b e2 04 73 d8 12 b8 39 e5 a1 2b 81 c8 27 a1
753 
# 1f dd 21 ca 31
754 
# ****
755 
# 51980 ns: Preamble detected, last IFG = 96 bits
756 
# 52581 ns: SFD received, last IFG = 96 bits
757 
#             56900000 ns: Completed packet transmission to MAC
758 
# 57940 ns: Starting packet transmission to MAC, size = 72
759 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
760 
# Contents:
761 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 49 14
762 
# 3d 4b 5c 47 86 39 b4 d0 2c 8c 07 6a 11 e8 4b 73
763 
# ec 23 a4 c9 39 df d4 67 9d b0 82 49 d9 20 1c 93
764 
# e3 2a c8 5d 3a 84 2b 39 12 52 59 d0 6e 97 db a6
765 
# bb 00 0f 69 16 8d 9c 08
766 
# ****
767 
# 58180 ns: Received packet, size = 70
768 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
769 
# Length error, type/length field = 1792, expected value = 52
770 
# Contents:
771 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 04 58
772 
# 96 14 12 96 b1 55 ed 2b f5 ad 27 84 a7 e7 b9 49
773 
# db c9 51 a1 2a fa 45 83 7c 72 fe 68 6f 86 f0 38
774 
# 40 28 f6 c5 c0 74 39 b0 3c 2a 62 15 e1 17 43 c9
775 
# 86 25 ec 93 f7 b6
776 
# ****
777 
# Config-Write: Id: 4 Addr = 705c, Cfg. Data = 28478047
778 
# 59180 ns: Preamble detected, last IFG = 96 bits
779 
# 59781 ns: SFD received, last IFG = 96 bits
780 
#             64340000 ns: Completed packet transmission to MAC
781 
# 65380 ns: Starting packet transmission to MAC, size = 73
782 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
783 
# Contents:
784 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 0c 59
785 
# c5 cf 90 51 69 77 4a d8 9b c4 b8 b7 86 30 77 b5
786 
# d4 07 76 e9 8b 01 db 80 c2 c5 30 af 66 af e9 f8
787 
# 06 ef e1 95 ee 60 e5 28 64 29 e1 77 6e 81 d5 68
788 
# f0 aa 0f f1 7d 1f 08 38 e7
789 
# ****
790 
# 65460 ns: Received packet, size = 71
791 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
792 
# Length error, type/length field = 1792, expected value = 53
793 
# Contents:
794 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 c1 8d
795 
# 5a 07 2c 0c 71 3b b6 f7 9e 5c 55 20 a0 72 b4 dd
796 
# 0d 4b 79 9e fd 7b 8f 03 e3 1d b1 44 95 e0 ed 52
797 
# f8 8d 52 84 46 8c 90 17 6a 84 aa 7c 60 ba 8b a6
798 
# 25 32 a2 b2 82 de 56
799 
# ****
800 
# Config-Write: Id: 4 Addr = 7060, Cfg. Data = 2848a048
801 
# 66780 ns: Preamble detected, last IFG = 128 bits
802 
# 67381 ns: SFD received, last IFG = 128 bits
803 
#             71860000 ns: Completed packet transmission to MAC
804 
# 73140 ns: Received packet, size = 72
805 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
806 
# Length error, type/length field = 1792, expected value = 54
807 
# Contents:
808 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 49 14
809 
# 3d 4b 5c 47 86 39 b4 d0 2c 8c 07 6a 11 e8 4b 73
810 
# ec 23 a4 c9 39 df d4 67 9d b0 82 49 d9 20 1c 93
811 
# e3 2a c8 5d 3a 84 2b 39 12 52 59 d0 6e 97 db a6
812 
# bb 00 0f 69 16 8d 9c 08
813 
# ****
814 
# Config-Write: Id: 4 Addr = 7064, Cfg. Data = 2849c049
815 
# 74420 ns: Preamble detected, last IFG = 124 bits
816 
# 75021 ns: SFD received, last IFG = 124 bits
817 
# 80860 ns: Received packet, size = 73
818 
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700
819 
# Length error, type/length field = 1792, expected value = 55
820 
# Contents:
821 
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 0c 59
822 
# c5 cf 90 51 69 77 4a d8 9b c4 b8 b7 86 30 77 b5
823 
# d4 07 76 e9 8b 01 db 80 c2 c5 30 af 66 af e9 f8
824 
# 06 ef e1 95 ee 60 e5 28 64 29 e1 77 6e 81 d5 68
825 
# f0 aa 0f f1 7d 1f 08 38 e7
826 
# ****
827 
#############################
828 
#    TB MII Statistic
829 
#  TB TO DUT :
830 
#      Frm cnt       :          10
831 
#      Byte cnt      :         685
832 
#  DUT TO TB :
833 
#      Frm cnt       :          10
834 
#      Byte cnt      :         685
835 
#      Pause Frm  cnt:           0
836 
#      Alig Err   cnt:           0
837 
#      usized Err cnt:           0
838 
#      crc Err    cnt:           0
839 
#      Length Err cnt:          10
840 
#############################
841 
#
842 
# -------------------------------------------------
843 
# Test Status
844 
# warnings: 0, errors: 0
845 
#
846 
# -------------------------------------------------
847 
# Test Status
848 
# warnings: 0, errors: 0
849 
#
850 
# =========
851 
# Test Status: TEST PASSED
852 
# =========
853 
#
854 
# ** Note: $finish    : ../../verif/lib/tb_glbl.v(64)
855 
#    Time: 174676 ns  Iteration: 0  Instance: /tb_top
856 
### test 2: gmac_test_1 --> PASSED
857 
### Running test 3: uart_test_1
858 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
859 
 
860 
# 6.6d
861 
 
862 
# vsim +uart_test_1 -do run.do -c tb_top
863 
# //  ModelSim ACTEL 6.6d Nov  2 2010
864 
# //
865 
# //  Copyright 1991-2010 Mentor Graphics Corporation
866 
# //              All Rights Reserved.
867 
# //
868 
# //  THIS WORK CONTAINS TRADE SECRET AND
869 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
870 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
871 
# //  AND IS SUBJECT TO LICENSE TERMS.
872 
# //
873 
# Loading sv_std.std
874 
# Loading work.tb_top
875 
# Loading work.turbo8051
876 
# Loading work.clkgen
877 
# Loading work.clk_ctl
878 
# Loading work.wb_crossbar
879 
# Loading work.g_mac_top
880 
# Loading work.g_dpath_ctrl
881 
# Loading work.g_eth_parser
882 
# Loading work.g_mac_core
883 
# Loading work.g_rx_top
884 
# Loading work.g_rx_fsm
885 
# Loading work.half_dup_dble_reg
886 
# Loading work.g_rx_crc32
887 
# Loading work.g_deferral_rx
888 
# Loading work.g_md_intf
889 
# Loading work.g_tx_top
890 
# Loading work.g_deferral
891 
# Loading work.g_tx_fsm
892 
# Loading work.g_tx_crc32
893 
# Loading work.toggle_sync
894 
# Loading work.g_cfg_mgmt
895 
# Loading work.s2f_sync
896 
# Loading work.generic_register
897 
# Loading work.req_register
898 
# Loading work.stat_counter
899 
# Loading work.generic_intr_stat_reg
900 
# Loading work.g_mii_intf
901 
# Loading work.async_fifo
902 
# Loading work.wb_rd_mem2mem
903 
# Loading work.wb_wr_mem2mem
904 
# Loading work.uart_core
905 
# Loading work.uart_cfg
906 
# Loading work.stat_register
907 
# Loading work.uart_txfsm
908 
# Loading work.uart_rxfsm
909 
# Loading work.double_sync_low
910 
# Loading work.spi_core
911 
# Loading work.spi_if
912 
# Loading work.spi_ctl
913 
# Loading work.spi_cfg
914 
# Loading work.oc8051_top
915 
# Loading work.oc8051_decoder
916 
# Loading work.oc8051_alu
917 
# Loading work.oc8051_multiply
918 
# Loading work.oc8051_divide
919 
# Loading work.oc8051_ram_top
920 
# Loading work.oc8051_ram_256x8_two_bist
921 
# Loading work.oc8051_alu_src_sel
922 
# Loading work.oc8051_comp
923 
# Loading work.oc8051_rom
924 
# Loading work.oc8051_cy_select
925 
# Loading work.oc8051_indi_addr
926 
# Loading work.oc8051_memory_interface
927 
# Loading work.oc8051_sfr
928 
# Loading work.oc8051_acc
929 
# Loading work.oc8051_b_register
930 
# Loading work.oc8051_sp
931 
# Loading work.oc8051_dptr
932 
# Loading work.oc8051_psw
933 
# Loading work.oc8051_ports
934 
# Loading work.oc8051_int
935 
# Loading work.oc8051_tc
936 
# Loading work.oc8051_tc2
937 
# Loading work.oc8051_xrom
938 
# Loading work.oc8051_xram
939 
# Loading work.tb_eth_top
940 
# Loading work.tb_mii
941 
# Loading work.tb_rmii
942 
# Loading work.uart_agent
943 
# Loading work.m25p20
944 
# Loading work.memory_access
945 
# Loading work.acdc_check
946 
# Loading work.internal_logic
947 
# Loading work.AT45DB321
948 
# Loading work.tb_glbl
949 
# Loading work.bit_register
950 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
951 
#           File in use by:   Hostname:   ProcessID: 14
952 
#           Attempting to use alternate WLF file "./wlft22nc1m".
953 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
954 
#           Using alternate file: ./wlft22nc1m
955 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
956 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
957 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
958 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
959 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
960 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
961 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
962 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
963 
# do run.do
964 
# i : 00
965 
# i : 00
966 
# i : 00
967 
# i : 00
968 
# i : 00
969 
# i : 00
970 
# i : 00
971 
# i : 00
972 
# i : 00
973 
# i : 00
974 
# NOTE : Load memory with Initial delivery content
975 
# NOTE : Initial Load End
976 
# NOTE: COMMUNICATION (RE)STARTED
977 
# Config-Write: Id: 3 Addr = 0000, Cfg. Data = 00000017
978 
#
979 
# ... Writing char  36 ...
980 
# ... Write data 24 to UART done cnt :          1 ...
981 
#
982 
#
983 
# ... Writing char 129 ...
984 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  24
985 
# ... Read Data from UART done cnt :         1...
986 
# ... Write data 81 to UART done cnt :          2 ...
987 
#
988 
#
989 
# ... Writing char   9 ...
990 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  81
991 
# ... Read Data from UART done cnt :         2...
992 
# ... Write data 09 to UART done cnt :          3 ...
993 
#
994 
#
995 
# ... Writing char  99 ...
996 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  09
997 
# ... Read Data from UART done cnt :         3...
998 
# ... Write data 63 to UART done cnt :          4 ...
999 
#
1000 
#
1001 
# ... Writing char  13 ...
1002 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  63
1003 
# ... Read Data from UART done cnt :         4...
1004 
# ... Write data 0d to UART done cnt :          5 ...
1005 
#
1006 
#
1007 
# ... Writing char 141 ...
1008 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0d
1009 
# ... Read Data from UART done cnt :         5...
1010 
# ... Write data 8d to UART done cnt :          6 ...
1011 
#
1012 
#
1013 
# ... Writing char 101 ...
1014 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  8d
1015 
# ... Read Data from UART done cnt :         6...
1016 
# ... Write data 65 to UART done cnt :          7 ...
1017 
#
1018 
#
1019 
# ... Writing char  18 ...
1020 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  65
1021 
# ... Read Data from UART done cnt :         7...
1022 
# ... Write data 12 to UART done cnt :          8 ...
1023 
#
1024 
#
1025 
# ... Writing char   1 ...
1026 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  12
1027 
# ... Read Data from UART done cnt :         8...
1028 
# ... Write data 01 to UART done cnt :          9 ...
1029 
#
1030 
#
1031 
# ... Writing char  13 ...
1032 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  01
1033 
# ... Read Data from UART done cnt :         9...
1034 
# ... Write data 0d to UART done cnt :         10 ...
1035 
#
1036 
#
1037 
# ... Writing char 118 ...
1038 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0d
1039 
# ... Read Data from UART done cnt :        10...
1040 
# ... Write data 76 to UART done cnt :         11 ...
1041 
#
1042 
#
1043 
# ... Writing char  61 ...
1044 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  76
1045 
# ... Read Data from UART done cnt :        11...
1046 
# ... Write data 3d to UART done cnt :         12 ...
1047 
#
1048 
#
1049 
# ... Writing char 237 ...
1050 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  3d
1051 
# ... Read Data from UART done cnt :        12...
1052 
# ... Write data ed to UART done cnt :         13 ...
1053 
#
1054 
#
1055 
# ... Writing char 140 ...
1056 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  ed
1057 
# ... Read Data from UART done cnt :        13...
1058 
# ... Write data 8c to UART done cnt :         14 ...
1059 
#
1060 
#
1061 
# ... Writing char 249 ...
1062 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  8c
1063 
# ... Read Data from UART done cnt :        14...
1064 
# ... Write data f9 to UART done cnt :         15 ...
1065 
#
1066 
#
1067 
# ... Writing char 198 ...
1068 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  f9
1069 
# ... Read Data from UART done cnt :        15...
1070 
# ... Write data c6 to UART done cnt :         16 ...
1071 
#
1072 
#
1073 
# ... Writing char 197 ...
1074 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  c6
1075 
# ... Read Data from UART done cnt :        16...
1076 
# ... Write data c5 to UART done cnt :         17 ...
1077 
#
1078 
#
1079 
# ... Writing char 170 ...
1080 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  c5
1081 
# ... Read Data from UART done cnt :        17...
1082 
# ... Write data aa to UART done cnt :         18 ...
1083 
#
1084 
#
1085 
# ... Writing char 229 ...
1086 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  aa
1087 
# ... Read Data from UART done cnt :        18...
1088 
# ... Write data e5 to UART done cnt :         19 ...
1089 
#
1090 
#
1091 
# ... Writing char 119 ...
1092 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  e5
1093 
# ... Read Data from UART done cnt :        19...
1094 
# ... Write data 77 to UART done cnt :         20 ...
1095 
#
1096 
#
1097 
# ... Writing char  18 ...
1098 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  77
1099 
# ... Read Data from UART done cnt :        20...
1100 
# ... Write data 12 to UART done cnt :         21 ...
1101 
#
1102 
#
1103 
# ... Writing char 143 ...
1104 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  12
1105 
# ... Read Data from UART done cnt :        21...
1106 
# ... Write data 8f to UART done cnt :         22 ...
1107 
#
1108 
#
1109 
# ... Writing char 242 ...
1110 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  8f
1111 
# ... Read Data from UART done cnt :        22...
1112 
# ... Write data f2 to UART done cnt :         23 ...
1113 
#
1114 
#
1115 
# ... Writing char 206 ...
1116 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  f2
1117 
# ... Read Data from UART done cnt :        23...
1118 
# ... Write data ce to UART done cnt :         24 ...
1119 
#
1120 
#
1121 
# ... Writing char 232 ...
1122 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  ce
1123 
# ... Read Data from UART done cnt :        24...
1124 
# ... Write data e8 to UART done cnt :         25 ...
1125 
#
1126 
#
1127 
# ... Writing char 197 ...
1128 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  e8
1129 
# ... Read Data from UART done cnt :        25...
1130 
# ... Write data c5 to UART done cnt :         26 ...
1131 
#
1132 
#
1133 
# ... Writing char  92 ...
1134 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  c5
1135 
# ... Read Data from UART done cnt :        26...
1136 
# ... Write data 5c to UART done cnt :         27 ...
1137 
#
1138 
#
1139 
# ... Writing char 189 ...
1140 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  5c
1141 
# ... Read Data from UART done cnt :        27...
1142 
# ... Write data bd to UART done cnt :         28 ...
1143 
#
1144 
#
1145 
# ... Writing char  45 ...
1146 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  bd
1147 
# ... Read Data from UART done cnt :        28...
1148 
# ... Write data 2d to UART done cnt :         29 ...
1149 
#
1150 
#
1151 
# ... Writing char 101 ...
1152 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  2d
1153 
# ... Read Data from UART done cnt :        29...
1154 
# ... Write data 65 to UART done cnt :         30 ...
1155 
#
1156 
#
1157 
# ... Writing char  99 ...
1158 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  65
1159 
# ... Read Data from UART done cnt :        30...
1160 
# ... Write data 63 to UART done cnt :         31 ...
1161 
#
1162 
#
1163 
# ... Writing char  10 ...
1164 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  63
1165 
# ... Read Data from UART done cnt :        31...
1166 
# ... Write data 0a to UART done cnt :         32 ...
1167 
#
1168 
#
1169 
# ... Writing char 128 ...
1170 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0a
1171 
# ... Read Data from UART done cnt :        32...
1172 
# ... Write data 80 to UART done cnt :         33 ...
1173 
#
1174 
#
1175 
# ... Writing char  32 ...
1176 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  80
1177 
# ... Read Data from UART done cnt :        33...
1178 
# ... Write data 20 to UART done cnt :         34 ...
1179 
#
1180 
#
1181 
# ... Writing char 170 ...
1182 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  20
1183 
# ... Read Data from UART done cnt :        34...
1184 
# ... Write data aa to UART done cnt :         35 ...
1185 
#
1186 
#
1187 
# ... Writing char 157 ...
1188 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  aa
1189 
# ... Read Data from UART done cnt :        35...
1190 
# ... Write data 9d to UART done cnt :         36 ...
1191 
#
1192 
#
1193 
# ... Writing char 150 ...
1194 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  9d
1195 
# ... Read Data from UART done cnt :        36...
1196 
# ... Write data 96 to UART done cnt :         37 ...
1197 
#
1198 
#
1199 
# ... Writing char  19 ...
1200 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  96
1201 
# ... Read Data from UART done cnt :        37...
1202 
# ... Write data 13 to UART done cnt :         38 ...
1203 
#
1204 
#
1205 
# ... Writing char  13 ...
1206 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  13
1207 
# ... Read Data from UART done cnt :        38...
1208 
# ... Write data 0d to UART done cnt :         39 ...
1209 
#
1210 
#
1211 
# ... Writing char  83 ...
1212 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0d
1213 
# ... Read Data from UART done cnt :        39...
1214 
# ... Write data 53 to UART done cnt :         40 ...
1215 
#
1216 
# (tb_top.tb_uart.read_char_chk.loop_2) Data match  53
1217 
# ... Read Data from UART done cnt :        40...
1218 
# -------------------- Reporting Configuration --------------------
1219 
#       Data bit number setting is : 8
1220 
#       Stop bit number setting is : 1
1221 
#       Divisor of Uart clock   is : 3
1222 
#       Parity is enable
1223 
#       Even parity setting
1224 
#       FIFO mode is disable
1225 
# -----------------------------------------------------------------
1226 
# -------------------- Reporting Status --------------------
1227 
#
1228 
#       Number of character received is :    40
1229 
#       Number of character sent     is :    40
1230 
#       Number of parity error rxd   is :     0
1231 
#       Number of stop1  error rxd   is :     0
1232 
#       Number of stop2  error rxd   is :     0
1233 
#       Number of timeout error      is :     0
1234 
#       Number of error              is :     0
1235 
# -----------------------------------------------------------------
1236 
#
1237 
# -------------------------------------------------
1238 
# Test Status
1239 
# warnings: 0, errors: 0
1240 
#
1241 
# -------------------------------------------------
1242 
# Test Status
1243 
# warnings: 0, errors: 0
1244 
#
1245 
# =========
1246 
# Test Status: TEST PASSED
1247 
# =========
1248 
#
1249 
# ** Note: $finish    : ../../verif/lib/tb_glbl.v(64)
1250 
#    Time: 157871 ns  Iteration: 0  Instance: /tb_top
1251 
### test 3: uart_test_1 --> PASSED
1252 
### Running test 4: spi_test_1
1253 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
1254 
 
1255 
# 6.6d
1256 
 
1257 
# vsim +spi_test_1 -do run.do -c tb_top
1258 
# //  ModelSim ACTEL 6.6d Nov  2 2010
1259 
# //
1260 
# //  Copyright 1991-2010 Mentor Graphics Corporation
1261 
# //              All Rights Reserved.
1262 
# //
1263 
# //  THIS WORK CONTAINS TRADE SECRET AND
1264 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
1265 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
1266 
# //  AND IS SUBJECT TO LICENSE TERMS.
1267 
# //
1268 
# Loading sv_std.std
1269 
# Loading work.tb_top
1270 
# Loading work.turbo8051
1271 
# Loading work.clkgen
1272 
# Loading work.clk_ctl
1273 
# Loading work.wb_crossbar
1274 
# Loading work.g_mac_top
1275 
# Loading work.g_dpath_ctrl
1276 
# Loading work.g_eth_parser
1277 
# Loading work.g_mac_core
1278 
# Loading work.g_rx_top
1279 
# Loading work.g_rx_fsm
1280 
# Loading work.half_dup_dble_reg
1281 
# Loading work.g_rx_crc32
1282 
# Loading work.g_deferral_rx
1283 
# Loading work.g_md_intf
1284 
# Loading work.g_tx_top
1285 
# Loading work.g_deferral
1286 
# Loading work.g_tx_fsm
1287 
# Loading work.g_tx_crc32
1288 
# Loading work.toggle_sync
1289 
# Loading work.g_cfg_mgmt
1290 
# Loading work.s2f_sync
1291 
# Loading work.generic_register
1292 
# Loading work.req_register
1293 
# Loading work.stat_counter
1294 
# Loading work.generic_intr_stat_reg
1295 
# Loading work.g_mii_intf
1296 
# Loading work.async_fifo
1297 
# Loading work.wb_rd_mem2mem
1298 
# Loading work.wb_wr_mem2mem
1299 
# Loading work.uart_core
1300 
# Loading work.uart_cfg
1301 
# Loading work.stat_register
1302 
# Loading work.uart_txfsm
1303 
# Loading work.uart_rxfsm
1304 
# Loading work.double_sync_low
1305 
# Loading work.spi_core
1306 
# Loading work.spi_if
1307 
# Loading work.spi_ctl
1308 
# Loading work.spi_cfg
1309 
# Loading work.oc8051_top
1310 
# Loading work.oc8051_decoder
1311 
# Loading work.oc8051_alu
1312 
# Loading work.oc8051_multiply
1313 
# Loading work.oc8051_divide
1314 
# Loading work.oc8051_ram_top
1315 
# Loading work.oc8051_ram_256x8_two_bist
1316 
# Loading work.oc8051_alu_src_sel
1317 
# Loading work.oc8051_comp
1318 
# Loading work.oc8051_rom
1319 
# Loading work.oc8051_cy_select
1320 
# Loading work.oc8051_indi_addr
1321 
# Loading work.oc8051_memory_interface
1322 
# Loading work.oc8051_sfr
1323 
# Loading work.oc8051_acc
1324 
# Loading work.oc8051_b_register
1325 
# Loading work.oc8051_sp
1326 
# Loading work.oc8051_dptr
1327 
# Loading work.oc8051_psw
1328 
# Loading work.oc8051_ports
1329 
# Loading work.oc8051_int
1330 
# Loading work.oc8051_tc
1331 
# Loading work.oc8051_tc2
1332 
# Loading work.oc8051_xrom
1333 
# Loading work.oc8051_xram
1334 
# Loading work.tb_eth_top
1335 
# Loading work.tb_mii
1336 
# Loading work.tb_rmii
1337 
# Loading work.uart_agent
1338 
# Loading work.m25p20
1339 
# Loading work.memory_access
1340 
# Loading work.acdc_check
1341 
# Loading work.internal_logic
1342 
# Loading work.AT45DB321
1343 
# Loading work.tb_glbl
1344 
# Loading work.bit_register
1345 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
1346 
#           File in use by:   Hostname:   ProcessID: 14
1347 
#           Attempting to use alternate WLF file "./wlftdf5ms9".
1348 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
1349 
#           Using alternate file: ./wlftdf5ms9
1350 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
1351 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
1352 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
1353 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
1354 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
1355 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
1356 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
1357 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
1358 
# do run.do
1359 
# i : 00
1360 
# i : 00
1361 
# i : 00
1362 
# i : 00
1363 
# i : 00
1364 
# i : 00
1365 
# i : 00
1366 
# i : 00
1367 
# i : 00
1368 
# i : 00
1369 
# NOTE : Load memory with Initial delivery content
1370 
# NOTE : Initial Load End
1371 
# NOTE: COMMUNICATION (RE)STARTED
1372 
############################################
1373 
#    Testing ST Flash Read/Write Access
1374 
############################################
1375 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 06000000
1376 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020240
1377 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d8000000
1378 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0201
1379 
#              6815000 : tb_top.spi_sector_errase : Sending Sector Errase for Address : 000000
1380 
# NOTE : Sector erase cycle has begun
1381 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000
1382 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200
1383 
# NOTE : Only a Read Status Register instruction will be valid
1384 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240
1385 
# Total time Elapsed: 0(us): tb_top.spi_wait_busy : Checking the SPI RDStatus : 03000000
1386 
# NOTE : Sector erase cycle is finished
1387 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000
1388 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200
1389 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240
1390 
# Total time Elapsed: 0(us): tb_top.spi_wait_busy : Checking the SPI RDStatus : 00000000
1391 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 06000000
1392 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020240
1393 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 02000000
1394 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1395 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 00010203
1396 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1397 
# tb_top.spi_page_write : Writing Data : 00010203
1398 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 04050607
1399 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1400 
# tb_top.spi_page_write : Writing Data : 04050607
1401 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 08090a0b
1402 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1403 
# tb_top.spi_page_write : Writing Data : 08090a0b
1404 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 0c0d0e0f
1405 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1406 
# tb_top.spi_page_write : Writing Data : 0c0d0e0f
1407 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 10111213
1408 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1409 
# tb_top.spi_page_write : Writing Data : 10111213
1410 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 14151617
1411 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1412 
# tb_top.spi_page_write : Writing Data : 14151617
1413 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 18191a1b
1414 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1415 
# tb_top.spi_page_write : Writing Data : 18191a1b
1416 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 1c1d1e1f
1417 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1418 
# tb_top.spi_page_write : Writing Data : 1c1d1e1f
1419 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 20212223
1420 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1421 
# tb_top.spi_page_write : Writing Data : 20212223
1422 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 24252627
1423 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1424 
# tb_top.spi_page_write : Writing Data : 24252627
1425 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 28292a2b
1426 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1427 
# tb_top.spi_page_write : Writing Data : 28292a2b
1428 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 2c2d2e2f
1429 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1430 
# tb_top.spi_page_write : Writing Data : 2c2d2e2f
1431 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 30313233
1432 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1433 
# tb_top.spi_page_write : Writing Data : 30313233
1434 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 34353637
1435 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1436 
# tb_top.spi_page_write : Writing Data : 34353637
1437 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 38393a3b
1438 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1439 
# tb_top.spi_page_write : Writing Data : 38393a3b
1440 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 3c3d3e3f
1441 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1442 
# tb_top.spi_page_write : Writing Data : 3c3d3e3f
1443 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 40414243
1444 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1445 
# tb_top.spi_page_write : Writing Data : 40414243
1446 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 44454647
1447 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1448 
# tb_top.spi_page_write : Writing Data : 44454647
1449 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 48494a4b
1450 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1451 
# tb_top.spi_page_write : Writing Data : 48494a4b
1452 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 4c4d4e4f
1453 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1454 
# tb_top.spi_page_write : Writing Data : 4c4d4e4f
1455 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 50515253
1456 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1457 
# tb_top.spi_page_write : Writing Data : 50515253
1458 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 54555657
1459 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1460 
# tb_top.spi_page_write : Writing Data : 54555657
1461 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 58595a5b
1462 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1463 
# tb_top.spi_page_write : Writing Data : 58595a5b
1464 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 5c5d5e5f
1465 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1466 
# tb_top.spi_page_write : Writing Data : 5c5d5e5f
1467 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 60616263
1468 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1469 
# tb_top.spi_page_write : Writing Data : 60616263
1470 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 64656667
1471 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1472 
# tb_top.spi_page_write : Writing Data : 64656667
1473 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 68696a6b
1474 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1475 
# tb_top.spi_page_write : Writing Data : 68696a6b
1476 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 6c6d6e6f
1477 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1478 
# tb_top.spi_page_write : Writing Data : 6c6d6e6f
1479 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 70717273
1480 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1481 
# tb_top.spi_page_write : Writing Data : 70717273
1482 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 74757677
1483 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1484 
# tb_top.spi_page_write : Writing Data : 74757677
1485 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 78797a7b
1486 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1487 
# tb_top.spi_page_write : Writing Data : 78797a7b
1488 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 7c7d7e7f
1489 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1490 
# tb_top.spi_page_write : Writing Data : 7c7d7e7f
1491 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 80818283
1492 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1493 
# tb_top.spi_page_write : Writing Data : 80818283
1494 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 84858687
1495 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1496 
# tb_top.spi_page_write : Writing Data : 84858687
1497 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 88898a8b
1498 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1499 
# tb_top.spi_page_write : Writing Data : 88898a8b
1500 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 8c8d8e8f
1501 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1502 
# tb_top.spi_page_write : Writing Data : 8c8d8e8f
1503 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 90919293
1504 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1505 
# tb_top.spi_page_write : Writing Data : 90919293
1506 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 94959697
1507 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1508 
# tb_top.spi_page_write : Writing Data : 94959697
1509 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 98999a9b
1510 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1511 
# tb_top.spi_page_write : Writing Data : 98999a9b
1512 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 9c9d9e9f
1513 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1514 
# tb_top.spi_page_write : Writing Data : 9c9d9e9f
1515 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = a0a1a2a3
1516 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1517 
# tb_top.spi_page_write : Writing Data : a0a1a2a3
1518 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = a4a5a6a7
1519 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1520 
# tb_top.spi_page_write : Writing Data : a4a5a6a7
1521 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = a8a9aaab
1522 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1523 
# tb_top.spi_page_write : Writing Data : a8a9aaab
1524 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = acadaeaf
1525 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1526 
# tb_top.spi_page_write : Writing Data : acadaeaf
1527 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = b0b1b2b3
1528 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1529 
# tb_top.spi_page_write : Writing Data : b0b1b2b3
1530 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = b4b5b6b7
1531 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1532 
# tb_top.spi_page_write : Writing Data : b4b5b6b7
1533 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = b8b9babb
1534 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1535 
# tb_top.spi_page_write : Writing Data : b8b9babb
1536 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = bcbdbebf
1537 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1538 
# tb_top.spi_page_write : Writing Data : bcbdbebf
1539 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = c0c1c2c3
1540 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1541 
# tb_top.spi_page_write : Writing Data : c0c1c2c3
1542 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = c4c5c6c7
1543 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1544 
# tb_top.spi_page_write : Writing Data : c4c5c6c7
1545 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = c8c9cacb
1546 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1547 
# tb_top.spi_page_write : Writing Data : c8c9cacb
1548 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = cccdcecf
1549 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1550 
# tb_top.spi_page_write : Writing Data : cccdcecf
1551 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d0d1d2d3
1552 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1553 
# tb_top.spi_page_write : Writing Data : d0d1d2d3
1554 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d4d5d6d7
1555 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1556 
# tb_top.spi_page_write : Writing Data : d4d5d6d7
1557 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d8d9dadb
1558 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1559 
# tb_top.spi_page_write : Writing Data : d8d9dadb
1560 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = dcdddedf
1561 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1562 
# tb_top.spi_page_write : Writing Data : dcdddedf
1563 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = e0e1e2e3
1564 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1565 
# tb_top.spi_page_write : Writing Data : e0e1e2e3
1566 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = e4e5e6e7
1567 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1568 
# tb_top.spi_page_write : Writing Data : e4e5e6e7
1569 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = e8e9eaeb
1570 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1571 
# tb_top.spi_page_write : Writing Data : e8e9eaeb
1572 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = ecedeeef
1573 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1574 
# tb_top.spi_page_write : Writing Data : ecedeeef
1575 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = f0f1f2f3
1576 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1577 
# tb_top.spi_page_write : Writing Data : f0f1f2f3
1578 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = f4f5f6f7
1579 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1580 
# tb_top.spi_page_write : Writing Data : f4f5f6f7
1581 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = f8f9fafb
1582 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1583 
# tb_top.spi_page_write : Writing Data : f8f9fafb
1584 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = fcfdfeff
1585 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0201
1586 
# NOTE : Page program cycle is started
1587 
# tb_top.spi_page_write : Writing Data : fcfdfeff
1588 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000
1589 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200
1590 
# NOTE : Only a Read Status Register instruction will be valid
1591 
# NOTE : Page program cycle is finished
1592 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240
1593 
# Total time Elapsed: 0(us): tb_top.spi_wait_busy : Checking the SPI RDStatus : 00000000
1594 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 03000000
1595 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
1596 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1597 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 00010203
1598 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1599 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 04050607
1600 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1601 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 08090a0b
1602 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1603 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 0c0d0e0f
1604 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1605 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 10111213
1606 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1607 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 14151617
1608 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1609 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 18191a1b
1610 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1611 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 1c1d1e1f
1612 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1613 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 20212223
1614 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1615 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 24252627
1616 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1617 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 28292a2b
1618 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1619 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 2c2d2e2f
1620 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1621 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 30313233
1622 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1623 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 34353637
1624 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1625 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 38393a3b
1626 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1627 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 3c3d3e3f
1628 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1629 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 40414243
1630 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1631 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 44454647
1632 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1633 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 48494a4b
1634 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1635 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 4c4d4e4f
1636 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1637 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 50515253
1638 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1639 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 54555657
1640 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1641 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 58595a5b
1642 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1643 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 5c5d5e5f
1644 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1645 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 60616263
1646 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1647 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 64656667
1648 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1649 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 68696a6b
1650 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1651 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 6c6d6e6f
1652 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1653 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 70717273
1654 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1655 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 74757677
1656 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1657 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 78797a7b
1658 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1659 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 7c7d7e7f
1660 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1661 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 80818283
1662 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1663 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 84858687
1664 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1665 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 88898a8b
1666 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1667 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 8c8d8e8f
1668 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1669 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 90919293
1670 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1671 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 94959697
1672 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1673 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 98999a9b
1674 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1675 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : 9c9d9e9f
1676 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1677 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : a0a1a2a3
1678 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1679 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : a4a5a6a7
1680 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1681 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : a8a9aaab
1682 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1683 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : acadaeaf
1684 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1685 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : b0b1b2b3
1686 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1687 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : b4b5b6b7
1688 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1689 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : b8b9babb
1690 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1691 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : bcbdbebf
1692 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1693 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : c0c1c2c3
1694 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1695 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : c4c5c6c7
1696 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1697 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : c8c9cacb
1698 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1699 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : cccdcecf
1700 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1701 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : d0d1d2d3
1702 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1703 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : d4d5d6d7
1704 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1705 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : d8d9dadb
1706 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1707 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : dcdddedf
1708 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1709 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : e0e1e2e3
1710 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1711 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : e4e5e6e7
1712 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1713 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : e8e9eaeb
1714 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1715 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : ecedeeef
1716 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1717 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : f0f1f2f3
1718 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1719 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : f4f5f6f7
1720 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1721 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : f8f9fafb
1722 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
1723 
# tb_top.spi_page_read_verify : STATUS :  Data Matched : fcfdfeff
1724 
#############################
1725 
#    Test Statistic
1726 
# TEST STATUS : PASSED
1727 
#############################
1728 
#
1729 
# -------------------------------------------------
1730 
# Test Status
1731 
# warnings: 0, errors: 0
1732 
#
1733 
# -------------------------------------------------
1734 
# Test Status
1735 
# warnings: 0, errors: 0
1736 
#
1737 
# =========
1738 
# Test Status: TEST PASSED
1739 
# =========
1740 
#
1741 
# ** Note: $finish    : ../../verif/lib/tb_glbl.v(64)
1742 
#    Time: 2968996 ns  Iteration: 0  Instance: /tb_top
1743 
### test 4: spi_test_1 --> PASSED
1744 
###########################################
1745 
 
1746 
###########################################
1747 
###  Test Logs
1748 
   test 1: ../log/gmac_test_2.log
1749 
   test 2: ../log/gmac_test_1.log
1750 
   test 3: ../log/uart_test_1.log
1751 
   test 4: ../log/spi_test_1.log
1752 
###########################################
1753 
 
1754 
 
1755 
###########################################
1756 
### tesing 8051 programs from external rom
1757 
###########################################
1758 
###########################################
1759 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
1760 
 
1761 
# 6.6d
1762 
 
1763 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
1764 
# //  ModelSim ACTEL 6.6d Nov  2 2010
1765 
# //
1766 
# //  Copyright 1991-2010 Mentor Graphics Corporation
1767 
# //              All Rights Reserved.
1768 
# //
1769 
# //  THIS WORK CONTAINS TRADE SECRET AND
1770 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
1771 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
1772 
# //  AND IS SUBJECT TO LICENSE TERMS.
1773 
# //
1774 
# Loading sv_std.std
1775 
# Loading work.tb_top
1776 
# Loading work.turbo8051
1777 
# Loading work.clkgen
1778 
# Loading work.clk_ctl
1779 
# Loading work.wb_crossbar
1780 
# Loading work.g_mac_top
1781 
# Loading work.g_dpath_ctrl
1782 
# Loading work.g_eth_parser
1783 
# Loading work.g_mac_core
1784 
# Loading work.g_rx_top
1785 
# Loading work.g_rx_fsm
1786 
# Loading work.half_dup_dble_reg
1787 
# Loading work.g_rx_crc32
1788 
# Loading work.g_deferral_rx
1789 
# Loading work.g_md_intf
1790 
# Loading work.g_tx_top
1791 
# Loading work.g_deferral
1792 
# Loading work.g_tx_fsm
1793 
# Loading work.g_tx_crc32
1794 
# Loading work.toggle_sync
1795 
# Loading work.g_cfg_mgmt
1796 
# Loading work.s2f_sync
1797 
# Loading work.generic_register
1798 
# Loading work.req_register
1799 
# Loading work.stat_counter
1800 
# Loading work.generic_intr_stat_reg
1801 
# Loading work.g_mii_intf
1802 
# Loading work.async_fifo
1803 
# Loading work.wb_rd_mem2mem
1804 
# Loading work.wb_wr_mem2mem
1805 
# Loading work.uart_core
1806 
# Loading work.uart_cfg
1807 
# Loading work.stat_register
1808 
# Loading work.uart_txfsm
1809 
# Loading work.uart_rxfsm
1810 
# Loading work.double_sync_low
1811 
# Loading work.spi_core
1812 
# Loading work.spi_if
1813 
# Loading work.spi_ctl
1814 
# Loading work.spi_cfg
1815 
# Loading work.oc8051_top
1816 
# Loading work.oc8051_decoder
1817 
# Loading work.oc8051_alu
1818 
# Loading work.oc8051_multiply
1819 
# Loading work.oc8051_divide
1820 
# Loading work.oc8051_ram_top
1821 
# Loading work.oc8051_ram_256x8_two_bist
1822 
# Loading work.oc8051_alu_src_sel
1823 
# Loading work.oc8051_comp
1824 
# Loading work.oc8051_rom
1825 
# Loading work.oc8051_cy_select
1826 
# Loading work.oc8051_indi_addr
1827 
# Loading work.oc8051_memory_interface
1828 
# Loading work.oc8051_sfr
1829 
# Loading work.oc8051_acc
1830 
# Loading work.oc8051_b_register
1831 
# Loading work.oc8051_sp
1832 
# Loading work.oc8051_dptr
1833 
# Loading work.oc8051_psw
1834 
# Loading work.oc8051_ports
1835 
# Loading work.oc8051_int
1836 
# Loading work.oc8051_tc
1837 
# Loading work.oc8051_tc2
1838 
# Loading work.oc8051_xrom
1839 
# Loading work.oc8051_xram
1840 
# Loading work.tb_eth_top
1841 
# Loading work.tb_mii
1842 
# Loading work.tb_rmii
1843 
# Loading work.uart_agent
1844 
# Loading work.m25p20
1845 
# Loading work.memory_access
1846 
# Loading work.acdc_check
1847 
# Loading work.internal_logic
1848 
# Loading work.AT45DB321
1849 
# Loading work.tb_glbl
1850 
# Loading work.bit_register
1851 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
1852 
#           File in use by:   Hostname:   ProcessID: 14
1853 
#           Attempting to use alternate WLF file "./wlftg8faj1".
1854 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
1855 
#           Using alternate file: ./wlftg8faj1
1856 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
1857 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
1858 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
1859 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
1860 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
1861 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
1862 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
1863 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
1864 
# do run.do
1865 
# i : 02
1866 
# i : 00
1867 
# i : 08
1868 
# i : 12
1869 
# i : 01
1870 
# i : 51
1871 
# i : 80
1872 
# i : fe
1873 
# i : 75
1874 
# i : 81
1875 
# NOTE : Load memory with Initial delivery content
1876 
# NOTE : Initial Load End
1877 
# NOTE: COMMUNICATION (RE)STARTED
1878 
################################
1879 
# time                62216 Passed
1880 
################################
1881 
# ** Note: $finish    : ../tb/tb_top.v(448)
1882 
#    Time: 62316 ns  Iteration: 0  Instance: /tb_top
1883 
### test 1: fib --> PASSED
1884 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
1885 
 
1886 
# 6.6d
1887 
 
1888 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
1889 
# //  ModelSim ACTEL 6.6d Nov  2 2010
1890 
# //
1891 
# //  Copyright 1991-2010 Mentor Graphics Corporation
1892 
# //              All Rights Reserved.
1893 
# //
1894 
# //  THIS WORK CONTAINS TRADE SECRET AND
1895 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
1896 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
1897 
# //  AND IS SUBJECT TO LICENSE TERMS.
1898 
# //
1899 
# Loading sv_std.std
1900 
# Loading work.tb_top
1901 
# Loading work.turbo8051
1902 
# Loading work.clkgen
1903 
# Loading work.clk_ctl
1904 
# Loading work.wb_crossbar
1905 
# Loading work.g_mac_top
1906 
# Loading work.g_dpath_ctrl
1907 
# Loading work.g_eth_parser
1908 
# Loading work.g_mac_core
1909 
# Loading work.g_rx_top
1910 
# Loading work.g_rx_fsm
1911 
# Loading work.half_dup_dble_reg
1912 
# Loading work.g_rx_crc32
1913 
# Loading work.g_deferral_rx
1914 
# Loading work.g_md_intf
1915 
# Loading work.g_tx_top
1916 
# Loading work.g_deferral
1917 
# Loading work.g_tx_fsm
1918 
# Loading work.g_tx_crc32
1919 
# Loading work.toggle_sync
1920 
# Loading work.g_cfg_mgmt
1921 
# Loading work.s2f_sync
1922 
# Loading work.generic_register
1923 
# Loading work.req_register
1924 
# Loading work.stat_counter
1925 
# Loading work.generic_intr_stat_reg
1926 
# Loading work.g_mii_intf
1927 
# Loading work.async_fifo
1928 
# Loading work.wb_rd_mem2mem
1929 
# Loading work.wb_wr_mem2mem
1930 
# Loading work.uart_core
1931 
# Loading work.uart_cfg
1932 
# Loading work.stat_register
1933 
# Loading work.uart_txfsm
1934 
# Loading work.uart_rxfsm
1935 
# Loading work.double_sync_low
1936 
# Loading work.spi_core
1937 
# Loading work.spi_if
1938 
# Loading work.spi_ctl
1939 
# Loading work.spi_cfg
1940 
# Loading work.oc8051_top
1941 
# Loading work.oc8051_decoder
1942 
# Loading work.oc8051_alu
1943 
# Loading work.oc8051_multiply
1944 
# Loading work.oc8051_divide
1945 
# Loading work.oc8051_ram_top
1946 
# Loading work.oc8051_ram_256x8_two_bist
1947 
# Loading work.oc8051_alu_src_sel
1948 
# Loading work.oc8051_comp
1949 
# Loading work.oc8051_rom
1950 
# Loading work.oc8051_cy_select
1951 
# Loading work.oc8051_indi_addr
1952 
# Loading work.oc8051_memory_interface
1953 
# Loading work.oc8051_sfr
1954 
# Loading work.oc8051_acc
1955 
# Loading work.oc8051_b_register
1956 
# Loading work.oc8051_sp
1957 
# Loading work.oc8051_dptr
1958 
# Loading work.oc8051_psw
1959 
# Loading work.oc8051_ports
1960 
# Loading work.oc8051_int
1961 
# Loading work.oc8051_tc
1962 
# Loading work.oc8051_tc2
1963 
# Loading work.oc8051_xrom
1964 
# Loading work.oc8051_xram
1965 
# Loading work.tb_eth_top
1966 
# Loading work.tb_mii
1967 
# Loading work.tb_rmii
1968 
# Loading work.uart_agent
1969 
# Loading work.m25p20
1970 
# Loading work.memory_access
1971 
# Loading work.acdc_check
1972 
# Loading work.internal_logic
1973 
# Loading work.AT45DB321
1974 
# Loading work.tb_glbl
1975 
# Loading work.bit_register
1976 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
1977 
#           File in use by:   Hostname:   ProcessID: 14
1978 
#           Attempting to use alternate WLF file "./wlftin6zdt".
1979 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
1980 
#           Using alternate file: ./wlftin6zdt
1981 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
1982 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
1983 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
1984 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
1985 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
1986 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
1987 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
1988 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
1989 
# do run.do
1990 
# i : 02
1991 
# i : 00
1992 
# i : 08
1993 
# i : 12
1994 
# i : 00
1995 
# i : 64
1996 
# i : 80
1997 
# i : fe
1998 
# i : 75
1999 
# i : 81
2000 
# NOTE : Load memory with Initial delivery content
2001 
# NOTE : Initial Load End
2002 
# NOTE: COMMUNICATION (RE)STARTED
2003 
################################
2004 
# time                45976 Passed
2005 
################################
2006 
# ** Note: $finish    : ../tb/tb_top.v(448)
2007 
#    Time: 46076 ns  Iteration: 0  Instance: /tb_top
2008 
### test 2: divmul --> PASSED
2009 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
2010 
 
2011 
# 6.6d
2012 
 
2013 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
2014 
# //  ModelSim ACTEL 6.6d Nov  2 2010
2015 
# //
2016 
# //  Copyright 1991-2010 Mentor Graphics Corporation
2017 
# //              All Rights Reserved.
2018 
# //
2019 
# //  THIS WORK CONTAINS TRADE SECRET AND
2020 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
2021 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
2022 
# //  AND IS SUBJECT TO LICENSE TERMS.
2023 
# //
2024 
# Loading sv_std.std
2025 
# Loading work.tb_top
2026 
# Loading work.turbo8051
2027 
# Loading work.clkgen
2028 
# Loading work.clk_ctl
2029 
# Loading work.wb_crossbar
2030 
# Loading work.g_mac_top
2031 
# Loading work.g_dpath_ctrl
2032 
# Loading work.g_eth_parser
2033 
# Loading work.g_mac_core
2034 
# Loading work.g_rx_top
2035 
# Loading work.g_rx_fsm
2036 
# Loading work.half_dup_dble_reg
2037 
# Loading work.g_rx_crc32
2038 
# Loading work.g_deferral_rx
2039 
# Loading work.g_md_intf
2040 
# Loading work.g_tx_top
2041 
# Loading work.g_deferral
2042 
# Loading work.g_tx_fsm
2043 
# Loading work.g_tx_crc32
2044 
# Loading work.toggle_sync
2045 
# Loading work.g_cfg_mgmt
2046 
# Loading work.s2f_sync
2047 
# Loading work.generic_register
2048 
# Loading work.req_register
2049 
# Loading work.stat_counter
2050 
# Loading work.generic_intr_stat_reg
2051 
# Loading work.g_mii_intf
2052 
# Loading work.async_fifo
2053 
# Loading work.wb_rd_mem2mem
2054 
# Loading work.wb_wr_mem2mem
2055 
# Loading work.uart_core
2056 
# Loading work.uart_cfg
2057 
# Loading work.stat_register
2058 
# Loading work.uart_txfsm
2059 
# Loading work.uart_rxfsm
2060 
# Loading work.double_sync_low
2061 
# Loading work.spi_core
2062 
# Loading work.spi_if
2063 
# Loading work.spi_ctl
2064 
# Loading work.spi_cfg
2065 
# Loading work.oc8051_top
2066 
# Loading work.oc8051_decoder
2067 
# Loading work.oc8051_alu
2068 
# Loading work.oc8051_multiply
2069 
# Loading work.oc8051_divide
2070 
# Loading work.oc8051_ram_top
2071 
# Loading work.oc8051_ram_256x8_two_bist
2072 
# Loading work.oc8051_alu_src_sel
2073 
# Loading work.oc8051_comp
2074 
# Loading work.oc8051_rom
2075 
# Loading work.oc8051_cy_select
2076 
# Loading work.oc8051_indi_addr
2077 
# Loading work.oc8051_memory_interface
2078 
# Loading work.oc8051_sfr
2079 
# Loading work.oc8051_acc
2080 
# Loading work.oc8051_b_register
2081 
# Loading work.oc8051_sp
2082 
# Loading work.oc8051_dptr
2083 
# Loading work.oc8051_psw
2084 
# Loading work.oc8051_ports
2085 
# Loading work.oc8051_int
2086 
# Loading work.oc8051_tc
2087 
# Loading work.oc8051_tc2
2088 
# Loading work.oc8051_xrom
2089 
# Loading work.oc8051_xram
2090 
# Loading work.tb_eth_top
2091 
# Loading work.tb_mii
2092 
# Loading work.tb_rmii
2093 
# Loading work.uart_agent
2094 
# Loading work.m25p20
2095 
# Loading work.memory_access
2096 
# Loading work.acdc_check
2097 
# Loading work.internal_logic
2098 
# Loading work.AT45DB321
2099 
# Loading work.tb_glbl
2100 
# Loading work.bit_register
2101 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
2102 
#           File in use by:   Hostname:   ProcessID: 14
2103 
#           Attempting to use alternate WLF file "./wlfty0wib6".
2104 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
2105 
#           Using alternate file: ./wlfty0wib6
2106 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
2107 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
2108 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
2109 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
2110 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
2111 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
2112 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
2113 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
2114 
# do run.do
2115 
# i : 02
2116 
# i : 00
2117 
# i : 08
2118 
# i : 12
2119 
# i : 01
2120 
# i : 1f
2121 
# i : 80
2122 
# i : fe
2123 
# i : 75
2124 
# i : 81
2125 
# NOTE : Load memory with Initial delivery content
2126 
# NOTE : Initial Load End
2127 
# NOTE: COMMUNICATION (RE)STARTED
2128 
################################
2129 
# time               184436 Passed
2130 
################################
2131 
# ** Note: $finish    : ../tb/tb_top.v(448)
2132 
#    Time: 184536 ns  Iteration: 0  Instance: /tb_top
2133 
### test 3: sort --> PASSED
2134 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
2135 
 
2136 
# 6.6d
2137 
 
2138 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
2139 
# //  ModelSim ACTEL 6.6d Nov  2 2010
2140 
# //
2141 
# //  Copyright 1991-2010 Mentor Graphics Corporation
2142 
# //              All Rights Reserved.
2143 
# //
2144 
# //  THIS WORK CONTAINS TRADE SECRET AND
2145 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
2146 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
2147 
# //  AND IS SUBJECT TO LICENSE TERMS.
2148 
# //
2149 
# Loading sv_std.std
2150 
# Loading work.tb_top
2151 
# Loading work.turbo8051
2152 
# Loading work.clkgen
2153 
# Loading work.clk_ctl
2154 
# Loading work.wb_crossbar
2155 
# Loading work.g_mac_top
2156 
# Loading work.g_dpath_ctrl
2157 
# Loading work.g_eth_parser
2158 
# Loading work.g_mac_core
2159 
# Loading work.g_rx_top
2160 
# Loading work.g_rx_fsm
2161 
# Loading work.half_dup_dble_reg
2162 
# Loading work.g_rx_crc32
2163 
# Loading work.g_deferral_rx
2164 
# Loading work.g_md_intf
2165 
# Loading work.g_tx_top
2166 
# Loading work.g_deferral
2167 
# Loading work.g_tx_fsm
2168 
# Loading work.g_tx_crc32
2169 
# Loading work.toggle_sync
2170 
# Loading work.g_cfg_mgmt
2171 
# Loading work.s2f_sync
2172 
# Loading work.generic_register
2173 
# Loading work.req_register
2174 
# Loading work.stat_counter
2175 
# Loading work.generic_intr_stat_reg
2176 
# Loading work.g_mii_intf
2177 
# Loading work.async_fifo
2178 
# Loading work.wb_rd_mem2mem
2179 
# Loading work.wb_wr_mem2mem
2180 
# Loading work.uart_core
2181 
# Loading work.uart_cfg
2182 
# Loading work.stat_register
2183 
# Loading work.uart_txfsm
2184 
# Loading work.uart_rxfsm
2185 
# Loading work.double_sync_low
2186 
# Loading work.spi_core
2187 
# Loading work.spi_if
2188 
# Loading work.spi_ctl
2189 
# Loading work.spi_cfg
2190 
# Loading work.oc8051_top
2191 
# Loading work.oc8051_decoder
2192 
# Loading work.oc8051_alu
2193 
# Loading work.oc8051_multiply
2194 
# Loading work.oc8051_divide
2195 
# Loading work.oc8051_ram_top
2196 
# Loading work.oc8051_ram_256x8_two_bist
2197 
# Loading work.oc8051_alu_src_sel
2198 
# Loading work.oc8051_comp
2199 
# Loading work.oc8051_rom
2200 
# Loading work.oc8051_cy_select
2201 
# Loading work.oc8051_indi_addr
2202 
# Loading work.oc8051_memory_interface
2203 
# Loading work.oc8051_sfr
2204 
# Loading work.oc8051_acc
2205 
# Loading work.oc8051_b_register
2206 
# Loading work.oc8051_sp
2207 
# Loading work.oc8051_dptr
2208 
# Loading work.oc8051_psw
2209 
# Loading work.oc8051_ports
2210 
# Loading work.oc8051_int
2211 
# Loading work.oc8051_tc
2212 
# Loading work.oc8051_tc2
2213 
# Loading work.oc8051_xrom
2214 
# Loading work.oc8051_xram
2215 
# Loading work.tb_eth_top
2216 
# Loading work.tb_mii
2217 
# Loading work.tb_rmii
2218 
# Loading work.uart_agent
2219 
# Loading work.m25p20
2220 
# Loading work.memory_access
2221 
# Loading work.acdc_check
2222 
# Loading work.internal_logic
2223 
# Loading work.AT45DB321
2224 
# Loading work.tb_glbl
2225 
# Loading work.bit_register
2226 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
2227 
#           File in use by:   Hostname:   ProcessID: 14
2228 
#           Attempting to use alternate WLF file "./wlftddiavq".
2229 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
2230 
#           Using alternate file: ./wlftddiavq
2231 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
2232 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
2233 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
2234 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
2235 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
2236 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
2237 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
2238 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
2239 
# do run.do
2240 
# i : 02
2241 
# i : 00
2242 
# i : 08
2243 
# i : 12
2244 
# i : 00
2245 
# i : 64
2246 
# i : 80
2247 
# i : fe
2248 
# i : 75
2249 
# i : 81
2250 
# NOTE : Load memory with Initial delivery content
2251 
# NOTE : Initial Load End
2252 
# NOTE: COMMUNICATION (RE)STARTED
2253 
################################
2254 
# time                33776 Passed
2255 
################################
2256 
# ** Note: $finish    : ../tb/tb_top.v(448)
2257 
#    Time: 33876 ns  Iteration: 0  Instance: /tb_top
2258 
### test 4: gcd --> PASSED
2259 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
2260 
 
2261 
# 6.6d
2262 
 
2263 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
2264 
# //  ModelSim ACTEL 6.6d Nov  2 2010
2265 
# //
2266 
# //  Copyright 1991-2010 Mentor Graphics Corporation
2267 
# //              All Rights Reserved.
2268 
# //
2269 
# //  THIS WORK CONTAINS TRADE SECRET AND
2270 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
2271 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
2272 
# //  AND IS SUBJECT TO LICENSE TERMS.
2273 
# //
2274 
# Loading sv_std.std
2275 
# Loading work.tb_top
2276 
# Loading work.turbo8051
2277 
# Loading work.clkgen
2278 
# Loading work.clk_ctl
2279 
# Loading work.wb_crossbar
2280 
# Loading work.g_mac_top
2281 
# Loading work.g_dpath_ctrl
2282 
# Loading work.g_eth_parser
2283 
# Loading work.g_mac_core
2284 
# Loading work.g_rx_top
2285 
# Loading work.g_rx_fsm
2286 
# Loading work.half_dup_dble_reg
2287 
# Loading work.g_rx_crc32
2288 
# Loading work.g_deferral_rx
2289 
# Loading work.g_md_intf
2290 
# Loading work.g_tx_top
2291 
# Loading work.g_deferral
2292 
# Loading work.g_tx_fsm
2293 
# Loading work.g_tx_crc32
2294 
# Loading work.toggle_sync
2295 
# Loading work.g_cfg_mgmt
2296 
# Loading work.s2f_sync
2297 
# Loading work.generic_register
2298 
# Loading work.req_register
2299 
# Loading work.stat_counter
2300 
# Loading work.generic_intr_stat_reg
2301 
# Loading work.g_mii_intf
2302 
# Loading work.async_fifo
2303 
# Loading work.wb_rd_mem2mem
2304 
# Loading work.wb_wr_mem2mem
2305 
# Loading work.uart_core
2306 
# Loading work.uart_cfg
2307 
# Loading work.stat_register
2308 
# Loading work.uart_txfsm
2309 
# Loading work.uart_rxfsm
2310 
# Loading work.double_sync_low
2311 
# Loading work.spi_core
2312 
# Loading work.spi_if
2313 
# Loading work.spi_ctl
2314 
# Loading work.spi_cfg
2315 
# Loading work.oc8051_top
2316 
# Loading work.oc8051_decoder
2317 
# Loading work.oc8051_alu
2318 
# Loading work.oc8051_multiply
2319 
# Loading work.oc8051_divide
2320 
# Loading work.oc8051_ram_top
2321 
# Loading work.oc8051_ram_256x8_two_bist
2322 
# Loading work.oc8051_alu_src_sel
2323 
# Loading work.oc8051_comp
2324 
# Loading work.oc8051_rom
2325 
# Loading work.oc8051_cy_select
2326 
# Loading work.oc8051_indi_addr
2327 
# Loading work.oc8051_memory_interface
2328 
# Loading work.oc8051_sfr
2329 
# Loading work.oc8051_acc
2330 
# Loading work.oc8051_b_register
2331 
# Loading work.oc8051_sp
2332 
# Loading work.oc8051_dptr
2333 
# Loading work.oc8051_psw
2334 
# Loading work.oc8051_ports
2335 
# Loading work.oc8051_int
2336 
# Loading work.oc8051_tc
2337 
# Loading work.oc8051_tc2
2338 
# Loading work.oc8051_xrom
2339 
# Loading work.oc8051_xram
2340 
# Loading work.tb_eth_top
2341 
# Loading work.tb_mii
2342 
# Loading work.tb_rmii
2343 
# Loading work.uart_agent
2344 
# Loading work.m25p20
2345 
# Loading work.memory_access
2346 
# Loading work.acdc_check
2347 
# Loading work.internal_logic
2348 
# Loading work.AT45DB321
2349 
# Loading work.tb_glbl
2350 
# Loading work.bit_register
2351 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
2352 
#           File in use by:   Hostname:   ProcessID: 14
2353 
#           Attempting to use alternate WLF file "./wlftfiaaw0".
2354 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
2355 
#           Using alternate file: ./wlftfiaaw0
2356 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
2357 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
2358 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
2359 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
2360 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
2361 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
2362 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
2363 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
2364 
# do run.do
2365 
# i : 02
2366 
# i : 00
2367 
# i : 08
2368 
# i : 12
2369 
# i : 00
2370 
# i : 65
2371 
# i : 80
2372 
# i : fe
2373 
# i : 75
2374 
# i : 81
2375 
# NOTE : Load memory with Initial delivery content
2376 
# NOTE : Initial Load End
2377 
# NOTE: COMMUNICATION (RE)STARTED
2378 
################################
2379 
# time                29536 Passed
2380 
################################
2381 
# ** Note: $finish    : ../tb/tb_top.v(448)
2382 
#    Time: 29636 ns  Iteration: 0  Instance: /tb_top
2383 
### test 5: cast --> PASSED
2384 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
2385 
 
2386 
# 6.6d
2387 
 
2388 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
2389 
# //  ModelSim ACTEL 6.6d Nov  2 2010
2390 
# //
2391 
# //  Copyright 1991-2010 Mentor Graphics Corporation
2392 
# //              All Rights Reserved.
2393 
# //
2394 
# //  THIS WORK CONTAINS TRADE SECRET AND
2395 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
2396 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
2397 
# //  AND IS SUBJECT TO LICENSE TERMS.
2398 
# //
2399 
# Loading sv_std.std
2400 
# Loading work.tb_top
2401 
# Loading work.turbo8051
2402 
# Loading work.clkgen
2403 
# Loading work.clk_ctl
2404 
# Loading work.wb_crossbar
2405 
# Loading work.g_mac_top
2406 
# Loading work.g_dpath_ctrl
2407 
# Loading work.g_eth_parser
2408 
# Loading work.g_mac_core
2409 
# Loading work.g_rx_top
2410 
# Loading work.g_rx_fsm
2411 
# Loading work.half_dup_dble_reg
2412 
# Loading work.g_rx_crc32
2413 
# Loading work.g_deferral_rx
2414 
# Loading work.g_md_intf
2415 
# Loading work.g_tx_top
2416 
# Loading work.g_deferral
2417 
# Loading work.g_tx_fsm
2418 
# Loading work.g_tx_crc32
2419 
# Loading work.toggle_sync
2420 
# Loading work.g_cfg_mgmt
2421 
# Loading work.s2f_sync
2422 
# Loading work.generic_register
2423 
# Loading work.req_register
2424 
# Loading work.stat_counter
2425 
# Loading work.generic_intr_stat_reg
2426 
# Loading work.g_mii_intf
2427 
# Loading work.async_fifo
2428 
# Loading work.wb_rd_mem2mem
2429 
# Loading work.wb_wr_mem2mem
2430 
# Loading work.uart_core
2431 
# Loading work.uart_cfg
2432 
# Loading work.stat_register
2433 
# Loading work.uart_txfsm
2434 
# Loading work.uart_rxfsm
2435 
# Loading work.double_sync_low
2436 
# Loading work.spi_core
2437 
# Loading work.spi_if
2438 
# Loading work.spi_ctl
2439 
# Loading work.spi_cfg
2440 
# Loading work.oc8051_top
2441 
# Loading work.oc8051_decoder
2442 
# Loading work.oc8051_alu
2443 
# Loading work.oc8051_multiply
2444 
# Loading work.oc8051_divide
2445 
# Loading work.oc8051_ram_top
2446 
# Loading work.oc8051_ram_256x8_two_bist
2447 
# Loading work.oc8051_alu_src_sel
2448 
# Loading work.oc8051_comp
2449 
# Loading work.oc8051_rom
2450 
# Loading work.oc8051_cy_select
2451 
# Loading work.oc8051_indi_addr
2452 
# Loading work.oc8051_memory_interface
2453 
# Loading work.oc8051_sfr
2454 
# Loading work.oc8051_acc
2455 
# Loading work.oc8051_b_register
2456 
# Loading work.oc8051_sp
2457 
# Loading work.oc8051_dptr
2458 
# Loading work.oc8051_psw
2459 
# Loading work.oc8051_ports
2460 
# Loading work.oc8051_int
2461 
# Loading work.oc8051_tc
2462 
# Loading work.oc8051_tc2
2463 
# Loading work.oc8051_xrom
2464 
# Loading work.oc8051_xram
2465 
# Loading work.tb_eth_top
2466 
# Loading work.tb_mii
2467 
# Loading work.tb_rmii
2468 
# Loading work.uart_agent
2469 
# Loading work.m25p20
2470 
# Loading work.memory_access
2471 
# Loading work.acdc_check
2472 
# Loading work.internal_logic
2473 
# Loading work.AT45DB321
2474 
# Loading work.tb_glbl
2475 
# Loading work.bit_register
2476 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
2477 
#           File in use by:   Hostname:   ProcessID: 14
2478 
#           Attempting to use alternate WLF file "./wlftc8emq2".
2479 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
2480 
#           Using alternate file: ./wlftc8emq2
2481 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
2482 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
2483 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
2484 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
2485 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
2486 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
2487 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
2488 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
2489 
# do run.do
2490 
# i : 02
2491 
# i : 00
2492 
# i : 08
2493 
# i : 12
2494 
# i : 00
2495 
# i : 64
2496 
# i : 80
2497 
# i : fe
2498 
# i : 75
2499 
# i : 81
2500 
# NOTE : Load memory with Initial delivery content
2501 
# NOTE : Initial Load End
2502 
# NOTE: COMMUNICATION (RE)STARTED
2503 
################################
2504 
# time              4411896 Passed
2505 
################################
2506 
# ** Note: $finish    : ../tb/tb_top.v(448)
2507 
#    Time: 4411996 ns  Iteration: 0  Instance: /tb_top
2508 
### test 6: xram --> PASSED
2509 
###########################################
2510 
 
2511 
 
2512 
###########################################
2513 
### tesing 8051 programs from internal rom
2514 
###########################################
2515 
###########################################
2516 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
2517 
 
2518 
# 6.6d
2519 
 
2520 
# vsim +INTERNAL_ROM -do run.do -c tb_top
2521 
# //  ModelSim ACTEL 6.6d Nov  2 2010
2522 
# //
2523 
# //  Copyright 1991-2010 Mentor Graphics Corporation
2524 
# //              All Rights Reserved.
2525 
# //
2526 
# //  THIS WORK CONTAINS TRADE SECRET AND
2527 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
2528 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
2529 
# //  AND IS SUBJECT TO LICENSE TERMS.
2530 
# //
2531 
# Loading sv_std.std
2532 
# Loading work.tb_top
2533 
# Loading work.turbo8051
2534 
# Loading work.clkgen
2535 
# Loading work.clk_ctl
2536 
# Loading work.wb_crossbar
2537 
# Loading work.g_mac_top
2538 
# Loading work.g_dpath_ctrl
2539 
# Loading work.g_eth_parser
2540 
# Loading work.g_mac_core
2541 
# Loading work.g_rx_top
2542 
# Loading work.g_rx_fsm
2543 
# Loading work.half_dup_dble_reg
2544 
# Loading work.g_rx_crc32
2545 
# Loading work.g_deferral_rx
2546 
# Loading work.g_md_intf
2547 
# Loading work.g_tx_top
2548 
# Loading work.g_deferral
2549 
# Loading work.g_tx_fsm
2550 
# Loading work.g_tx_crc32
2551 
# Loading work.toggle_sync
2552 
# Loading work.g_cfg_mgmt
2553 
# Loading work.s2f_sync
2554 
# Loading work.generic_register
2555 
# Loading work.req_register
2556 
# Loading work.stat_counter
2557 
# Loading work.generic_intr_stat_reg
2558 
# Loading work.g_mii_intf
2559 
# Loading work.async_fifo
2560 
# Loading work.wb_rd_mem2mem
2561 
# Loading work.wb_wr_mem2mem
2562 
# Loading work.uart_core
2563 
# Loading work.uart_cfg
2564 
# Loading work.stat_register
2565 
# Loading work.uart_txfsm
2566 
# Loading work.uart_rxfsm
2567 
# Loading work.double_sync_low
2568 
# Loading work.spi_core
2569 
# Loading work.spi_if
2570 
# Loading work.spi_ctl
2571 
# Loading work.spi_cfg
2572 
# Loading work.oc8051_top
2573 
# Loading work.oc8051_decoder
2574 
# Loading work.oc8051_alu
2575 
# Loading work.oc8051_multiply
2576 
# Loading work.oc8051_divide
2577 
# Loading work.oc8051_ram_top
2578 
# Loading work.oc8051_ram_256x8_two_bist
2579 
# Loading work.oc8051_alu_src_sel
2580 
# Loading work.oc8051_comp
2581 
# Loading work.oc8051_rom
2582 
# Loading work.oc8051_cy_select
2583 
# Loading work.oc8051_indi_addr
2584 
# Loading work.oc8051_memory_interface
2585 
# Loading work.oc8051_sfr
2586 
# Loading work.oc8051_acc
2587 
# Loading work.oc8051_b_register
2588 
# Loading work.oc8051_sp
2589 
# Loading work.oc8051_dptr
2590 
# Loading work.oc8051_psw
2591 
# Loading work.oc8051_ports
2592 
# Loading work.oc8051_int
2593 
# Loading work.oc8051_tc
2594 
# Loading work.oc8051_tc2
2595 
# Loading work.oc8051_xrom
2596 
# Loading work.oc8051_xram
2597 
# Loading work.tb_eth_top
2598 
# Loading work.tb_mii
2599 
# Loading work.tb_rmii
2600 
# Loading work.uart_agent
2601 
# Loading work.m25p20
2602 
# Loading work.memory_access
2603 
# Loading work.acdc_check
2604 
# Loading work.internal_logic
2605 
# Loading work.AT45DB321
2606 
# Loading work.tb_glbl
2607 
# Loading work.bit_register
2608 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
2609 
#           File in use by:   Hostname:   ProcessID: 14
2610 
#           Attempting to use alternate WLF file "./wlft2f91sk".
2611 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
2612 
#           Using alternate file: ./wlft2f91sk
2613 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
2614 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
2615 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
2616 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
2617 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
2618 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
2619 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
2620 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
2621 
# do run.do
2622 
# i : 02
2623 
# i : 00
2624 
# i : 08
2625 
# i : 12
2626 
# i : 01
2627 
# i : 51
2628 
# i : 80
2629 
# i : fe
2630 
# i : 75
2631 
# i : 81
2632 
# NOTE : Load memory with Initial delivery content
2633 
# NOTE : Initial Load End
2634 
# NOTE: COMMUNICATION (RE)STARTED
2635 
################################
2636 
# time                62216 Passed
2637 
################################
2638 
# ** Note: $finish    : ../tb/tb_top.v(448)
2639 
#    Time: 62316 ns  Iteration: 0  Instance: /tb_top
2640 
### test 1: fib --> PASSED
2641 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
2642 
 
2643 
# 6.6d
2644 
 
2645 
# vsim +INTERNAL_ROM -do run.do -c tb_top
2646 
# //  ModelSim ACTEL 6.6d Nov  2 2010
2647 
# //
2648 
# //  Copyright 1991-2010 Mentor Graphics Corporation
2649 
# //              All Rights Reserved.
2650 
# //
2651 
# //  THIS WORK CONTAINS TRADE SECRET AND
2652 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
2653 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
2654 
# //  AND IS SUBJECT TO LICENSE TERMS.
2655 
# //
2656 
# Loading sv_std.std
2657 
# Loading work.tb_top
2658 
# Loading work.turbo8051
2659 
# Loading work.clkgen
2660 
# Loading work.clk_ctl
2661 
# Loading work.wb_crossbar
2662 
# Loading work.g_mac_top
2663 
# Loading work.g_dpath_ctrl
2664 
# Loading work.g_eth_parser
2665 
# Loading work.g_mac_core
2666 
# Loading work.g_rx_top
2667 
# Loading work.g_rx_fsm
2668 
# Loading work.half_dup_dble_reg
2669 
# Loading work.g_rx_crc32
2670 
# Loading work.g_deferral_rx
2671 
# Loading work.g_md_intf
2672 
# Loading work.g_tx_top
2673 
# Loading work.g_deferral
2674 
# Loading work.g_tx_fsm
2675 
# Loading work.g_tx_crc32
2676 
# Loading work.toggle_sync
2677 
# Loading work.g_cfg_mgmt
2678 
# Loading work.s2f_sync
2679 
# Loading work.generic_register
2680 
# Loading work.req_register
2681 
# Loading work.stat_counter
2682 
# Loading work.generic_intr_stat_reg
2683 
# Loading work.g_mii_intf
2684 
# Loading work.async_fifo
2685 
# Loading work.wb_rd_mem2mem
2686 
# Loading work.wb_wr_mem2mem
2687 
# Loading work.uart_core
2688 
# Loading work.uart_cfg
2689 
# Loading work.stat_register
2690 
# Loading work.uart_txfsm
2691 
# Loading work.uart_rxfsm
2692 
# Loading work.double_sync_low
2693 
# Loading work.spi_core
2694 
# Loading work.spi_if
2695 
# Loading work.spi_ctl
2696 
# Loading work.spi_cfg
2697 
# Loading work.oc8051_top
2698 
# Loading work.oc8051_decoder
2699 
# Loading work.oc8051_alu
2700 
# Loading work.oc8051_multiply
2701 
# Loading work.oc8051_divide
2702 
# Loading work.oc8051_ram_top
2703 
# Loading work.oc8051_ram_256x8_two_bist
2704 
# Loading work.oc8051_alu_src_sel
2705 
# Loading work.oc8051_comp
2706 
# Loading work.oc8051_rom
2707 
# Loading work.oc8051_cy_select
2708 
# Loading work.oc8051_indi_addr
2709 
# Loading work.oc8051_memory_interface
2710 
# Loading work.oc8051_sfr
2711 
# Loading work.oc8051_acc
2712 
# Loading work.oc8051_b_register
2713 
# Loading work.oc8051_sp
2714 
# Loading work.oc8051_dptr
2715 
# Loading work.oc8051_psw
2716 
# Loading work.oc8051_ports
2717 
# Loading work.oc8051_int
2718 
# Loading work.oc8051_tc
2719 
# Loading work.oc8051_tc2
2720 
# Loading work.oc8051_xrom
2721 
# Loading work.oc8051_xram
2722 
# Loading work.tb_eth_top
2723 
# Loading work.tb_mii
2724 
# Loading work.tb_rmii
2725 
# Loading work.uart_agent
2726 
# Loading work.m25p20
2727 
# Loading work.memory_access
2728 
# Loading work.acdc_check
2729 
# Loading work.internal_logic
2730 
# Loading work.AT45DB321
2731 
# Loading work.tb_glbl
2732 
# Loading work.bit_register
2733 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
2734 
#           File in use by:   Hostname:   ProcessID: 14
2735 
#           Attempting to use alternate WLF file "./wlftckcg14".
2736 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
2737 
#           Using alternate file: ./wlftckcg14
2738 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
2739 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
2740 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
2741 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
2742 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
2743 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
2744 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
2745 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
2746 
# do run.do
2747 
# i : 02
2748 
# i : 00
2749 
# i : 08
2750 
# i : 12
2751 
# i : 00
2752 
# i : 64
2753 
# i : 80
2754 
# i : fe
2755 
# i : 75
2756 
# i : 81
2757 
# NOTE : Load memory with Initial delivery content
2758 
# NOTE : Initial Load End
2759 
# NOTE: COMMUNICATION (RE)STARTED
2760 
################################
2761 
# time                45976 Passed
2762 
################################
2763 
# ** Note: $finish    : ../tb/tb_top.v(448)
2764 
#    Time: 46076 ns  Iteration: 0  Instance: /tb_top
2765 
### test 2: divmul --> PASSED
2766 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
2767 
 
2768 
# 6.6d
2769 
 
2770 
# vsim +INTERNAL_ROM -do run.do -c tb_top
2771 
# //  ModelSim ACTEL 6.6d Nov  2 2010
2772 
# //
2773 
# //  Copyright 1991-2010 Mentor Graphics Corporation
2774 
# //              All Rights Reserved.
2775 
# //
2776 
# //  THIS WORK CONTAINS TRADE SECRET AND
2777 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
2778 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
2779 
# //  AND IS SUBJECT TO LICENSE TERMS.
2780 
# //
2781 
# Loading sv_std.std
2782 
# Loading work.tb_top
2783 
# Loading work.turbo8051
2784 
# Loading work.clkgen
2785 
# Loading work.clk_ctl
2786 
# Loading work.wb_crossbar
2787 
# Loading work.g_mac_top
2788 
# Loading work.g_dpath_ctrl
2789 
# Loading work.g_eth_parser
2790 
# Loading work.g_mac_core
2791 
# Loading work.g_rx_top
2792 
# Loading work.g_rx_fsm
2793 
# Loading work.half_dup_dble_reg
2794 
# Loading work.g_rx_crc32
2795 
# Loading work.g_deferral_rx
2796 
# Loading work.g_md_intf
2797 
# Loading work.g_tx_top
2798 
# Loading work.g_deferral
2799 
# Loading work.g_tx_fsm
2800 
# Loading work.g_tx_crc32
2801 
# Loading work.toggle_sync
2802 
# Loading work.g_cfg_mgmt
2803 
# Loading work.s2f_sync
2804 
# Loading work.generic_register
2805 
# Loading work.req_register
2806 
# Loading work.stat_counter
2807 
# Loading work.generic_intr_stat_reg
2808 
# Loading work.g_mii_intf
2809 
# Loading work.async_fifo
2810 
# Loading work.wb_rd_mem2mem
2811 
# Loading work.wb_wr_mem2mem
2812 
# Loading work.uart_core
2813 
# Loading work.uart_cfg
2814 
# Loading work.stat_register
2815 
# Loading work.uart_txfsm
2816 
# Loading work.uart_rxfsm
2817 
# Loading work.double_sync_low
2818 
# Loading work.spi_core
2819 
# Loading work.spi_if
2820 
# Loading work.spi_ctl
2821 
# Loading work.spi_cfg
2822 
# Loading work.oc8051_top
2823 
# Loading work.oc8051_decoder
2824 
# Loading work.oc8051_alu
2825 
# Loading work.oc8051_multiply
2826 
# Loading work.oc8051_divide
2827 
# Loading work.oc8051_ram_top
2828 
# Loading work.oc8051_ram_256x8_two_bist
2829 
# Loading work.oc8051_alu_src_sel
2830 
# Loading work.oc8051_comp
2831 
# Loading work.oc8051_rom
2832 
# Loading work.oc8051_cy_select
2833 
# Loading work.oc8051_indi_addr
2834 
# Loading work.oc8051_memory_interface
2835 
# Loading work.oc8051_sfr
2836 
# Loading work.oc8051_acc
2837 
# Loading work.oc8051_b_register
2838 
# Loading work.oc8051_sp
2839 
# Loading work.oc8051_dptr
2840 
# Loading work.oc8051_psw
2841 
# Loading work.oc8051_ports
2842 
# Loading work.oc8051_int
2843 
# Loading work.oc8051_tc
2844 
# Loading work.oc8051_tc2
2845 
# Loading work.oc8051_xrom
2846 
# Loading work.oc8051_xram
2847 
# Loading work.tb_eth_top
2848 
# Loading work.tb_mii
2849 
# Loading work.tb_rmii
2850 
# Loading work.uart_agent
2851 
# Loading work.m25p20
2852 
# Loading work.memory_access
2853 
# Loading work.acdc_check
2854 
# Loading work.internal_logic
2855 
# Loading work.AT45DB321
2856 
# Loading work.tb_glbl
2857 
# Loading work.bit_register
2858 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
2859 
#           File in use by:   Hostname:   ProcessID: 14
2860 
#           Attempting to use alternate WLF file "./wlftq1m3jq".
2861 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
2862 
#           Using alternate file: ./wlftq1m3jq
2863 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
2864 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
2865 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
2866 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
2867 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
2868 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
2869 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
2870 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
2871 
# do run.do
2872 
# i : 02
2873 
# i : 00
2874 
# i : 08
2875 
# i : 12
2876 
# i : 01
2877 
# i : 1f
2878 
# i : 80
2879 
# i : fe
2880 
# i : 75
2881 
# i : 81
2882 
# NOTE : Load memory with Initial delivery content
2883 
# NOTE : Initial Load End
2884 
# NOTE: COMMUNICATION (RE)STARTED
2885 
################################
2886 
# time               184436 Passed
2887 
################################
2888 
# ** Note: $finish    : ../tb/tb_top.v(448)
2889 
#    Time: 184536 ns  Iteration: 0  Instance: /tb_top
2890 
### test 3: sort --> PASSED
2891 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
2892 
 
2893 
# 6.6d
2894 
 
2895 
# vsim +INTERNAL_ROM -do run.do -c tb_top
2896 
# //  ModelSim ACTEL 6.6d Nov  2 2010
2897 
# //
2898 
# //  Copyright 1991-2010 Mentor Graphics Corporation
2899 
# //              All Rights Reserved.
2900 
# //
2901 
# //  THIS WORK CONTAINS TRADE SECRET AND
2902 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
2903 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
2904 
# //  AND IS SUBJECT TO LICENSE TERMS.
2905 
# //
2906 
# Loading sv_std.std
2907 
# Loading work.tb_top
2908 
# Loading work.turbo8051
2909 
# Loading work.clkgen
2910 
# Loading work.clk_ctl
2911 
# Loading work.wb_crossbar
2912 
# Loading work.g_mac_top
2913 
# Loading work.g_dpath_ctrl
2914 
# Loading work.g_eth_parser
2915 
# Loading work.g_mac_core
2916 
# Loading work.g_rx_top
2917 
# Loading work.g_rx_fsm
2918 
# Loading work.half_dup_dble_reg
2919 
# Loading work.g_rx_crc32
2920 
# Loading work.g_deferral_rx
2921 
# Loading work.g_md_intf
2922 
# Loading work.g_tx_top
2923 
# Loading work.g_deferral
2924 
# Loading work.g_tx_fsm
2925 
# Loading work.g_tx_crc32
2926 
# Loading work.toggle_sync
2927 
# Loading work.g_cfg_mgmt
2928 
# Loading work.s2f_sync
2929 
# Loading work.generic_register
2930 
# Loading work.req_register
2931 
# Loading work.stat_counter
2932 
# Loading work.generic_intr_stat_reg
2933 
# Loading work.g_mii_intf
2934 
# Loading work.async_fifo
2935 
# Loading work.wb_rd_mem2mem
2936 
# Loading work.wb_wr_mem2mem
2937 
# Loading work.uart_core
2938 
# Loading work.uart_cfg
2939 
# Loading work.stat_register
2940 
# Loading work.uart_txfsm
2941 
# Loading work.uart_rxfsm
2942 
# Loading work.double_sync_low
2943 
# Loading work.spi_core
2944 
# Loading work.spi_if
2945 
# Loading work.spi_ctl
2946 
# Loading work.spi_cfg
2947 
# Loading work.oc8051_top
2948 
# Loading work.oc8051_decoder
2949 
# Loading work.oc8051_alu
2950 
# Loading work.oc8051_multiply
2951 
# Loading work.oc8051_divide
2952 
# Loading work.oc8051_ram_top
2953 
# Loading work.oc8051_ram_256x8_two_bist
2954 
# Loading work.oc8051_alu_src_sel
2955 
# Loading work.oc8051_comp
2956 
# Loading work.oc8051_rom
2957 
# Loading work.oc8051_cy_select
2958 
# Loading work.oc8051_indi_addr
2959 
# Loading work.oc8051_memory_interface
2960 
# Loading work.oc8051_sfr
2961 
# Loading work.oc8051_acc
2962 
# Loading work.oc8051_b_register
2963 
# Loading work.oc8051_sp
2964 
# Loading work.oc8051_dptr
2965 
# Loading work.oc8051_psw
2966 
# Loading work.oc8051_ports
2967 
# Loading work.oc8051_int
2968 
# Loading work.oc8051_tc
2969 
# Loading work.oc8051_tc2
2970 
# Loading work.oc8051_xrom
2971 
# Loading work.oc8051_xram
2972 
# Loading work.tb_eth_top
2973 
# Loading work.tb_mii
2974 
# Loading work.tb_rmii
2975 
# Loading work.uart_agent
2976 
# Loading work.m25p20
2977 
# Loading work.memory_access
2978 
# Loading work.acdc_check
2979 
# Loading work.internal_logic
2980 
# Loading work.AT45DB321
2981 
# Loading work.tb_glbl
2982 
# Loading work.bit_register
2983 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
2984 
#           File in use by:   Hostname:   ProcessID: 14
2985 
#           Attempting to use alternate WLF file "./wlfttxndz9".
2986 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
2987 
#           Using alternate file: ./wlfttxndz9
2988 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
2989 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
2990 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
2991 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
2992 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
2993 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
2994 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
2995 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
2996 
# do run.do
2997 
# i : 02
2998 
# i : 00
2999 
# i : 08
3000 
# i : 12
3001 
# i : 00
3002 
# i : 64
3003 
# i : 80
3004 
# i : fe
3005 
# i : 75
3006 
# i : 81
3007 
# NOTE : Load memory with Initial delivery content
3008 
# NOTE : Initial Load End
3009 
# NOTE: COMMUNICATION (RE)STARTED
3010 
################################
3011 
# time                33776 Passed
3012 
################################
3013 
# ** Note: $finish    : ../tb/tb_top.v(448)
3014 
#    Time: 33876 ns  Iteration: 0  Instance: /tb_top
3015 
### test 4: gcd --> PASSED
3016 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
3017 
 
3018 
# 6.6d
3019 
 
3020 
# vsim +INTERNAL_ROM -do run.do -c tb_top
3021 
# //  ModelSim ACTEL 6.6d Nov  2 2010
3022 
# //
3023 
# //  Copyright 1991-2010 Mentor Graphics Corporation
3024 
# //              All Rights Reserved.
3025 
# //
3026 
# //  THIS WORK CONTAINS TRADE SECRET AND
3027 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
3028 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
3029 
# //  AND IS SUBJECT TO LICENSE TERMS.
3030 
# //
3031 
# Loading sv_std.std
3032 
# Loading work.tb_top
3033 
# Loading work.turbo8051
3034 
# Loading work.clkgen
3035 
# Loading work.clk_ctl
3036 
# Loading work.wb_crossbar
3037 
# Loading work.g_mac_top
3038 
# Loading work.g_dpath_ctrl
3039 
# Loading work.g_eth_parser
3040 
# Loading work.g_mac_core
3041 
# Loading work.g_rx_top
3042 
# Loading work.g_rx_fsm
3043 
# Loading work.half_dup_dble_reg
3044 
# Loading work.g_rx_crc32
3045 
# Loading work.g_deferral_rx
3046 
# Loading work.g_md_intf
3047 
# Loading work.g_tx_top
3048 
# Loading work.g_deferral
3049 
# Loading work.g_tx_fsm
3050 
# Loading work.g_tx_crc32
3051 
# Loading work.toggle_sync
3052 
# Loading work.g_cfg_mgmt
3053 
# Loading work.s2f_sync
3054 
# Loading work.generic_register
3055 
# Loading work.req_register
3056 
# Loading work.stat_counter
3057 
# Loading work.generic_intr_stat_reg
3058 
# Loading work.g_mii_intf
3059 
# Loading work.async_fifo
3060 
# Loading work.wb_rd_mem2mem
3061 
# Loading work.wb_wr_mem2mem
3062 
# Loading work.uart_core
3063 
# Loading work.uart_cfg
3064 
# Loading work.stat_register
3065 
# Loading work.uart_txfsm
3066 
# Loading work.uart_rxfsm
3067 
# Loading work.double_sync_low
3068 
# Loading work.spi_core
3069 
# Loading work.spi_if
3070 
# Loading work.spi_ctl
3071 
# Loading work.spi_cfg
3072 
# Loading work.oc8051_top
3073 
# Loading work.oc8051_decoder
3074 
# Loading work.oc8051_alu
3075 
# Loading work.oc8051_multiply
3076 
# Loading work.oc8051_divide
3077 
# Loading work.oc8051_ram_top
3078 
# Loading work.oc8051_ram_256x8_two_bist
3079 
# Loading work.oc8051_alu_src_sel
3080 
# Loading work.oc8051_comp
3081 
# Loading work.oc8051_rom
3082 
# Loading work.oc8051_cy_select
3083 
# Loading work.oc8051_indi_addr
3084 
# Loading work.oc8051_memory_interface
3085 
# Loading work.oc8051_sfr
3086 
# Loading work.oc8051_acc
3087 
# Loading work.oc8051_b_register
3088 
# Loading work.oc8051_sp
3089 
# Loading work.oc8051_dptr
3090 
# Loading work.oc8051_psw
3091 
# Loading work.oc8051_ports
3092 
# Loading work.oc8051_int
3093 
# Loading work.oc8051_tc
3094 
# Loading work.oc8051_tc2
3095 
# Loading work.oc8051_xrom
3096 
# Loading work.oc8051_xram
3097 
# Loading work.tb_eth_top
3098 
# Loading work.tb_mii
3099 
# Loading work.tb_rmii
3100 
# Loading work.uart_agent
3101 
# Loading work.m25p20
3102 
# Loading work.memory_access
3103 
# Loading work.acdc_check
3104 
# Loading work.internal_logic
3105 
# Loading work.AT45DB321
3106 
# Loading work.tb_glbl
3107 
# Loading work.bit_register
3108 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
3109 
#           File in use by:   Hostname:   ProcessID: 14
3110 
#           Attempting to use alternate WLF file "./wlft1sdqy9".
3111 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
3112 
#           Using alternate file: ./wlft1sdqy9
3113 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
3114 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
3115 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
3116 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
3117 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
3118 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
3119 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
3120 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
3121 
# do run.do
3122 
# i : 02
3123 
# i : 00
3124 
# i : 08
3125 
# i : 12
3126 
# i : 00
3127 
# i : 65
3128 
# i : 80
3129 
# i : fe
3130 
# i : 75
3131 
# i : 81
3132 
# NOTE : Load memory with Initial delivery content
3133 
# NOTE : Initial Load End
3134 
# NOTE: COMMUNICATION (RE)STARTED
3135 
################################
3136 
# time                29536 Passed
3137 
################################
3138 
# ** Note: $finish    : ../tb/tb_top.v(448)
3139 
#    Time: 29636 ns  Iteration: 0  Instance: /tb_top
3140 
### test 5: cast --> PASSED
3141 
Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
3142 
 
3143 
# 6.6d
3144 
 
3145 
# vsim +INTERNAL_ROM -do run.do -c tb_top
3146 
# //  ModelSim ACTEL 6.6d Nov  2 2010
3147 
# //
3148 
# //  Copyright 1991-2010 Mentor Graphics Corporation
3149 
# //              All Rights Reserved.
3150 
# //
3151 
# //  THIS WORK CONTAINS TRADE SECRET AND
3152 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
3153 
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
3154 
# //  AND IS SUBJECT TO LICENSE TERMS.
3155 
# //
3156 
# Loading sv_std.std
3157 
# Loading work.tb_top
3158 
# Loading work.turbo8051
3159 
# Loading work.clkgen
3160 
# Loading work.clk_ctl
3161 
# Loading work.wb_crossbar
3162 
# Loading work.g_mac_top
3163 
# Loading work.g_dpath_ctrl
3164 
# Loading work.g_eth_parser
3165 
# Loading work.g_mac_core
3166 
# Loading work.g_rx_top
3167 
# Loading work.g_rx_fsm
3168 
# Loading work.half_dup_dble_reg
3169 
# Loading work.g_rx_crc32
3170 
# Loading work.g_deferral_rx
3171 
# Loading work.g_md_intf
3172 
# Loading work.g_tx_top
3173 
# Loading work.g_deferral
3174 
# Loading work.g_tx_fsm
3175 
# Loading work.g_tx_crc32
3176 
# Loading work.toggle_sync
3177 
# Loading work.g_cfg_mgmt
3178 
# Loading work.s2f_sync
3179 
# Loading work.generic_register
3180 
# Loading work.req_register
3181 
# Loading work.stat_counter
3182 
# Loading work.generic_intr_stat_reg
3183 
# Loading work.g_mii_intf
3184 
# Loading work.async_fifo
3185 
# Loading work.wb_rd_mem2mem
3186 
# Loading work.wb_wr_mem2mem
3187 
# Loading work.uart_core
3188 
# Loading work.uart_cfg
3189 
# Loading work.stat_register
3190 
# Loading work.uart_txfsm
3191 
# Loading work.uart_rxfsm
3192 
# Loading work.double_sync_low
3193 
# Loading work.spi_core
3194 
# Loading work.spi_if
3195 
# Loading work.spi_ctl
3196 
# Loading work.spi_cfg
3197 
# Loading work.oc8051_top
3198 
# Loading work.oc8051_decoder
3199 
# Loading work.oc8051_alu
3200 
# Loading work.oc8051_multiply
3201 
# Loading work.oc8051_divide
3202 
# Loading work.oc8051_ram_top
3203 
# Loading work.oc8051_ram_256x8_two_bist
3204 
# Loading work.oc8051_alu_src_sel
3205 
# Loading work.oc8051_comp
3206 
# Loading work.oc8051_rom
3207 
# Loading work.oc8051_cy_select
3208 
# Loading work.oc8051_indi_addr
3209 
# Loading work.oc8051_memory_interface
3210 
# Loading work.oc8051_sfr
3211 
# Loading work.oc8051_acc
3212 
# Loading work.oc8051_b_register
3213 
# Loading work.oc8051_sp
3214 
# Loading work.oc8051_dptr
3215 
# Loading work.oc8051_psw
3216 
# Loading work.oc8051_ports
3217 
# Loading work.oc8051_int
3218 
# Loading work.oc8051_tc
3219 
# Loading work.oc8051_tc2
3220 
# Loading work.oc8051_xrom
3221 
# Loading work.oc8051_xram
3222 
# Loading work.tb_eth_top
3223 
# Loading work.tb_mii
3224 
# Loading work.tb_rmii
3225 
# Loading work.uart_agent
3226 
# Loading work.m25p20
3227 
# Loading work.memory_access
3228 
# Loading work.acdc_check
3229 
# Loading work.internal_logic
3230 
# Loading work.AT45DB321
3231 
# Loading work.tb_glbl
3232 
# Loading work.bit_register
3233 
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
3234 
#           File in use by:   Hostname:   ProcessID: 14
3235 
#           Attempting to use alternate WLF file "./wlftixja49".
3236 
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
3237 
#           Using alternate file: ./wlftixja49
3238 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
3239 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
3240 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
3241 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
3242 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
3243 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
3244 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
3245 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
3246 
# do run.do
3247 
# i : 02
3248 
# i : 00
3249 
# i : 08
3250 
# i : 12
3251 
# i : 00
3252 
# i : 64
3253 
# i : 80
3254 
# i : fe
3255 
# i : 75
3256 
# i : 81
3257 
# NOTE : Load memory with Initial delivery content
3258 
# NOTE : Initial Load End
3259 
# NOTE: COMMUNICATION (RE)STARTED
3260 
################################
3261 
# time              4411896 Passed
3262 
################################
3263 
# ** Note: $finish    : ../tb/tb_top.v(448)
3264 
#    Time: 4411996 ns  Iteration: 0  Instance: /tb_top
3265 
### test 6: xram --> PASSED
3266 
###########################################
3267 
 
3268 
###########################################
3269 
###  Test Summary
3270 
###
3271 
### Failed 0 of 4 misc tests
3272 
### Failed 0 of 6 external rom tests
3273 
### Failed 0 of 6 internal rom tests
3274 
###########################################

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