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[/] [turbo8051/] [trunk/] [verif/] [log/] [uart_test_1.log] - Blame information for rev 76

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1 76 dinesha
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
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# 10.1b
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# vsim +uart_test_1 -do run.do -c tb_top
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# //  ModelSim ACTEL 10.1b Apr 27 2012
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# //
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# //  Copyright 1991-2012 Mentor Graphics Corporation
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# //  All Rights Reserved.
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# //
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# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
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# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
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# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
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# //
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# Loading sv_std.std
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# Loading work.tb_top
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# Loading work.digital_core
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# Loading work.clkgen
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# Loading work.clk_ctl
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# Loading work.wb_crossbar
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# Loading work.g_mac_top
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# Loading work.g_dpath_ctrl
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# Loading work.g_eth_parser
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# Loading work.g_mac_core
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# Loading work.g_rx_top
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# Loading work.g_rx_fsm
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# Loading work.half_dup_dble_reg
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# Loading work.g_rx_crc32
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# Loading work.g_deferral_rx
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# Loading work.g_md_intf
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# Loading work.g_tx_top
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# Loading work.g_deferral
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# Loading work.g_tx_fsm
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# Loading work.g_tx_crc32
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# Loading work.toggle_sync
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# Loading work.g_cfg_mgmt
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# Loading work.s2f_sync
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# Loading work.generic_register
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# Loading work.req_register
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# Loading work.stat_counter
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# Loading work.generic_intr_stat_reg
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# Loading work.g_mii_intf
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# Loading work.async_fifo
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# Loading work.wb_rd_mem2mem
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# Loading work.wb_wr_mem2mem
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# Loading work.uart_core
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# Loading work.uart_cfg
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# Loading work.stat_register
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# Loading work.uart_txfsm
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# Loading work.uart_rxfsm
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# Loading work.double_sync_low
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# Loading work.spi_core
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# Loading work.spi_if
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# Loading work.spi_ctl
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# Loading work.spi_cfg
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# Loading work.oc8051_top
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# Loading work.oc8051_decoder
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# Loading work.oc8051_alu
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# Loading work.oc8051_multiply
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# Loading work.oc8051_divide
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# Loading work.oc8051_ram_top
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# Loading work.oc8051_ram_256x8_two_bist
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# Loading work.oc8051_alu_src_sel
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# Loading work.oc8051_comp
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# Loading work.oc8051_cy_select
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# Loading work.oc8051_indi_addr
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# Loading work.oc8051_memory_interface
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# Loading work.oc8051_sfr
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# Loading work.oc8051_acc
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# Loading work.oc8051_b_register
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# Loading work.oc8051_sp
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# Loading work.oc8051_dptr
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# Loading work.oc8051_psw
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# Loading work.oc8051_ports
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# Loading work.oc8051_int
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# Loading work.oc8051_tc
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# Loading work.oc8051_tc2
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# Loading work.oc8051_xrom
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# Loading work.oc8051_xram
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# Loading work.tb_eth_top
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# Loading work.tb_mii
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# Loading work.tb_rmii
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# Loading work.uart_agent
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# Loading work.m25p20
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# Loading work.memory_access
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# Loading work.acdc_check
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# Loading work.internal_logic
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# Loading work.AT45DB321
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# Loading work.tb_glbl
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# Loading work.bit_register
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# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(397): [TOFD] - System task or function '$shm_open' is not defined.
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#
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#         Region: /tb_top
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# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(398): [TOFD] - System task or function '$shm_probe' is not defined.
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#
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#         Region: /tb_top
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# ** Warning: (vsim-3017) ../tb/tb_top.v(235): [TFMPC] - Too few port connections. Expected 50, found 44.
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#
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#         Region: /tb_top/u_core
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# ** Warning: (vsim-3015) ../tb/tb_top.v(235): [PCDPC] - Port size (8 or 8) does not match connection size (4) for port 'phy_txd'. The port definition is at: ../../rtl/core/digital_core.v(29).
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#
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#         Region: /tb_top/u_core
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# ** Warning: (vsim-3015) ../tb/tb_top.v(235): [PCDPC] - Port size (8 or 8) does not match connection size (4) for port 'phy_rxd'. The port definition is at: ../../rtl/core/digital_core.v(35).
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#
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#         Region: /tb_top/u_core
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'scan_mode'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'scan_enable'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_clk'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_in'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_out'.
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#
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# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_out_en'.
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#
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# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(214): [TFMPC] - Too few port connections. Expected 14, found 12.
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#
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#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(214): [TFMPC] - Missing connection for port 'afull'.
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#
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(214): [TFMPC] - Missing connection for port 'aempty'.
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#
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# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(230): [TFMPC] - Too few port connections. Expected 14, found 12.
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#
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#         Region: /tb_top/u_core/u_uart_core/u_txfifo
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(230): [TFMPC] - Missing connection for port 'afull'.
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#
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(230): [TFMPC] - Missing connection for port 'aempty'.
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#
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# do run.do
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# NOTE : Load memory with Initial delivery content
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# NOTE : Initial Load End
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# --> Dumpping the design
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# NOTE: COMMUNICATION (RE)STARTED
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# Config-Write: Id: 3 Addr = 0000, Cfg. Data = 00000017
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#
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# ... Writing char 24 ...
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# ... Write data 24 to UART done cnt :          1 ...
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#
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#
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# ... Writing char 81 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  24
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# ... Read Data from UART done cnt :         1...
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# ... Write data 81 to UART done cnt :          2 ...
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#
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#
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# ... Writing char 09 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  81
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# ... Read Data from UART done cnt :         2...
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# ... Write data 09 to UART done cnt :          3 ...
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#
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#
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# ... Writing char 63 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  09
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# ... Read Data from UART done cnt :         3...
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# ... Write data 63 to UART done cnt :          4 ...
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#
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#
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# ... Writing char 0d ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  63
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# ... Read Data from UART done cnt :         4...
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# ... Write data 0d to UART done cnt :          5 ...
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#
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#
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# ... Writing char 8d ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0d
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# ... Read Data from UART done cnt :         5...
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# ... Write data 8d to UART done cnt :          6 ...
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#
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#
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# ... Writing char 65 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  8d
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# ... Read Data from UART done cnt :         6...
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# ... Write data 65 to UART done cnt :          7 ...
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#
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#
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# ... Writing char 12 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  65
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# ... Read Data from UART done cnt :         7...
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# ... Write data 12 to UART done cnt :          8 ...
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#
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#
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# ... Writing char 01 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  12
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# ... Read Data from UART done cnt :         8...
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# ... Write data 01 to UART done cnt :          9 ...
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#
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#
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# ... Writing char 0d ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  01
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# ... Read Data from UART done cnt :         9...
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# ... Write data 0d to UART done cnt :         10 ...
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#
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#
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# ... Writing char 76 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0d
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# ... Read Data from UART done cnt :        10...
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# ... Write data 76 to UART done cnt :         11 ...
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#
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#
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# ... Writing char 3d ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  76
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# ... Read Data from UART done cnt :        11...
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# ... Write data 3d to UART done cnt :         12 ...
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#
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#
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# ... Writing char ed ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  3d
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# ... Read Data from UART done cnt :        12...
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# ... Write data ed to UART done cnt :         13 ...
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#
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#
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# ... Writing char 8c ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  ed
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# ... Read Data from UART done cnt :        13...
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# ... Write data 8c to UART done cnt :         14 ...
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#
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#
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# ... Writing char f9 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  8c
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# ... Read Data from UART done cnt :        14...
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# ... Write data f9 to UART done cnt :         15 ...
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#
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#
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# ... Writing char c6 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  f9
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# ... Read Data from UART done cnt :        15...
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# ... Write data c6 to UART done cnt :         16 ...
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#
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#
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# ... Writing char c5 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  c6
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# ... Read Data from UART done cnt :        16...
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# ... Write data c5 to UART done cnt :         17 ...
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#
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#
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# ... Writing char aa ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  c5
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# ... Read Data from UART done cnt :        17...
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# ... Write data aa to UART done cnt :         18 ...
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#
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#
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# ... Writing char e5 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  aa
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# ... Read Data from UART done cnt :        18...
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# ... Write data e5 to UART done cnt :         19 ...
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#
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#
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# ... Writing char 77 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  e5
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# ... Read Data from UART done cnt :        19...
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# ... Write data 77 to UART done cnt :         20 ...
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#
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#
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# ... Writing char 12 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  77
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# ... Read Data from UART done cnt :        20...
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# ... Write data 12 to UART done cnt :         21 ...
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#
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#
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# ... Writing char 8f ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  12
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# ... Read Data from UART done cnt :        21...
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# ... Write data 8f to UART done cnt :         22 ...
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#
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#
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# ... Writing char f2 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  8f
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# ... Read Data from UART done cnt :        22...
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# ... Write data f2 to UART done cnt :         23 ...
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#
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#
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# ... Writing char ce ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  f2
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# ... Read Data from UART done cnt :        23...
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# ... Write data ce to UART done cnt :         24 ...
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#
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#
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# ... Writing char e8 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  ce
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# ... Read Data from UART done cnt :        24...
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# ... Write data e8 to UART done cnt :         25 ...
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#
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#
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# ... Writing char c5 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  e8
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# ... Read Data from UART done cnt :        25...
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# ... Write data c5 to UART done cnt :         26 ...
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#
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#
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# ... Writing char 5c ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  c5
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# ... Read Data from UART done cnt :        26...
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# ... Write data 5c to UART done cnt :         27 ...
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#
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#
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# ... Writing char bd ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  5c
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# ... Read Data from UART done cnt :        27...
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# ... Write data bd to UART done cnt :         28 ...
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#
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#
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# ... Writing char 2d ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  bd
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# ... Read Data from UART done cnt :        28...
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# ... Write data 2d to UART done cnt :         29 ...
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#
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#
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# ... Writing char 65 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  2d
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# ... Read Data from UART done cnt :        29...
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# ... Write data 65 to UART done cnt :         30 ...
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#
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#
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# ... Writing char 63 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  65
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# ... Read Data from UART done cnt :        30...
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# ... Write data 63 to UART done cnt :         31 ...
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#
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#
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# ... Writing char 0a ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  63
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# ... Read Data from UART done cnt :        31...
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# ... Write data 0a to UART done cnt :         32 ...
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#
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#
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# ... Writing char 80 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0a
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# ... Read Data from UART done cnt :        32...
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# ... Write data 80 to UART done cnt :         33 ...
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#
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#
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# ... Writing char 20 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  80
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# ... Read Data from UART done cnt :        33...
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# ... Write data 20 to UART done cnt :         34 ...
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#
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#
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# ... Writing char aa ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  20
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# ... Read Data from UART done cnt :        34...
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# ... Write data aa to UART done cnt :         35 ...
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#
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#
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# ... Writing char 9d ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  aa
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# ... Read Data from UART done cnt :        35...
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# ... Write data 9d to UART done cnt :         36 ...
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#
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#
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# ... Writing char 96 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  9d
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# ... Read Data from UART done cnt :        36...
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# ... Write data 96 to UART done cnt :         37 ...
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#
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#
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# ... Writing char 13 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  96
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# ... Read Data from UART done cnt :        37...
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# ... Write data 13 to UART done cnt :         38 ...
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#
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#
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# ... Writing char 0d ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  13
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# ... Read Data from UART done cnt :        38...
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# ... Write data 0d to UART done cnt :         39 ...
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#
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#
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# ... Writing char 53 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0d
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# ... Read Data from UART done cnt :        39...
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# ... Write data 53 to UART done cnt :         40 ...
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#
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match  53
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# ... Read Data from UART done cnt :        40...
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# -------------------- Reporting Configuration --------------------
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#       Data bit number setting is : 8
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#       Stop bit number setting is : 1
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#       Divisor of Uart clock   is : 3
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#       Parity is enable
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#       Even parity setting
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#       FIFO mode is disable
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# -----------------------------------------------------------------
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# -------------------- Reporting Status --------------------
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#
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#       Number of character received is :    40
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#       Number of character sent     is :    40
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#       Number of parity error rxd   is :     0
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#       Number of stop1  error rxd   is :     0
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#       Number of stop2  error rxd   is :     0
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#       Number of timeout error      is :     0
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#       Number of error              is :     0
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# -----------------------------------------------------------------
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#
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# -------------------------------------------------
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# Test Status
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# warnings: 0, errors: 0
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#
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# -------------------------------------------------
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# Test Status
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# warnings: 0, errors: 0
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#
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# =========
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# Test Status: TEST PASSED
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# =========
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#

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