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[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Blame information for rev 79

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
 
`include "tb_defines.v"
 
module tb_top;
 
 
reg    reset_n;
reg    reset;
reg    xtal_clk;
reg    ref_clk_125;
wire   app_clk;
reg    ref_clk_50;
reg    uart_clk_16x;
 
 
parameter XTAL_CLK_PERIOD = 10; // 100MHZ 40; // 25Mhz
parameter APP_CLK_PERIOD = 10;
parameter REF_CLK_125_PERIOD = 8;
parameter REF_CLK_50_PERIOD = 20;
parameter UART_REF_CLK_PERIOD = 20;
 
reg[31:0] events_log;
 
initial
begin
        reset_n = 1;
   #100 reset_n = 0;
   #100 reset_n = 1;
end
 
 
initial begin
  xtal_clk = 1'b0;
  forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;
end
 
 
//initial begin
//  app_clk = 1'b0;
//  forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;
//end
 
initial begin
  ref_clk_125 = 1'b0;
  forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;
end
 
initial begin
  ref_clk_50 = 1'b0;
  forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;
end
 
 
initial begin
  uart_clk_16x = 1'b0;
  forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;
end
 
 
wire [3:0]   phy_txd            ;
wire [3:0]   phy_rxd            ;
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
reg                reg_cs     ;
reg [3:0]          reg_id     ;
reg                reg_wr         ;
reg  [14:0]        reg_addr       ;
reg  [31:0]        reg_wdata      ;
reg  [3:0]         reg_be         ;
 
// Outputs
wire  [31:0]        reg_rdata      ;
wire                reg_ack        ;
 
reg                 master_mode   ;
reg                 ea_in   ;   // 1--> Internal Memory
 
 
wire         spi_sck            ;
wire         spi_so             ;
wire         spi_si             ;
wire [3:0]   spi_cs_n           ;
 
wire         clkout             ;
wire         reset_out_n        ;
 
//----------------------------------------
// 8051 core ROM related signals
//---------------------------------------
wire  [15:0]   wb_xrom_adr       ; // instruction address
wire           wb_xrom_ack       ; // instruction acknowlage
wire           wb_xrom_err       ; // instruction error
wire           wb_xrom_wr        ; // instruction error
wire    [31:0] wb_xrom_rdata     ; // rom data input
wire   [31:0]  wb_xrom_wdata     ; // rom data input
 
wire           wb_xrom_stb       ; // instruction strobe
wire           wb_xrom_cyc       ; // instruction cycle
 
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
wire   [15:0] wb_xram_adr        ; // data-ram address
wire          wb_xram_ack        ; // data-ram acknowlage
wire          wb_xram_err        ; // data-ram error
wire          wb_xram_wr         ; // data-ram error
wire   [3:0]  wb_xram_be         ; // data-ram error
wire   [31:0] wb_xram_rdata      ; // ram data input
wire   [31:0] wb_xram_wdata      ; // ram data input
 
wire          wb_xram_stb        ; // data-ram strobe
wire          wb_xram_cyc        ; // data-ram cycle
 
//----------------------------------------
 
digital_core  u_core (
 
             . reset_n             (reset_n            ),
             . fastsim_mode        (1'b1               ),
             . mastermode          (master_mode        ),
 
             . xtal_clk            (xtal_clk           ),
             . clkout              (app_clk            ),
             . reset_out_n         (reset_out_n        ),
 
        // Reg Bus Interface Signal
             . ext_reg_cs          (reg_cs             ),
             . ext_reg_tid         (reg_id             ),
             . ext_reg_wr          (reg_wr             ),
             . ext_reg_addr        (reg_addr[14:0]     ),
             . ext_reg_wdata       (reg_wdata          ),
             . ext_reg_be          (reg_be             ),
 
            // Outputs
             . ext_reg_rdata       (reg_rdata          ),
             . ext_reg_ack         (reg_ack            ),
 
 
          // Line Side Interface TX Path
             .phy_tx_en            (phy_tx_en          ),
             .phy_txd              (phy_txd            ),
             .phy_tx_clk           (phy_tx_clk         ),
 
          // Line Side Interface RX Path
             .phy_rx_clk           (phy_rx_clk         ),
             .phy_rx_dv            (phy_rx_dv          ),
             .phy_rxd              (phy_rxd            ),
 
          //MDIO interface
             //.MDC                  (MDC                ),
             //.MDIO                 (MDIO               ),
 
 
       // UART Line Interface
             .si                   (si                 ),
             .so                   (so                 ),
 
 
             .spi_sck              (spi_sck            ),
             .spi_so               (spi_so             ),
             .spi_si               (spi_si             ),
             .spi_cs_n             (spi_cs_n           ),
 
         // External ROM interface
               .wb_xrom_adr        (wb_xrom_adr        ),
               .wb_xrom_ack        (wb_xrom_ack        ),
               .wb_xrom_err        (wb_xrom_err        ),
               .wb_xrom_wr         (wb_xrom_wr         ),
               .wb_xrom_rdata      (wb_xrom_rdata      ),
               .wb_xrom_wdata      (wb_xrom_wdata      ),
 
               .wb_xrom_stb        (wb_xrom_stb        ),
               .wb_xrom_cyc        (wb_xrom_cyc        ),
 
         // External RAM interface
               .wb_xram_adr        (wb_xram_adr        ),
               .wb_xram_ack        (wb_xram_ack        ),
               .wb_xram_err        (wb_xram_err        ),
               .wb_xram_wr         (wb_xram_wr         ),
               .wb_xram_be         (wb_xram_be         ),
               .wb_xram_rdata      (wb_xram_rdata      ),
               .wb_xram_wdata      (wb_xram_wdata      ),
 
               .wb_xram_stb        (wb_xram_stb        ),
               .wb_xram_cyc        (wb_xram_cyc        ),
 
               .ea_in              (ea_in               ) // internal ROM
 
        );
 
 
  oc8051_xrom oc8051_xrom1
      (
             .rst                ( !reset_n         ),
             .clk                ( app_clk          ),
             .addr               ( wb_xrom_adr      ),
             .data               ( wb_xrom_rdata    ),
             .stb_i              ( wb_xrom_stb      ),
             .cyc_i              ( wb_xrom_cyc      ),
             .ack_o              ( wb_xrom_ack      )
      );
 
   defparam oc8051_xrom1.DELAY = 0;
 
 
//
// external data ram
//
oc8051_xram oc8051_xram1 (
          .clk               (app_clk       ),
          .rst               (!reset_n      ),
          .wr                (wb_xram_wr    ),
          .be                (wb_xram_be    ),
          .addr              (wb_xram_adr   ),
          .data_in           (wb_xram_wdata ),
          .data_out          (wb_xram_rdata ),
          .ack               (wb_xram_ack   ),
          .stb               (wb_xram_stb   )
      );
 
 
defparam oc8051_xram1.DELAY = 2;
 
 
 
 
tb_eth_top u_tb_eth (
 
               . REFCLK_50_MHz     (ref_clk_50         ), // 50 MHz Reference clock input
               . REFCLK_125_MHz    (ref_clk_125        ), // 125 MHz reference clock
               . transmit_enable   (1'b1               ), // transmit enable for testbench
 
          // Separate interfaces for each MII port type
 
          // Full MII, 4-bit interface
          // Transmit interface
               . MII_RXD           (phy_rxd[3:0]       ), // Receive data (output)
               . MII_RX_CLK        (phy_rx_clk         ), // Receive clock for MII (output)
               . MII_CRS           (phy_crs            ), // carrier sense (output)
               . MII_COL           (                   ), // Collision signal for MII (output)
               . MII_RX_DV         (phy_rx_dv          ), // Receive data valid for MII (output)
 
          // Receive interface
               . MII_TXD           (phy_txd[3:0]       ), // Transmit data (input)
               . MII_TX_EN         (phy_tx_en          ), // Tx enable (input)
               . MII_TX_CLK        (phy_tx_clk         ), // Transmit clock (output)
 
          // Reduced MII, 2-bit interface
          // Transmit interface
               . RMII_RXD          (                   ), // Receive data (output)
               . RMII_CRS_DV       (                   ), // carrier sense (output)
          // Receive interface
               . RMII_TXD          (                   ), // Transmit data (input)
               . RMII_TX_EN        (                   ), // Tx enable (input)
 
          // Serial MII interface
               . SMII_RXD          (                   ), // Receive data (output)
               . SMII_TXD          (                   ), // Transmit data (input)
               . SMII_SYNC         (                   ), // SMII SYNC signal (input)                
 
          // GMII, 8-bit/10-bit interface
          // Transmit interface
               . GMII_RXD          (                   ), // Receive data (output)
               . GMII_RX_CLK       (                   ), // Receive clock for MII (output)
               . GMII_CRS          (                   ), // carrier sense (output)
               . GMII_COL          (                   ), // Collision signal for MII (output)
               . GMII_RX_DV        (                   ), // Receive data valid for MII (output)
 
          // Receive interface
               . GMII_TXD          (                   ), // Transmit data (input)
               . GMII_TX_EN        (                   ), // Tx enable (input)
               . GMII_TX_CLK       (                   ), // Transmit clock (output)
               . GMII_GTX_CLK      (                   ), // Gigabit Tx clock (input), 125 MHz
 
              // MII management interface
               .MDIO               (MDC                ), // serial I/O data
               .MDC                (MDC                )  // clock
 
 
 
 
      );
 
 uart_agent tb_uart (
               . test_clk          (uart_clk_16x       ),
               . sin               (si                 ),
               . dsr_n             (                   ),
               . cts_n             (                   ),
               . dcd_n             (                   ),
 
               . sout              (so                 ),
               . dtr_n             (1'b0               ),
               . rts_n             (1'b0               ),
               . out1_n            (1'b0               ),
               . out2_n            (1'b0               )
       );
 
 
//----------------------- SPI Agents
 
m25p20 i_m25p20_0 (
               .c                  (spi_sck            ),
               .s                  (spi_cs_n[0]        ), // Include selection logic
               .w                  (1'b1               ), // Write protect is always disabled
               .hold               (1'b1               ), // Hold support not used
               .data_in            (spi_so             ),
               .data_out           (spi_si             )
             );
 
 
AT45DB321 i_AT45DB321_0 (
               .CSB                (spi_cs_n[1]        ),
               .SCK                (spi_sck            ),
               .SI                 (spi_so             ),
               .WPB                (1'b1               ),
               .RESETB             (1'b1               ),
               .RDY_BUSYB          (                   ),
               .SO                 (spi_si             )
      );
/***************
spi_agent_3120 spi_agent_3120_0 (
               .cs_b               (spi_cs_n[2]        ),
               .spi_din            (spi_si             ),
               .spi_dout           (spi_so             ),
               .spi_clk            (spi_sck            )
       );
 
spi_agent_3120 spi_agent_3120_1 (
               .cs_b               (spi_cs_n[3]        ),
               .spi_din            (spi_si             ),
               .spi_dout           (spi_so             ),
               .spi_clk            (spi_sck            )
       );
*****************/
 
tb_glbl  tb_glbl ();
 
 
`ifdef DUMP_ENABLE
initial begin
   if ( $test$plusargs("DUMP") ) begin
          $fsdbDumpfile("../dump/test_1.fsdb");
      $fsdbDumpvars;
      $fsdbDumpon;
   end
end
`endif
 
/***
initial begin //{
   $display ("--> Dumpping the design");
   $shm_open("simvision.shm");
   $shm_probe("AC");
end //}
***/
 
initial begin
                $dumpfile("simx.vcd");
                $dumpvars(0, tb_top);
end
 
 
 
initial begin
 
   if ( $test$plusargs("INTERNAL_ROM") )  begin
      ea_in       = 1;
      master_mode = 1;
   end else if ( $test$plusargs("EXTERNAL_ROM") ) begin
      ea_in       = 0;
      master_mode = 1;
   end else begin
      ea_in       = 0;
      master_mode = 0;
   end
 
  `TB_GLBL.init;
 
   // test case, which has control before reset
   if ( $test$plusargs("gmac_test_2") )
       gmac_test2();
   else if ( $test$plusargs("webserver") )
       webserver();
 
   #1000 wait(reset_out_n == 1);
 
   // test case, which has control after reset
   if ( $test$plusargs("gmac_test_1") )
       gmac_test1();
   else if ( $test$plusargs("uart_test_1") )
       uart_test1();
   else if ( $test$plusargs("spi_test_1") )
       spi_test1();
   else if ( !$test$plusargs("gmac_test_2") &&
             !$test$plusargs("webserver")) begin
     // 8051 Test Cases
     #80000000
     $display("time ",$time, "\n faulire: end of time\n \n");
   end
 
   `TB_GLBL.test_stats;
   `TB_GLBL.test_finish;
   #1000 $finish;
end
 
wire [7:0] p2_out = u_core.u_8051_core.p2_o;
wire [7:0] p3_out = u_core.u_8051_core.p3_o;
always @(p2_out or p3_out)
begin
  if((p2_out == 8'haa) &&      // fib.c
     (p3_out == 8'haa )) begin
      $display("################################");
      $display("time ",$time, " Passed");
      $display("################################");
      #100
      $finish;
  end else if(p2_out == 8'h55) begin     // fib.c
      $display("");
      $display("time ",$time," Error: %h", p3_out);
      $display("");
      #100
      $finish;
  end
end
 
 
 
 
`include "gmac_test1.v"
`include "gmac_test2.v"
`include "webserver.v"
`include "uart_test1.v"
`include "spi_test1.v"
`include "tb_tasks.v"
`include "spi_tasks.v"
 
 
endmodule
`include "tb_glbl.v"

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Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Blame information for rev 79

Line No.	Rev	Author	Line
1	15	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the Turbo 8051 cores project ////`
5			`//// http://www.opencores.org/cores/turbo8051/ ////`
6			`//// ////`
7			`//// Description ////`
8			`//// Turbo 8051 definitions. ////`
9			`//// ////`
10			`//// To Do: ////`
11			`//// nothing ////`
12			`//// ////`
13			`//// Author(s): ////`
14			`//// - Dinesh Annayya, dinesha@opencores.org ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43
44
45			`include "tb_defines.v"
46
47			`module tb_top;`
48
49
50			`reg reset_n;`
51			`reg reset;`
52			`reg xtal_clk;`
53			`reg ref_clk_125;`
54			`wire app_clk;`
55			`reg ref_clk_50;`
56			`reg uart_clk_16x;`
57
58
59	57	dinesha	`parameter XTAL_CLK_PERIOD = 10; // 100MHZ 40; // 25Mhz`
60	15	dinesha	`parameter APP_CLK_PERIOD = 10;`
61			`parameter REF_CLK_125_PERIOD = 8;`
62			`parameter REF_CLK_50_PERIOD = 20;`
63			`parameter UART_REF_CLK_PERIOD = 20;`
64
65			`reg[31:0] events_log;`
66
67			`initial`
68			`begin`
69			`reset_n = 1;`
70			`#100 reset_n = 0;`
71			`#100 reset_n = 1;`
72			`end`
73
74
75			`initial begin`
76			`xtal_clk = 1'b0;`
77			`forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;`
78			`end`
79
80
81			`//initial begin`
82			`// app_clk = 1'b0;`
83			`// forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;`
84			`//end`
85
86			`initial begin`
87			`ref_clk_125 = 1'b0;`
88			`forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;`
89			`end`
90
91			`initial begin`
92			`ref_clk_50 = 1'b0;`
93			`forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;`
94			`end`
95
96
97			`initial begin`
98			`uart_clk_16x = 1'b0;`
99			`forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;`
100			`end`
101
102
103	73	dinesha	`wire [3:0] phy_txd ;`
104			`wire [3:0] phy_rxd ;`
105	15	dinesha
106			`//---------------------------------`
107			`// Reg Bus Interface Signal`
108			`//---------------------------------`
109			`reg reg_cs ;`
110			`reg [3:0] reg_id ;`
111			`reg reg_wr ;`
112	56	dinesha	`reg [14:0] reg_addr ;`
113	15	dinesha	`reg [31:0] reg_wdata ;`
114			`reg [3:0] reg_be ;`
115
116			`// Outputs`
117			`wire [31:0] reg_rdata ;`
118			`wire reg_ack ;`
119
120	28	dinesha	`reg master_mode ;`
121			`reg ea_in ; // 1--> Internal Memory`
122	15	dinesha
123
124			`wire spi_sck ;`
125			`wire spi_so ;`
126			`wire spi_si ;`
127			`wire [3:0] spi_cs_n ;`
128
129			`wire clkout ;`
130			`wire reset_out_n ;`
131
132			`//----------------------------------------`
133			`// 8051 core ROM related signals`
134			`//---------------------------------------`
135			`wire [15:0] wb_xrom_adr ; // instruction address`
136			`wire wb_xrom_ack ; // instruction acknowlage`
137			`wire wb_xrom_err ; // instruction error`
138			`wire wb_xrom_wr ; // instruction error`
139			`wire [31:0] wb_xrom_rdata ; // rom data input`
140			`wire [31:0] wb_xrom_wdata ; // rom data input`
141
142			`wire wb_xrom_stb ; // instruction strobe`
143			`wire wb_xrom_cyc ; // instruction cycle`
144
145
146			`//----------------------------------------`
147			`// 8051 core RAM related signals`
148			`//---------------------------------------`
149			`wire [15:0] wb_xram_adr ; // data-ram address`
150			`wire wb_xram_ack ; // data-ram acknowlage`
151			`wire wb_xram_err ; // data-ram error`
152			`wire wb_xram_wr ; // data-ram error`
153	50	dinesha	`wire [3:0] wb_xram_be ; // data-ram error`
154			`wire [31:0] wb_xram_rdata ; // ram data input`
155			`wire [31:0] wb_xram_wdata ; // ram data input`
156	15	dinesha
157			`wire wb_xram_stb ; // data-ram strobe`
158			`wire wb_xram_cyc ; // data-ram cycle`
159
160			`//----------------------------------------`
161
162	76	dinesha	`digital_core u_core (`
163	15	dinesha
164			`. reset_n (reset_n ),`
165			`. fastsim_mode (1'b1 ),`
166	28	dinesha	`. mastermode (master_mode ),`
167	27	dinesha
168	15	dinesha	`. xtal_clk (xtal_clk ),`
169			`. clkout (app_clk ),`
170			`. reset_out_n (reset_out_n ),`
171
172			`// Reg Bus Interface Signal`
173			`. ext_reg_cs (reg_cs ),`
174			`. ext_reg_tid (reg_id ),`
175			`. ext_reg_wr (reg_wr ),`
176	56	dinesha	`. ext_reg_addr (reg_addr[14:0] ),`
177	15	dinesha	`. ext_reg_wdata (reg_wdata ),`
178			`. ext_reg_be (reg_be ),`
179
180			`// Outputs`
181			`. ext_reg_rdata (reg_rdata ),`
182			`. ext_reg_ack (reg_ack ),`
183
184
185			`// Line Side Interface TX Path`
186			`.phy_tx_en (phy_tx_en ),`
187			`.phy_txd (phy_txd ),`
188			`.phy_tx_clk (phy_tx_clk ),`
189
190			`// Line Side Interface RX Path`
191			`.phy_rx_clk (phy_rx_clk ),`
192			`.phy_rx_dv (phy_rx_dv ),`
193			`.phy_rxd (phy_rxd ),`
194
195			`//MDIO interface`
196	76	dinesha	`//.MDC (MDC ),`
197			`//.MDIO (MDIO ),`
198	15	dinesha
199
200			`// UART Line Interface`
201			`.si (si ),`
202			`.so (so ),`
203
204
205			`.spi_sck (spi_sck ),`
206			`.spi_so (spi_so ),`
207			`.spi_si (spi_si ),`
208			`.spi_cs_n (spi_cs_n ),`
209
210			`// External ROM interface`
211			`.wb_xrom_adr (wb_xrom_adr ),`
212			`.wb_xrom_ack (wb_xrom_ack ),`
213			`.wb_xrom_err (wb_xrom_err ),`
214			`.wb_xrom_wr (wb_xrom_wr ),`
215			`.wb_xrom_rdata (wb_xrom_rdata ),`
216			`.wb_xrom_wdata (wb_xrom_wdata ),`
217
218			`.wb_xrom_stb (wb_xrom_stb ),`
219			`.wb_xrom_cyc (wb_xrom_cyc ),`
220
221			`// External RAM interface`
222			`.wb_xram_adr (wb_xram_adr ),`
223			`.wb_xram_ack (wb_xram_ack ),`
224			`.wb_xram_err (wb_xram_err ),`
225			`.wb_xram_wr (wb_xram_wr ),`
226	50	dinesha	`.wb_xram_be (wb_xram_be ),`
227	15	dinesha	`.wb_xram_rdata (wb_xram_rdata ),`
228			`.wb_xram_wdata (wb_xram_wdata ),`
229
230			`.wb_xram_stb (wb_xram_stb ),`
231			`.wb_xram_cyc (wb_xram_cyc ),`
232
233	28	dinesha	`.ea_in (ea_in ) // internal ROM`
234	15	dinesha
235			`);`
236
237
238			`oc8051_xrom oc8051_xrom1`
239			`(`
240			`.rst ( !reset_n ),`
241			`.clk ( app_clk ),`
242			`.addr ( wb_xrom_adr ),`
243			`.data ( wb_xrom_rdata ),`
244			`.stb_i ( wb_xrom_stb ),`
245			`.cyc_i ( wb_xrom_cyc ),`
246			`.ack_o ( wb_xrom_ack )`
247			`);`
248
249			`defparam oc8051_xrom1.DELAY = 0;`
250
251
252			`//`
253			`// external data ram`
254			`//`
255			`oc8051_xram oc8051_xram1 (`
256			`.clk (app_clk ),`
257			`.rst (!reset_n ),`
258			`.wr (wb_xram_wr ),`
259	50	dinesha	`.be (wb_xram_be ),`
260	15	dinesha	`.addr (wb_xram_adr ),`
261			`.data_in (wb_xram_wdata ),`
262			`.data_out (wb_xram_rdata ),`
263			`.ack (wb_xram_ack ),`
264			`.stb (wb_xram_stb )`
265			`);`
266
267
268			`defparam oc8051_xram1.DELAY = 2;`
269
270
271
272
273			`tb_eth_top u_tb_eth (`
274
275			`. REFCLK_50_MHz (ref_clk_50 ), // 50 MHz Reference clock input`
276			`. REFCLK_125_MHz (ref_clk_125 ), // 125 MHz reference clock`
277			`. transmit_enable (1'b1 ), // transmit enable for testbench`
278
279			`// Separate interfaces for each MII port type`
280
281			`// Full MII, 4-bit interface`
282			`// Transmit interface`
283			`. MII_RXD (phy_rxd[3:0] ), // Receive data (output)`
284			`. MII_RX_CLK (phy_rx_clk ), // Receive clock for MII (output)`
285			`. MII_CRS (phy_crs ), // carrier sense (output)`
286			`. MII_COL ( ), // Collision signal for MII (output)`
287			`. MII_RX_DV (phy_rx_dv ), // Receive data valid for MII (output)`
288
289			`// Receive interface`
290			`. MII_TXD (phy_txd[3:0] ), // Transmit data (input)`
291			`. MII_TX_EN (phy_tx_en ), // Tx enable (input)`
292			`. MII_TX_CLK (phy_tx_clk ), // Transmit clock (output)`
293
294			`// Reduced MII, 2-bit interface`
295			`// Transmit interface`
296			`. RMII_RXD ( ), // Receive data (output)`
297			`. RMII_CRS_DV ( ), // carrier sense (output)`
298			`// Receive interface`
299			`. RMII_TXD ( ), // Transmit data (input)`
300			`. RMII_TX_EN ( ), // Tx enable (input)`
301
302			`// Serial MII interface`
303			`. SMII_RXD ( ), // Receive data (output)`
304			`. SMII_TXD ( ), // Transmit data (input)`
305			`. SMII_SYNC ( ), // SMII SYNC signal (input)`
306
307			`// GMII, 8-bit/10-bit interface`
308			`// Transmit interface`
309			`. GMII_RXD ( ), // Receive data (output)`
310			`. GMII_RX_CLK ( ), // Receive clock for MII (output)`
311			`. GMII_CRS ( ), // carrier sense (output)`
312			`. GMII_COL ( ), // Collision signal for MII (output)`
313			`. GMII_RX_DV ( ), // Receive data valid for MII (output)`
314
315			`// Receive interface`
316			`. GMII_TXD ( ), // Transmit data (input)`
317			`. GMII_TX_EN ( ), // Tx enable (input)`
318			`. GMII_TX_CLK ( ), // Transmit clock (output)`
319			`. GMII_GTX_CLK ( ), // Gigabit Tx clock (input), 125 MHz`
320
321			`// MII management interface`
322			`.MDIO (MDC ), // serial I/O data`
323			`.MDC (MDC ) // clock`
324
325
326
327
328			`);`
329
330			`uart_agent tb_uart (`
331			`. test_clk (uart_clk_16x ),`
332			`. sin (si ),`
333			`. dsr_n ( ),`
334			`. cts_n ( ),`
335			`. dcd_n ( ),`
336
337			`. sout (so ),`
338			`. dtr_n (1'b0 ),`
339			`. rts_n (1'b0 ),`
340			`. out1_n (1'b0 ),`
341			`. out2_n (1'b0 )`
342			`);`
343
344
345			`//----------------------- SPI Agents`
346
347			`m25p20 i_m25p20_0 (`
348			`.c (spi_sck ),`
349			`.s (spi_cs_n[0] ), // Include selection logic`
350			`.w (1'b1 ), // Write protect is always disabled`
351			`.hold (1'b1 ), // Hold support not used`
352			`.data_in (spi_so ),`
353			`.data_out (spi_si )`
354			`);`
355
356
357			`AT45DB321 i_AT45DB321_0 (`
358			`.CSB (spi_cs_n[1] ),`
359			`.SCK (spi_sck ),`
360			`.SI (spi_so ),`
361			`.WPB (1'b1 ),`
362			`.RESETB (1'b1 ),`
363			`.RDY_BUSYB ( ),`
364			`.SO (spi_si )`
365			`);`
366			`/***************`
367			`spi_agent_3120 spi_agent_3120_0 (`
368			`.cs_b (spi_cs_n[2] ),`
369			`.spi_din (spi_si ),`
370			`.spi_dout (spi_so ),`
371			`.spi_clk (spi_sck )`
372			`);`
373
374			`spi_agent_3120 spi_agent_3120_1 (`
375			`.cs_b (spi_cs_n[3] ),`
376			`.spi_din (spi_si ),`
377			`.spi_dout (spi_so ),`
378			`.spi_clk (spi_sck )`
379			`);`
380			`*****************/`
381
382			`tb_glbl tb_glbl ();`
383
384
385	57	dinesha	`ifdef DUMP_ENABLE
386	15	dinesha	`initial begin`
387			`if ( $test$plusargs("DUMP") ) begin`
388			`$fsdbDumpfile("../dump/test_1.fsdb");`
389			`$fsdbDumpvars;`
390			`$fsdbDumpon;`
391			`end`
392			`end`
393	57	dinesha	`endif
394	15	dinesha
395	79	dinesha	`/***`
396	76	dinesha	`initial begin //{`
397			`$display ("--> Dumpping the design");`
398			`$shm_open("simvision.shm");`
399			`$shm_probe("AC");`
400			`end //}`
401	79	dinesha	`***/`
402	76	dinesha
403	79	dinesha	`initial begin`
404			`$dumpfile("simx.vcd");`
405			`$dumpvars(0, tb_top);`
406			`end`
407	76	dinesha
408	79	dinesha
409
410	15	dinesha	`initial begin`
411
412	28	dinesha	`if ( $test$plusargs("INTERNAL_ROM") ) begin`
413			`ea_in = 1;`
414			`master_mode = 1;`
415			`end else if ( $test$plusargs("EXTERNAL_ROM") ) begin`
416			`ea_in = 0;`
417			`master_mode = 1;`
418			`end else begin`
419			`ea_in = 0;`
420			`master_mode = 0;`
421			`end`
422
423	15	dinesha	`TB_GLBL.init;
424	53	dinesha
425			`// test case, which has control before reset`
426			`if ( $test$plusargs("gmac_test_2") )`
427			`gmac_test2();`
428	61	dinesha	`else if ( $test$plusargs("webserver") )`
429			`webserver();`
430	53	dinesha
431	15	dinesha	`#1000 wait(reset_out_n == 1);`
432
433	53	dinesha	`// test case, which has control after reset`
434	15	dinesha	`if ( $test$plusargs("gmac_test_1") )`
435			`gmac_test1();`
436			`else if ( $test$plusargs("uart_test_1") )`
437			`uart_test1();`
438			`else if ( $test$plusargs("spi_test_1") )`
439			`spi_test1();`
440	61	dinesha	`else if ( !$test$plusargs("gmac_test_2") &&`
441			`!$test$plusargs("webserver")) begin`
442	15	dinesha	`// 8051 Test Cases`
443			`#80000000`
444			`$display("time ",$time, "\n faulire: end of time\n \n");`
445			`end`
446
447			`TB_GLBL.test_stats;
448			`TB_GLBL.test_finish;
449			`#1000 $finish;`
450			`end`
451
452			`wire [7:0] p2_out = u_core.u_8051_core.p2_o;`
453			`wire [7:0] p3_out = u_core.u_8051_core.p3_o;`
454			`always @(p2_out or p3_out)`
455			`begin`
456			`if((p2_out == 8'haa) && // fib.c`
457			`(p3_out == 8'haa )) begin`
458			`$display("################################");`
459			`$display("time ",$time, " Passed");`
460			`$display("################################");`
461			`#100`
462			`$finish;`
463			`end else if(p2_out == 8'h55) begin // fib.c`
464			`$display("");`
465			`$display("time ",$time," Error: %h", p3_out);`
466			`$display("");`
467			`#100`
468			`$finish;`
469			`end`
470			`end`
471
472
473
474
475			`include "gmac_test1.v"
476	52	dinesha	`include "gmac_test2.v"
477	61	dinesha	`include "webserver.v"
478	15	dinesha	`include "uart_test1.v"
479			`include "spi_test1.v"
480			`include "tb_tasks.v"
481			`include "spi_tasks.v"
482
483
484			`endmodule`
485			`include "tb_glbl.v"