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[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`timescale  1ns/1ps
 
`include "tb_defines.v"
 
module tb_top;
 
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0100 -- MAC core
// 4'b0011 -- UART
// 4'b0010 -- SPI core
// 4'b0001 -- External RAM
// 4'b0000 -- External ROM
//--------------------------------------------------------------
`define ADDR_SPACE_MAC  4'b0100
`define ADDR_SPACE_UART 4'b0011
`define ADDR_SPACE_SPI  4'b0010
`define ADDR_SPACE_RAM  4'b0001
`define ADDR_SPACE_ROM  4'b0000
 
reg    reset_n;
reg    reset;
reg    xtal_clk;
reg    ref_clk_125;
wire   app_clk;
reg    ref_clk_50;
reg    uart_clk_16x;
 
 
parameter XTAL_CLK_PERIOD = 40; // 25Mhz
parameter APP_CLK_PERIOD = 10;
parameter REF_CLK_125_PERIOD = 8;
parameter REF_CLK_50_PERIOD = 20;
parameter UART_REF_CLK_PERIOD = 20;
 
reg[31:0] events_log;
 
initial
begin
        reset_n = 1;
   #100 reset_n = 0;
   #100 reset_n = 1;
end
 
 
initial begin
  xtal_clk = 1'b0;
  forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;
end
 
 
//initial begin
//  app_clk = 1'b0;
//  forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;
//end
 
initial begin
  ref_clk_125 = 1'b0;
  forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;
end
 
initial begin
  ref_clk_50 = 1'b0;
  forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;
end
 
 
initial begin
  uart_clk_16x = 1'b0;
  forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;
end
 
 
wire [7:0]   phy_txd            ;
wire [7:0]   phy_rxd            ;
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
reg                reg_cs     ;
reg [3:0]          reg_id     ;
reg                reg_wr         ;
reg  [12:0]        reg_addr       ;
reg  [31:0]        reg_wdata      ;
reg  [3:0]         reg_be         ;
 
// Outputs
wire  [31:0]        reg_rdata      ;
wire                reg_ack        ;
 
 
 
wire         spi_sck            ;
wire         spi_so             ;
wire         spi_si             ;
wire [3:0]   spi_cs_n           ;
 
wire         clkout             ;
wire         reset_out_n        ;
 
//----------------------------------------
// 8051 core ROM related signals
//---------------------------------------
wire  [15:0]   wb_xrom_adr       ; // instruction address
wire           wb_xrom_ack       ; // instruction acknowlage
wire           wb_xrom_err       ; // instruction error
wire           wb_xrom_wr        ; // instruction error
wire    [31:0] wb_xrom_rdata     ; // rom data input
wire   [31:0]  wb_xrom_wdata     ; // rom data input
 
wire           wb_xrom_stb       ; // instruction strobe
wire           wb_xrom_cyc       ; // instruction cycle
 
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
wire   [15:0] wb_xram_adr        ; // data-ram address
wire          wb_xram_ack        ; // data-ram acknowlage
wire          wb_xram_err        ; // data-ram error
wire          wb_xram_wr         ; // data-ram error
wire   [7:0]  wb_xram_rdata      ; // ram data input
wire   [7:0]  wb_xram_wdata      ; // ram data input
 
wire          wb_xram_stb        ; // data-ram strobe
wire          wb_xram_cyc        ; // data-ram cycle
 
//----------------------------------------
 
core  u_core (
 
             . reset_n             (reset_n            ),
             . fastsim_mode        (1'b1               ),
             . xtal_clk            (xtal_clk           ),
             . clkout              (app_clk            ),
             . reset_out_n         (reset_out_n        ),
 
        // Reg Bus Interface Signal
             . ext_reg_cs          (reg_cs             ),
             . ext_reg_tid         (reg_id             ),
             . ext_reg_wr          (reg_wr             ),
             . ext_reg_addr        (reg_addr[12:0]     ),
             . ext_reg_wdata       (reg_wdata          ),
             . ext_reg_be          (reg_be             ),
 
            // Outputs
             . ext_reg_rdata       (reg_rdata          ),
             . ext_reg_ack         (reg_ack            ),
 
 
          // Line Side Interface TX Path
             .phy_tx_en            (phy_tx_en          ),
             .phy_txd              (phy_txd            ),
             .phy_tx_clk           (phy_tx_clk         ),
 
          // Line Side Interface RX Path
             .phy_rx_clk           (phy_rx_clk         ),
             .phy_rx_dv            (phy_rx_dv          ),
             .phy_rxd              (phy_rxd            ),
 
          //MDIO interface
             .MDC                  (MDC                ),
             .MDIO                 (MDIO               ),
 
 
       // UART Line Interface
             .si                   (si                 ),
             .so                   (so                 ),
 
 
             .spi_sck              (spi_sck            ),
             .spi_so               (spi_so             ),
             .spi_si               (spi_si             ),
             .spi_cs_n             (spi_cs_n           ),
 
         // External ROM interface
               .wb_xrom_adr        (wb_xrom_adr        ),
               .wb_xrom_ack        (wb_xrom_ack        ),
               .wb_xrom_err        (wb_xrom_err        ),
               .wb_xrom_wr         (wb_xrom_wr         ),
               .wb_xrom_rdata      (wb_xrom_rdata      ),
               .wb_xrom_wdata      (wb_xrom_wdata      ),
 
               .wb_xrom_stb        (wb_xrom_stb        ),
               .wb_xrom_cyc        (wb_xrom_cyc        ),
 
         // External RAM interface
               .wb_xram_adr        (wb_xram_adr        ),
               .wb_xram_ack        (wb_xram_ack        ),
               .wb_xram_err        (wb_xram_err        ),
               .wb_xram_wr         (wb_xram_wr         ),
               .wb_xram_rdata      (wb_xram_rdata      ),
               .wb_xram_wdata      (wb_xram_wdata      ),
 
               .wb_xram_stb        (wb_xram_stb        ),
               .wb_xram_cyc        (wb_xram_cyc        ),
 
             `ifdef INTERNAL_ROM
               .ea_in              (1'b1               ) // internal ROM
             `else
               .ea_in              (1'b0               ) // external ROM
             `endif
 
        );
 
 
  oc8051_xrom oc8051_xrom1
      (
             .rst                ( !reset_n         ),
             .clk                ( app_clk          ),
             .addr               ( wb_xrom_adr      ),
             .data               ( wb_xrom_rdata    ),
             .stb_i              ( wb_xrom_stb      ),
             .cyc_i              ( wb_xrom_cyc      ),
             .ack_o              ( wb_xrom_ack      )
      );
 
   defparam oc8051_xrom1.DELAY = 0;
 
 
//
// external data ram
//
oc8051_xram oc8051_xram1 (
          .clk               (app_clk       ),
          .rst               (!reset_n      ),
          .wr                (wb_xram_wr    ),
          .addr              (wb_xram_adr   ),
          .data_in           (wb_xram_wdata ),
          .data_out          (wb_xram_rdata ),
          .ack               (wb_xram_ack   ),
          .stb               (wb_xram_stb   )
      );
 
 
defparam oc8051_xram1.DELAY = 2;
 
 
 
 
tb_eth_top u_tb_eth (
 
               . REFCLK_50_MHz     (ref_clk_50         ), // 50 MHz Reference clock input
               . REFCLK_125_MHz    (ref_clk_125        ), // 125 MHz reference clock
               . transmit_enable   (1'b1               ), // transmit enable for testbench
 
          // Separate interfaces for each MII port type
 
          // Full MII, 4-bit interface
          // Transmit interface
               . MII_RXD           (phy_rxd[3:0]       ), // Receive data (output)
               . MII_RX_CLK        (phy_rx_clk         ), // Receive clock for MII (output)
               . MII_CRS           (phy_crs            ), // carrier sense (output)
               . MII_COL           (                   ), // Collision signal for MII (output)
               . MII_RX_DV         (phy_rx_dv          ), // Receive data valid for MII (output)
 
          // Receive interface
               . MII_TXD           (phy_txd[3:0]       ), // Transmit data (input)
               . MII_TX_EN         (phy_tx_en          ), // Tx enable (input)
               . MII_TX_CLK        (phy_tx_clk         ), // Transmit clock (output)
 
          // Reduced MII, 2-bit interface
          // Transmit interface
               . RMII_RXD          (                   ), // Receive data (output)
               . RMII_CRS_DV       (                   ), // carrier sense (output)
          // Receive interface
               . RMII_TXD          (                   ), // Transmit data (input)
               . RMII_TX_EN        (                   ), // Tx enable (input)
 
          // Serial MII interface
               . SMII_RXD          (                   ), // Receive data (output)
               . SMII_TXD          (                   ), // Transmit data (input)
               . SMII_SYNC         (                   ), // SMII SYNC signal (input)                
 
          // GMII, 8-bit/10-bit interface
          // Transmit interface
               . GMII_RXD          (                   ), // Receive data (output)
               . GMII_RX_CLK       (                   ), // Receive clock for MII (output)
               . GMII_CRS          (                   ), // carrier sense (output)
               . GMII_COL          (                   ), // Collision signal for MII (output)
               . GMII_RX_DV        (                   ), // Receive data valid for MII (output)
 
          // Receive interface
               . GMII_TXD          (                   ), // Transmit data (input)
               . GMII_TX_EN        (                   ), // Tx enable (input)
               . GMII_TX_CLK       (                   ), // Transmit clock (output)
               . GMII_GTX_CLK      (                   ), // Gigabit Tx clock (input), 125 MHz
 
              // MII management interface
               .MDIO               (MDC                ), // serial I/O data
               .MDC                (MDC                )  // clock
 
 
 
 
      );
 
 uart_agent tb_uart (
               . test_clk          (uart_clk_16x       ),
               . sin               (si                 ),
               . dsr_n             (                   ),
               . cts_n             (                   ),
               . dcd_n             (                   ),
 
               . sout              (so                 ),
               . dtr_n             (1'b0               ),
               . rts_n             (1'b0               ),
               . out1_n            (1'b0               ),
               . out2_n            (1'b0               )
       );
 
 
//----------------------- SPI Agents
 
m25p20 i_m25p20_0 (
               .c                  (spi_sck            ),
               .s                  (spi_cs_n[0]        ), // Include selection logic
               .w                  (1'b1               ), // Write protect is always disabled
               .hold               (1'b1               ), // Hold support not used
               .data_in            (spi_so             ),
               .data_out           (spi_si             )
             );
 
 
AT45DB321 i_AT45DB321_0 (
               .CSB                (spi_cs_n[1]        ),
               .SCK                (spi_sck            ),
               .SI                 (spi_so             ),
               .WPB                (1'b1               ),
               .RESETB             (1'b1               ),
               .RDY_BUSYB          (                   ),
               .SO                 (spi_si             )
      );
/***************
spi_agent_3120 spi_agent_3120_0 (
               .cs_b               (spi_cs_n[2]        ),
               .spi_din            (spi_si             ),
               .spi_dout           (spi_so             ),
               .spi_clk            (spi_sck            )
       );
 
spi_agent_3120 spi_agent_3120_1 (
               .cs_b               (spi_cs_n[3]        ),
               .spi_din            (spi_si             ),
               .spi_dout           (spi_so             ),
               .spi_clk            (spi_sck            )
       );
*****************/
 
tb_glbl  tb_glbl ();
 
 
initial begin
   if ( $test$plusargs("DUMP") ) begin
          $fsdbDumpfile("../dump/test_1.fsdb");
      $fsdbDumpvars;
      $fsdbDumpon;
   end
end
 
initial begin
 
  `TB_GLBL.init;
   #1000 wait(reset_out_n == 1);
 
   if ( $test$plusargs("gmac_test_1") )
       gmac_test1();
   else if ( $test$plusargs("uart_test_1") )
       uart_test1();
   else if ( $test$plusargs("spi_test_1") )
       spi_test1();
   else begin
     // 8051 Test Cases
     #80000000
     $display("time ",$time, "\n faulire: end of time\n \n");
   end
 
   `TB_GLBL.test_stats;
   `TB_GLBL.test_finish;
   #1000 $finish;
end
 
wire [7:0] p2_out = u_core.u_8051_core.p2_o;
wire [7:0] p3_out = u_core.u_8051_core.p3_o;
always @(p2_out or p3_out)
begin
  if((p2_out == 8'haa) &&      // fib.c
     (p3_out == 8'haa )) begin
      $display("################################");
      $display("time ",$time, " Passed");
      $display("################################");
      #100
      $finish;
  end else if(p2_out == 8'h55) begin     // fib.c
      $display("");
      $display("time ",$time," Error: %h", p3_out);
      $display("");
      #100
      $finish;
  end
end
 
 
 
 
`include "gmac_test1.v"
`include "uart_test1.v"
`include "spi_test1.v"
`include "tb_tasks.v"
`include "spi_tasks.v"
 
 
endmodule
`include "tb_glbl.v"

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[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the Turbo 8051 cores project ////`
5			`//// http://www.opencores.org/cores/turbo8051/ ////`
6			`//// ////`
7			`//// Description ////`
8			`//// Turbo 8051 definitions. ////`
9			`//// ////`
10			`//// To Do: ////`
11			`//// nothing ////`
12			`//// ////`
13			`//// Author(s): ////`
14			`//// - Dinesh Annayya, dinesha@opencores.org ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43
44			`timescale 1ns/1ps
45
46			`include "tb_defines.v"
47
48			`module tb_top;`
49
50			`//--------------------------------------------------------------`
51			`// Target ID Mapping`
52			`// 4'b0100 -- MAC core`
53			`// 4'b0011 -- UART`
54			`// 4'b0010 -- SPI core`
55			`// 4'b0001 -- External RAM`
56			`// 4'b0000 -- External ROM`
57			`//--------------------------------------------------------------`
58			`define ADDR_SPACE_MAC 4'b0100
59			`define ADDR_SPACE_UART 4'b0011
60			`define ADDR_SPACE_SPI 4'b0010
61			`define ADDR_SPACE_RAM 4'b0001
62			`define ADDR_SPACE_ROM 4'b0000
63
64			`reg reset_n;`
65			`reg reset;`
66			`reg xtal_clk;`
67			`reg ref_clk_125;`
68			`wire app_clk;`
69			`reg ref_clk_50;`
70			`reg uart_clk_16x;`
71
72
73			`parameter XTAL_CLK_PERIOD = 40; // 25Mhz`
74			`parameter APP_CLK_PERIOD = 10;`
75			`parameter REF_CLK_125_PERIOD = 8;`
76			`parameter REF_CLK_50_PERIOD = 20;`
77			`parameter UART_REF_CLK_PERIOD = 20;`
78
79			`reg[31:0] events_log;`
80
81			`initial`
82			`begin`
83			`reset_n = 1;`
84			`#100 reset_n = 0;`
85			`#100 reset_n = 1;`
86			`end`
87
88
89			`initial begin`
90			`xtal_clk = 1'b0;`
91			`forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;`
92			`end`
93
94
95			`//initial begin`
96			`// app_clk = 1'b0;`
97			`// forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;`
98			`//end`
99
100			`initial begin`
101			`ref_clk_125 = 1'b0;`
102			`forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;`
103			`end`
104
105			`initial begin`
106			`ref_clk_50 = 1'b0;`
107			`forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;`
108			`end`
109
110
111			`initial begin`
112			`uart_clk_16x = 1'b0;`
113			`forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;`
114			`end`
115
116
117			`wire [7:0] phy_txd ;`
118			`wire [7:0] phy_rxd ;`
119
120			`//---------------------------------`
121			`// Reg Bus Interface Signal`
122			`//---------------------------------`
123			`reg reg_cs ;`
124			`reg [3:0] reg_id ;`
125			`reg reg_wr ;`
126			`reg [12:0] reg_addr ;`
127			`reg [31:0] reg_wdata ;`
128			`reg [3:0] reg_be ;`
129
130			`// Outputs`
131			`wire [31:0] reg_rdata ;`
132			`wire reg_ack ;`
133
134
135
136			`wire spi_sck ;`
137			`wire spi_so ;`
138			`wire spi_si ;`
139			`wire [3:0] spi_cs_n ;`
140
141			`wire clkout ;`
142			`wire reset_out_n ;`
143
144			`//----------------------------------------`
145			`// 8051 core ROM related signals`
146			`//---------------------------------------`
147			`wire [15:0] wb_xrom_adr ; // instruction address`
148			`wire wb_xrom_ack ; // instruction acknowlage`
149			`wire wb_xrom_err ; // instruction error`
150			`wire wb_xrom_wr ; // instruction error`
151			`wire [31:0] wb_xrom_rdata ; // rom data input`
152			`wire [31:0] wb_xrom_wdata ; // rom data input`
153
154			`wire wb_xrom_stb ; // instruction strobe`
155			`wire wb_xrom_cyc ; // instruction cycle`
156
157
158			`//----------------------------------------`
159			`// 8051 core RAM related signals`
160			`//---------------------------------------`
161			`wire [15:0] wb_xram_adr ; // data-ram address`
162			`wire wb_xram_ack ; // data-ram acknowlage`
163			`wire wb_xram_err ; // data-ram error`
164			`wire wb_xram_wr ; // data-ram error`
165			`wire [7:0] wb_xram_rdata ; // ram data input`
166			`wire [7:0] wb_xram_wdata ; // ram data input`
167
168			`wire wb_xram_stb ; // data-ram strobe`
169			`wire wb_xram_cyc ; // data-ram cycle`
170
171			`//----------------------------------------`
172
173			`core u_core (`
174
175			`. reset_n (reset_n ),`
176			`. fastsim_mode (1'b1 ),`
177			`. xtal_clk (xtal_clk ),`
178			`. clkout (app_clk ),`
179			`. reset_out_n (reset_out_n ),`
180
181			`// Reg Bus Interface Signal`
182			`. ext_reg_cs (reg_cs ),`
183			`. ext_reg_tid (reg_id ),`
184			`. ext_reg_wr (reg_wr ),`
185			`. ext_reg_addr (reg_addr[12:0] ),`
186			`. ext_reg_wdata (reg_wdata ),`
187			`. ext_reg_be (reg_be ),`
188
189			`// Outputs`
190			`. ext_reg_rdata (reg_rdata ),`
191			`. ext_reg_ack (reg_ack ),`
192
193
194			`// Line Side Interface TX Path`
195			`.phy_tx_en (phy_tx_en ),`
196			`.phy_txd (phy_txd ),`
197			`.phy_tx_clk (phy_tx_clk ),`
198
199			`// Line Side Interface RX Path`
200			`.phy_rx_clk (phy_rx_clk ),`
201			`.phy_rx_dv (phy_rx_dv ),`
202			`.phy_rxd (phy_rxd ),`
203
204			`//MDIO interface`
205			`.MDC (MDC ),`
206			`.MDIO (MDIO ),`
207
208
209			`// UART Line Interface`
210			`.si (si ),`
211			`.so (so ),`
212
213
214			`.spi_sck (spi_sck ),`
215			`.spi_so (spi_so ),`
216			`.spi_si (spi_si ),`
217			`.spi_cs_n (spi_cs_n ),`
218
219			`// External ROM interface`
220			`.wb_xrom_adr (wb_xrom_adr ),`
221			`.wb_xrom_ack (wb_xrom_ack ),`
222			`.wb_xrom_err (wb_xrom_err ),`
223			`.wb_xrom_wr (wb_xrom_wr ),`
224			`.wb_xrom_rdata (wb_xrom_rdata ),`
225			`.wb_xrom_wdata (wb_xrom_wdata ),`
226
227			`.wb_xrom_stb (wb_xrom_stb ),`
228			`.wb_xrom_cyc (wb_xrom_cyc ),`
229
230			`// External RAM interface`
231			`.wb_xram_adr (wb_xram_adr ),`
232			`.wb_xram_ack (wb_xram_ack ),`
233			`.wb_xram_err (wb_xram_err ),`
234			`.wb_xram_wr (wb_xram_wr ),`
235			`.wb_xram_rdata (wb_xram_rdata ),`
236			`.wb_xram_wdata (wb_xram_wdata ),`
237
238			`.wb_xram_stb (wb_xram_stb ),`
239			`.wb_xram_cyc (wb_xram_cyc ),`
240
241			`ifdef INTERNAL_ROM
242			`.ea_in (1'b1 ) // internal ROM`
243			`else
244			`.ea_in (1'b0 ) // external ROM`
245			`endif
246
247			`);`
248
249
250			`oc8051_xrom oc8051_xrom1`
251			`(`
252			`.rst ( !reset_n ),`
253			`.clk ( app_clk ),`
254			`.addr ( wb_xrom_adr ),`
255			`.data ( wb_xrom_rdata ),`
256			`.stb_i ( wb_xrom_stb ),`
257			`.cyc_i ( wb_xrom_cyc ),`
258			`.ack_o ( wb_xrom_ack )`
259			`);`
260
261			`defparam oc8051_xrom1.DELAY = 0;`
262
263
264			`//`
265			`// external data ram`
266			`//`
267			`oc8051_xram oc8051_xram1 (`
268			`.clk (app_clk ),`
269			`.rst (!reset_n ),`
270			`.wr (wb_xram_wr ),`
271			`.addr (wb_xram_adr ),`
272			`.data_in (wb_xram_wdata ),`
273			`.data_out (wb_xram_rdata ),`
274			`.ack (wb_xram_ack ),`
275			`.stb (wb_xram_stb )`
276			`);`
277
278
279			`defparam oc8051_xram1.DELAY = 2;`
280
281
282
283
284			`tb_eth_top u_tb_eth (`
285
286			`. REFCLK_50_MHz (ref_clk_50 ), // 50 MHz Reference clock input`
287			`. REFCLK_125_MHz (ref_clk_125 ), // 125 MHz reference clock`
288			`. transmit_enable (1'b1 ), // transmit enable for testbench`
289
290			`// Separate interfaces for each MII port type`
291
292			`// Full MII, 4-bit interface`
293			`// Transmit interface`
294			`. MII_RXD (phy_rxd[3:0] ), // Receive data (output)`
295			`. MII_RX_CLK (phy_rx_clk ), // Receive clock for MII (output)`
296			`. MII_CRS (phy_crs ), // carrier sense (output)`
297			`. MII_COL ( ), // Collision signal for MII (output)`
298			`. MII_RX_DV (phy_rx_dv ), // Receive data valid for MII (output)`
299
300			`// Receive interface`
301			`. MII_TXD (phy_txd[3:0] ), // Transmit data (input)`
302			`. MII_TX_EN (phy_tx_en ), // Tx enable (input)`
303			`. MII_TX_CLK (phy_tx_clk ), // Transmit clock (output)`
304
305			`// Reduced MII, 2-bit interface`
306			`// Transmit interface`
307			`. RMII_RXD ( ), // Receive data (output)`
308			`. RMII_CRS_DV ( ), // carrier sense (output)`
309			`// Receive interface`
310			`. RMII_TXD ( ), // Transmit data (input)`
311			`. RMII_TX_EN ( ), // Tx enable (input)`
312
313			`// Serial MII interface`
314			`. SMII_RXD ( ), // Receive data (output)`
315			`. SMII_TXD ( ), // Transmit data (input)`
316			`. SMII_SYNC ( ), // SMII SYNC signal (input)`
317
318			`// GMII, 8-bit/10-bit interface`
319			`// Transmit interface`
320			`. GMII_RXD ( ), // Receive data (output)`
321			`. GMII_RX_CLK ( ), // Receive clock for MII (output)`
322			`. GMII_CRS ( ), // carrier sense (output)`
323			`. GMII_COL ( ), // Collision signal for MII (output)`
324			`. GMII_RX_DV ( ), // Receive data valid for MII (output)`
325
326			`// Receive interface`
327			`. GMII_TXD ( ), // Transmit data (input)`
328			`. GMII_TX_EN ( ), // Tx enable (input)`
329			`. GMII_TX_CLK ( ), // Transmit clock (output)`
330			`. GMII_GTX_CLK ( ), // Gigabit Tx clock (input), 125 MHz`
331
332			`// MII management interface`
333			`.MDIO (MDC ), // serial I/O data`
334			`.MDC (MDC ) // clock`
335
336
337
338
339			`);`
340
341			`uart_agent tb_uart (`
342			`. test_clk (uart_clk_16x ),`
343			`. sin (si ),`
344			`. dsr_n ( ),`
345			`. cts_n ( ),`
346			`. dcd_n ( ),`
347
348			`. sout (so ),`
349			`. dtr_n (1'b0 ),`
350			`. rts_n (1'b0 ),`
351			`. out1_n (1'b0 ),`
352			`. out2_n (1'b0 )`
353			`);`
354
355
356			`//----------------------- SPI Agents`
357
358			`m25p20 i_m25p20_0 (`
359			`.c (spi_sck ),`
360			`.s (spi_cs_n[0] ), // Include selection logic`
361			`.w (1'b1 ), // Write protect is always disabled`
362			`.hold (1'b1 ), // Hold support not used`
363			`.data_in (spi_so ),`
364			`.data_out (spi_si )`
365			`);`
366
367
368			`AT45DB321 i_AT45DB321_0 (`
369			`.CSB (spi_cs_n[1] ),`
370			`.SCK (spi_sck ),`
371			`.SI (spi_so ),`
372			`.WPB (1'b1 ),`
373			`.RESETB (1'b1 ),`
374			`.RDY_BUSYB ( ),`
375			`.SO (spi_si )`
376			`);`
377			`/***************`
378			`spi_agent_3120 spi_agent_3120_0 (`
379			`.cs_b (spi_cs_n[2] ),`
380			`.spi_din (spi_si ),`
381			`.spi_dout (spi_so ),`
382			`.spi_clk (spi_sck )`
383			`);`
384
385			`spi_agent_3120 spi_agent_3120_1 (`
386			`.cs_b (spi_cs_n[3] ),`
387			`.spi_din (spi_si ),`
388			`.spi_dout (spi_so ),`
389			`.spi_clk (spi_sck )`
390			`);`
391			`*****************/`
392
393			`tb_glbl tb_glbl ();`
394
395
396			`initial begin`
397			`if ( $test$plusargs("DUMP") ) begin`
398			`$fsdbDumpfile("../dump/test_1.fsdb");`
399			`$fsdbDumpvars;`
400			`$fsdbDumpon;`
401			`end`
402			`end`
403
404			`initial begin`
405
406			`TB_GLBL.init;
407			`#1000 wait(reset_out_n == 1);`
408
409			`if ( $test$plusargs("gmac_test_1") )`
410			`gmac_test1();`
411			`else if ( $test$plusargs("uart_test_1") )`
412			`uart_test1();`
413			`else if ( $test$plusargs("spi_test_1") )`
414			`spi_test1();`
415			`else begin`
416			`// 8051 Test Cases`
417			`#80000000`
418			`$display("time ",$time, "\n faulire: end of time\n \n");`
419			`end`
420
421			`TB_GLBL.test_stats;
422			`TB_GLBL.test_finish;
423			`#1000 $finish;`
424			`end`
425
426			`wire [7:0] p2_out = u_core.u_8051_core.p2_o;`
427			`wire [7:0] p3_out = u_core.u_8051_core.p3_o;`
428			`always @(p2_out or p3_out)`
429			`begin`
430			`if((p2_out == 8'haa) && // fib.c`
431			`(p3_out == 8'haa )) begin`
432			`$display("################################");`
433			`$display("time ",$time, " Passed");`
434			`$display("################################");`
435			`#100`
436			`$finish;`
437			`end else if(p2_out == 8'h55) begin // fib.c`
438			`$display("");`
439			`$display("time ",$time," Error: %h", p3_out);`
440			`$display("");`
441			`#100`
442			`$finish;`
443			`end`
444			`end`
445
446
447
448
449			`include "gmac_test1.v"
450			`include "uart_test1.v"
451			`include "spi_test1.v"
452			`include "tb_tasks.v"
453			`include "spi_tasks.v"
454
455
456			`endmodule`
457			`include "tb_glbl.v"