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[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Blame information for rev 56

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1 15 dinesha
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////                                                              ////
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////  This file is part of the Turbo 8051 cores project           ////
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////  http://www.opencores.org/cores/turbo8051/                   ////
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////                                                              ////
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////  Description                                                 ////
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////  Turbo 8051 definitions.                                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43
 
44
`timescale  1ns/1ps
45
 
46
`include "tb_defines.v"
47
 
48
module tb_top;
49
 
50
 
51
reg    reset_n;
52
reg    reset;
53
reg    xtal_clk;
54
reg    ref_clk_125;
55
wire   app_clk;
56
reg    ref_clk_50;
57
reg    uart_clk_16x;
58
 
59
 
60
parameter XTAL_CLK_PERIOD = 40; // 25Mhz
61
parameter APP_CLK_PERIOD = 10;
62
parameter REF_CLK_125_PERIOD = 8;
63
parameter REF_CLK_50_PERIOD = 20;
64
parameter UART_REF_CLK_PERIOD = 20;
65
 
66
reg[31:0] events_log;
67
 
68
initial
69
begin
70
        reset_n = 1;
71
   #100 reset_n = 0;
72
   #100 reset_n = 1;
73
end
74
 
75
 
76
initial begin
77
  xtal_clk = 1'b0;
78
  forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;
79
end
80
 
81
 
82
//initial begin
83
//  app_clk = 1'b0;
84
//  forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;
85
//end
86
 
87
initial begin
88
  ref_clk_125 = 1'b0;
89
  forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;
90
end
91
 
92
initial begin
93
  ref_clk_50 = 1'b0;
94
  forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;
95
end
96
 
97
 
98
initial begin
99
  uart_clk_16x = 1'b0;
100
  forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;
101
end
102
 
103
 
104
wire [7:0]   phy_txd            ;
105
wire [7:0]   phy_rxd            ;
106
 
107
//---------------------------------
108
// Reg Bus Interface Signal
109
//---------------------------------
110
reg                reg_cs     ;
111
reg [3:0]          reg_id     ;
112
reg                reg_wr         ;
113 56 dinesha
reg  [14:0]        reg_addr       ;
114 15 dinesha
reg  [31:0]        reg_wdata      ;
115
reg  [3:0]         reg_be         ;
116
 
117
// Outputs
118
wire  [31:0]        reg_rdata      ;
119
wire                reg_ack        ;
120
 
121 28 dinesha
reg                 master_mode   ;
122
reg                 ea_in   ;   // 1--> Internal Memory
123 15 dinesha
 
124
 
125
wire         spi_sck            ;
126
wire         spi_so             ;
127
wire         spi_si             ;
128
wire [3:0]   spi_cs_n           ;
129
 
130
wire         clkout             ;
131
wire         reset_out_n        ;
132
 
133
//----------------------------------------
134
// 8051 core ROM related signals
135
//---------------------------------------
136
wire  [15:0]   wb_xrom_adr       ; // instruction address
137
wire           wb_xrom_ack       ; // instruction acknowlage
138
wire           wb_xrom_err       ; // instruction error
139
wire           wb_xrom_wr        ; // instruction error
140
wire    [31:0] wb_xrom_rdata     ; // rom data input
141
wire   [31:0]  wb_xrom_wdata     ; // rom data input
142
 
143
wire           wb_xrom_stb       ; // instruction strobe
144
wire           wb_xrom_cyc       ; // instruction cycle
145
 
146
 
147
//----------------------------------------
148
// 8051 core RAM related signals
149
//---------------------------------------
150
wire   [15:0] wb_xram_adr        ; // data-ram address
151
wire          wb_xram_ack        ; // data-ram acknowlage
152
wire          wb_xram_err        ; // data-ram error
153
wire          wb_xram_wr         ; // data-ram error
154 50 dinesha
wire   [3:0]  wb_xram_be         ; // data-ram error
155
wire   [31:0] wb_xram_rdata      ; // ram data input
156
wire   [31:0] wb_xram_wdata      ; // ram data input
157 15 dinesha
 
158
wire          wb_xram_stb        ; // data-ram strobe
159
wire          wb_xram_cyc        ; // data-ram cycle
160
 
161
//----------------------------------------
162
 
163 33 dinesha
turbo8051  u_core (
164 15 dinesha
 
165
             . reset_n             (reset_n            ),
166
             . fastsim_mode        (1'b1               ),
167 28 dinesha
             . mastermode          (master_mode        ),
168 27 dinesha
 
169 15 dinesha
             . xtal_clk            (xtal_clk           ),
170
             . clkout              (app_clk            ),
171
             . reset_out_n         (reset_out_n        ),
172
 
173
        // Reg Bus Interface Signal
174
             . ext_reg_cs          (reg_cs             ),
175
             . ext_reg_tid         (reg_id             ),
176
             . ext_reg_wr          (reg_wr             ),
177 56 dinesha
             . ext_reg_addr        (reg_addr[14:0]     ),
178 15 dinesha
             . ext_reg_wdata       (reg_wdata          ),
179
             . ext_reg_be          (reg_be             ),
180
 
181
            // Outputs
182
             . ext_reg_rdata       (reg_rdata          ),
183
             . ext_reg_ack         (reg_ack            ),
184
 
185
 
186
          // Line Side Interface TX Path
187
             .phy_tx_en            (phy_tx_en          ),
188
             .phy_txd              (phy_txd            ),
189
             .phy_tx_clk           (phy_tx_clk         ),
190
 
191
          // Line Side Interface RX Path
192
             .phy_rx_clk           (phy_rx_clk         ),
193
             .phy_rx_dv            (phy_rx_dv          ),
194
             .phy_rxd              (phy_rxd            ),
195
 
196
          //MDIO interface
197
             .MDC                  (MDC                ),
198
             .MDIO                 (MDIO               ),
199
 
200
 
201
       // UART Line Interface
202
             .si                   (si                 ),
203
             .so                   (so                 ),
204
 
205
 
206
             .spi_sck              (spi_sck            ),
207
             .spi_so               (spi_so             ),
208
             .spi_si               (spi_si             ),
209
             .spi_cs_n             (spi_cs_n           ),
210
 
211
         // External ROM interface
212
               .wb_xrom_adr        (wb_xrom_adr        ),
213
               .wb_xrom_ack        (wb_xrom_ack        ),
214
               .wb_xrom_err        (wb_xrom_err        ),
215
               .wb_xrom_wr         (wb_xrom_wr         ),
216
               .wb_xrom_rdata      (wb_xrom_rdata      ),
217
               .wb_xrom_wdata      (wb_xrom_wdata      ),
218
 
219
               .wb_xrom_stb        (wb_xrom_stb        ),
220
               .wb_xrom_cyc        (wb_xrom_cyc        ),
221
 
222
         // External RAM interface
223
               .wb_xram_adr        (wb_xram_adr        ),
224
               .wb_xram_ack        (wb_xram_ack        ),
225
               .wb_xram_err        (wb_xram_err        ),
226
               .wb_xram_wr         (wb_xram_wr         ),
227 50 dinesha
               .wb_xram_be         (wb_xram_be         ),
228 15 dinesha
               .wb_xram_rdata      (wb_xram_rdata      ),
229
               .wb_xram_wdata      (wb_xram_wdata      ),
230
 
231
               .wb_xram_stb        (wb_xram_stb        ),
232
               .wb_xram_cyc        (wb_xram_cyc        ),
233
 
234 28 dinesha
               .ea_in              (ea_in               ) // internal ROM
235 15 dinesha
 
236
        );
237
 
238
 
239
  oc8051_xrom oc8051_xrom1
240
      (
241
             .rst                ( !reset_n         ),
242
             .clk                ( app_clk          ),
243
             .addr               ( wb_xrom_adr      ),
244
             .data               ( wb_xrom_rdata    ),
245
             .stb_i              ( wb_xrom_stb      ),
246
             .cyc_i              ( wb_xrom_cyc      ),
247
             .ack_o              ( wb_xrom_ack      )
248
      );
249
 
250
   defparam oc8051_xrom1.DELAY = 0;
251
 
252
 
253
//
254
// external data ram
255
//
256
oc8051_xram oc8051_xram1 (
257
          .clk               (app_clk       ),
258
          .rst               (!reset_n      ),
259
          .wr                (wb_xram_wr    ),
260 50 dinesha
          .be                (wb_xram_be    ),
261 15 dinesha
          .addr              (wb_xram_adr   ),
262
          .data_in           (wb_xram_wdata ),
263
          .data_out          (wb_xram_rdata ),
264
          .ack               (wb_xram_ack   ),
265
          .stb               (wb_xram_stb   )
266
      );
267
 
268
 
269
defparam oc8051_xram1.DELAY = 2;
270
 
271
 
272
 
273
 
274
tb_eth_top u_tb_eth (
275
 
276
               . REFCLK_50_MHz     (ref_clk_50         ), // 50 MHz Reference clock input
277
               . REFCLK_125_MHz    (ref_clk_125        ), // 125 MHz reference clock
278
               . transmit_enable   (1'b1               ), // transmit enable for testbench
279
 
280
          // Separate interfaces for each MII port type
281
 
282
          // Full MII, 4-bit interface
283
          // Transmit interface
284
               . MII_RXD           (phy_rxd[3:0]       ), // Receive data (output)
285
               . MII_RX_CLK        (phy_rx_clk         ), // Receive clock for MII (output)
286
               . MII_CRS           (phy_crs            ), // carrier sense (output)
287
               . MII_COL           (                   ), // Collision signal for MII (output)
288
               . MII_RX_DV         (phy_rx_dv          ), // Receive data valid for MII (output)
289
 
290
          // Receive interface
291
               . MII_TXD           (phy_txd[3:0]       ), // Transmit data (input)
292
               . MII_TX_EN         (phy_tx_en          ), // Tx enable (input)
293
               . MII_TX_CLK        (phy_tx_clk         ), // Transmit clock (output)
294
 
295
          // Reduced MII, 2-bit interface
296
          // Transmit interface
297
               . RMII_RXD          (                   ), // Receive data (output)
298
               . RMII_CRS_DV       (                   ), // carrier sense (output)
299
          // Receive interface
300
               . RMII_TXD          (                   ), // Transmit data (input)
301
               . RMII_TX_EN        (                   ), // Tx enable (input)
302
 
303
          // Serial MII interface
304
               . SMII_RXD          (                   ), // Receive data (output)
305
               . SMII_TXD          (                   ), // Transmit data (input)
306
               . SMII_SYNC         (                   ), // SMII SYNC signal (input)                
307
 
308
          // GMII, 8-bit/10-bit interface
309
          // Transmit interface
310
               . GMII_RXD          (                   ), // Receive data (output)
311
               . GMII_RX_CLK       (                   ), // Receive clock for MII (output)
312
               . GMII_CRS          (                   ), // carrier sense (output)
313
               . GMII_COL          (                   ), // Collision signal for MII (output)
314
               . GMII_RX_DV        (                   ), // Receive data valid for MII (output)
315
 
316
          // Receive interface
317
               . GMII_TXD          (                   ), // Transmit data (input)
318
               . GMII_TX_EN        (                   ), // Tx enable (input)
319
               . GMII_TX_CLK       (                   ), // Transmit clock (output)
320
               . GMII_GTX_CLK      (                   ), // Gigabit Tx clock (input), 125 MHz
321
 
322
              // MII management interface
323
               .MDIO               (MDC                ), // serial I/O data
324
               .MDC                (MDC                )  // clock
325
 
326
 
327
 
328
 
329
      );
330
 
331
 uart_agent tb_uart (
332
               . test_clk          (uart_clk_16x       ),
333
               . sin               (si                 ),
334
               . dsr_n             (                   ),
335
               . cts_n             (                   ),
336
               . dcd_n             (                   ),
337
 
338
               . sout              (so                 ),
339
               . dtr_n             (1'b0               ),
340
               . rts_n             (1'b0               ),
341
               . out1_n            (1'b0               ),
342
               . out2_n            (1'b0               )
343
       );
344
 
345
 
346
//----------------------- SPI Agents
347
 
348
m25p20 i_m25p20_0 (
349
               .c                  (spi_sck            ),
350
               .s                  (spi_cs_n[0]        ), // Include selection logic
351
               .w                  (1'b1               ), // Write protect is always disabled
352
               .hold               (1'b1               ), // Hold support not used
353
               .data_in            (spi_so             ),
354
               .data_out           (spi_si             )
355
             );
356
 
357
 
358
AT45DB321 i_AT45DB321_0 (
359
               .CSB                (spi_cs_n[1]        ),
360
               .SCK                (spi_sck            ),
361
               .SI                 (spi_so             ),
362
               .WPB                (1'b1               ),
363
               .RESETB             (1'b1               ),
364
               .RDY_BUSYB          (                   ),
365
               .SO                 (spi_si             )
366
      );
367
/***************
368
spi_agent_3120 spi_agent_3120_0 (
369
               .cs_b               (spi_cs_n[2]        ),
370
               .spi_din            (spi_si             ),
371
               .spi_dout           (spi_so             ),
372
               .spi_clk            (spi_sck            )
373
       );
374
 
375
spi_agent_3120 spi_agent_3120_1 (
376
               .cs_b               (spi_cs_n[3]        ),
377
               .spi_din            (spi_si             ),
378
               .spi_dout           (spi_so             ),
379
               .spi_clk            (spi_sck            )
380
       );
381
*****************/
382
 
383
tb_glbl  tb_glbl ();
384
 
385
 
386
initial begin
387
   if ( $test$plusargs("DUMP") ) begin
388
          $fsdbDumpfile("../dump/test_1.fsdb");
389
      $fsdbDumpvars;
390
      $fsdbDumpon;
391
   end
392
end
393
 
394
initial begin
395
 
396 28 dinesha
   if ( $test$plusargs("INTERNAL_ROM") )  begin
397
      ea_in       = 1;
398
      master_mode = 1;
399
   end else if ( $test$plusargs("EXTERNAL_ROM") ) begin
400
      ea_in       = 0;
401
      master_mode = 1;
402
   end else begin
403
      ea_in       = 0;
404
      master_mode = 0;
405
   end
406
 
407 15 dinesha
  `TB_GLBL.init;
408 53 dinesha
 
409
   // test case, which has control before reset
410
   if ( $test$plusargs("gmac_test_2") )
411
       gmac_test2();
412
 
413 15 dinesha
   #1000 wait(reset_out_n == 1);
414
 
415 53 dinesha
   // test case, which has control after reset
416 15 dinesha
   if ( $test$plusargs("gmac_test_1") )
417
       gmac_test1();
418
   else if ( $test$plusargs("uart_test_1") )
419
       uart_test1();
420
   else if ( $test$plusargs("spi_test_1") )
421
       spi_test1();
422 56 dinesha
   else if ( !$test$plusargs("gmac_test_2") ) begin
423 15 dinesha
     // 8051 Test Cases
424
     #80000000
425
     $display("time ",$time, "\n faulire: end of time\n \n");
426
   end
427
 
428
   `TB_GLBL.test_stats;
429
   `TB_GLBL.test_finish;
430
   #1000 $finish;
431
end
432
 
433
wire [7:0] p2_out = u_core.u_8051_core.p2_o;
434
wire [7:0] p3_out = u_core.u_8051_core.p3_o;
435
always @(p2_out or p3_out)
436
begin
437
  if((p2_out == 8'haa) &&      // fib.c
438
     (p3_out == 8'haa )) begin
439
      $display("################################");
440
      $display("time ",$time, " Passed");
441
      $display("################################");
442
      #100
443
      $finish;
444
  end else if(p2_out == 8'h55) begin     // fib.c
445
      $display("");
446
      $display("time ",$time," Error: %h", p3_out);
447
      $display("");
448
      #100
449
      $finish;
450
  end
451
end
452
 
453
 
454
 
455
 
456
`include "gmac_test1.v"
457 52 dinesha
`include "gmac_test2.v"
458 15 dinesha
`include "uart_test1.v"
459
`include "spi_test1.v"
460
`include "tb_tasks.v"
461
`include "spi_tasks.v"
462
 
463
 
464
endmodule
465
`include "tb_glbl.v"

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