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15 |
dinesha |
task gmac_test1;
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50 |
dinesha |
reg [31:0] read_data;
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reg [3:0] desc_ptr;
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reg [9:0] desc_rx_qbase;
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reg [9:0] desc_tx_qbase;
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reg [7:0] iFrmCnt;
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15 |
dinesha |
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74 |
dinesha |
begin
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50 |
dinesha |
//--------------------------
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// Data Memory MAP
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//-------------------------
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| 12 |
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// 0x0000 to 0x0FFF - 4K - Processor Data Memory
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| 13 |
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// 0x1000 to 0x1FFF - 4K - Gmac Rx Data Memory
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// 0x2000 to 0x2FFF - 4K - Reserved for Rx
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| 15 |
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// 0x3000 to 0x3FFF - 4K - Gmac Tx Data Memory
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| 16 |
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// 0x4000 to 0x4FFF - 4K - Reserved for Tx
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| 17 |
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// 0x7000 to 0x703F - 64 - Rx Descriptor
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// 0x7040 to 0x707F - 64 - Tx Descripto
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15 |
dinesha |
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events_log = $fopen("../test_log_files/test1_events.log");
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tb_top.u_tb_eth.event_file = events_log;
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50 |
dinesha |
desc_ptr = 0;
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desc_rx_qbase = 10'h1C0;
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desc_tx_qbase = 10'h1C1;
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iFrmCnt = 0;
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15 |
dinesha |
tb_top.u_tb_eth.init_port(3'b1, 3'b1, 1'b1, 0);
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| 28 |
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50 |
dinesha |
tb_top.cpu_write('h1,8'h0,{4'h1,4'h1,8'h45,8'h01}); // tx/rx-control
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15 |
dinesha |
tb_top.cpu_write('h1,8'h8,{16'h0,8'd22,8'd22}); // Tx/Rx IFG
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50 |
dinesha |
tb_top.cpu_write('h1,8'h24,{desc_tx_qbase,desc_ptr,2'b00,
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desc_rx_qbase,desc_ptr,2'b00}); // Tx/Rx Descriptor
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15 |
dinesha |
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tb_top.u_tb_eth.set_flow_type(0);//L2 unicast
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tb_top.u_tb_eth.set_L2_frame_size(1, 64, 84, 1); //, 1, 17, 33, 49, 64
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tb_top.u_tb_eth.set_payload_type(2, 5000,0); //make sure frame size is honored
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41 |
dinesha |
tb_top.u_tb_eth.set_L2_protocol(0); // Untagged frame
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| 38 |
15 |
dinesha |
tb_top.u_tb_eth.set_L2_source_address(0, 48'h12_34_56_78_9a_bc, 0,0);
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tb_top.u_tb_eth.set_L2_destination_address(0, 48'h16_22_33_44_55_66, 0,0);
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41 |
dinesha |
tb_top.u_tb_eth.set_L3_protocol(4); // IPV4
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| 41 |
15 |
dinesha |
tb_top.u_tb_eth.set_crc_option(0,0);
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fork
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tb_top.u_tb_eth.transmit_packet_sequence(10, 96, 1, 500000);
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begin
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tb_top.u_tb_eth.wait_for_event(3, 0);
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tb_top.u_tb_eth.wait_for_event(3, 0);
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end
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50 |
dinesha |
begin
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while(iFrmCnt != 10) begin
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tb_top.cpu_read('h1,8'h30,read_data); // Tx/Rx Counter
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if(read_data[3:0] != 0) begin // Check the Rx Q Counter
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// Read the Receive Descriptor
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56 |
dinesha |
tb_top.cpu_read('h4,{desc_rx_qbase,desc_ptr,2'b0},read_data);
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50 |
dinesha |
// Write the Tx Descriptor
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| 56 |
56 |
dinesha |
tb_top.cpu_write('h4,{desc_tx_qbase,desc_ptr,2'b0},read_data);
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50 |
dinesha |
desc_ptr = desc_ptr+1;
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iFrmCnt = iFrmCnt+1;
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end
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#1000;
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end
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end
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15 |
dinesha |
join
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#100000;
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`TB_AGENTS_GMAC.full_mii.status; // test status
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// Check the Transmitted & Received Frame cnt
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if(`TB_AGENTS_GMAC.full_mii.transmitted_packet_count != `TB_AGENTS_GMAC.full_mii.receive_packet_count)
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`TB_GLBL.test_err;
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// Check the Transmitted & Received Byte cnt
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if(`TB_AGENTS_GMAC.full_mii.transmitted_packet_byte_count != `TB_AGENTS_GMAC.full_mii.receive_packet_byte_count)
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`TB_GLBL.test_err;
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if(`TB_AGENTS_GMAC.full_mii.receive_crc_err_count)
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`TB_GLBL.test_err;
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| 80 |
74 |
dinesha |
end
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| 81 |
15 |
dinesha |
endtask
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