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[/] [turbo8051/] [trunk/] [verif/] [testcase/] [uart_test1.v] - Blame information for rev 28

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Line No. Rev Author Line
1 15 dinesha
task uart_test1;
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reg [1:0] data_bit        = 2'b11;
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reg       stop_bits       = 0; // 0: 1 stop bit; 1: 2 stop bit;
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reg       stick_parity    = 0; // 1: force even parity
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reg       parity_en       = 1; // parity enable
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reg       even_odd_parity = 1; // 0: odd parity; 1: even parity
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reg [7:0] data;
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reg [15:0] divisor        = 3;   // divided by n * 16
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reg [15:0] timeout        = 500;// wait time limit
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reg [15:0] rx_nu;
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reg [15:0] tx_nu;
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reg [7:0] write_data [0:39];
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reg     fifo_enable       = 0;   // fifo mode disable
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integer i,j;
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tb_uart.uart_init;
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tb_top.cpu_write('h3,8'h0,{27'h0,2'b10,1'b1,1'b1,1'b1});
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for (i=0; i<40; i=i+1)
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        write_data[i] = $random;
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  tb_top.tb_uart.control_setup (data_bit, stop_bits, parity_en, even_odd_parity, stick_parity, timeout, divisor, fifo_enable);
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   fork
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   begin
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      for (i=0; i<40; i=i+1)
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      begin
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        $display ("\n... Writing char %d ...", write_data[i]);
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         tb_top.tb_uart.write_char (write_data[i]);
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      end
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   end
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   begin
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      for (j=0; j<40; j=j+1)
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      begin
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        tb_top.tb_uart.read_char_chk(write_data[j]);
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      end
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   end
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   join
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   #100
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   tb_top.tb_uart.report_status(rx_nu, tx_nu);
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endtask

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