1 |
63 |
dinesha |
task webserver;
|
2 |
|
|
reg [31:0] read_data;
|
3 |
|
|
reg [3:0] desc_ptr;
|
4 |
|
|
reg [9:0] desc_rx_qbase;
|
5 |
|
|
reg [9:0] desc_tx_qbase;
|
6 |
|
|
reg [7:0] iFrmCnt;
|
7 |
|
|
|
8 |
|
|
reg [31:0] outfile;
|
9 |
|
|
|
10 |
|
|
//--------------------------
|
11 |
|
|
// Data Memory MAP
|
12 |
|
|
//-------------------------
|
13 |
|
|
// 0x0000 to 0x0FFF - 4K - Processor Data Memory
|
14 |
|
|
// 0x1000 to 0x1FFF - 4K - Gmac Rx Data Memory
|
15 |
|
|
// 0x2000 to 0x2FFF - 4K - Reserved for Rx
|
16 |
|
|
// 0x3000 to 0x3FFF - 4K - Gmac Tx Data Memory
|
17 |
|
|
// 0x4000 to 0x4FFF - 4K - Reserved for Tx
|
18 |
|
|
// 0x7000 to 0x703F - 64 - Rx Descriptor
|
19 |
|
|
// 0x7040 to 0x707F - 64 - Tx Descripto
|
20 |
|
|
|
21 |
|
|
events_log = $fopen("../test_log_files/test1_events.log");
|
22 |
|
|
tb_top.u_tb_eth.event_file = events_log;
|
23 |
|
|
|
24 |
|
|
outfile = $fopen("../test_log_files/test1_outfile.log");
|
25 |
|
|
tb_top.u_tb_eth.outfile = outfile;
|
26 |
|
|
$system("cp ../testcase/dat/webserver.dat ./dat/oc8051_xrom.in");
|
27 |
|
|
// Enable the RISC booting + Internal ROM Mode
|
28 |
|
|
tb_top.ea_in = 1;
|
29 |
|
|
tb_top.master_mode = 1;
|
30 |
|
|
|
31 |
|
|
#1000 wait(reset_out_n == 1);
|
32 |
|
|
|
33 |
|
|
|
34 |
|
|
desc_ptr = 0;
|
35 |
|
|
desc_rx_qbase = 10'h1C0; // MSB 10 Bits of 0x7000
|
36 |
|
|
desc_tx_qbase = 10'h1C1; // MSB 10 Bits of 0x7040
|
37 |
|
|
iFrmCnt = 0;
|
38 |
|
|
tb_top.u_tb_eth.init_port(3'b1, 3'b1, 1'b1, 0);
|
39 |
|
|
|
40 |
|
|
tb_top.cpu_write('h1,8'h0,{4'h1,4'h1,8'h45,8'h19}); // tx/rx-control
|
41 |
|
|
tb_top.cpu_write('h1,8'h8,{16'h0,8'd22,8'd22}); // Tx/Rx IFG
|
42 |
|
|
tb_top.cpu_write('h1,8'h24,{desc_tx_qbase,desc_ptr,2'b00,
|
43 |
|
|
desc_rx_qbase,desc_ptr,2'b00}); // Tx/Rx Descriptor
|
44 |
|
|
|
45 |
|
|
tb_top.u_tb_eth.set_L2_custom_header(42,336'h01_02_03_04_05_06_11_12_13_14_15_16_08_06_00_01_11_22_06_04_00_01_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_0A_01_01_01);//L2 unicast
|
46 |
|
|
tb_top.u_tb_eth.set_flow_type(0);//L2 unicast
|
47 |
|
|
tb_top.u_tb_eth.set_L2_frame_size(1, 64, 84, 1); //, 1, 17, 33, 49, 64
|
48 |
|
|
tb_top.u_tb_eth.set_payload_type(2, 5000,0); //make sure frame size is honored
|
49 |
|
|
//tb_top.u_tb_eth.set_L2_protocol(0); // Untagged frame
|
50 |
|
|
//tb_top.u_tb_eth.set_L2_source_address(0, 48'h12_34_56_78_9a_bc, 0,0);
|
51 |
|
|
//tb_top.u_tb_eth.set_L2_destination_address(0, 48'h16_22_33_44_55_66, 0,0);
|
52 |
|
|
tb_top.u_tb_eth.set_L3_protocol(4); // IPV4
|
53 |
|
|
tb_top.u_tb_eth.set_crc_option(0,0);
|
54 |
|
|
|
55 |
|
|
fork
|
56 |
|
|
begin
|
57 |
|
|
// Send ARP Packet
|
58 |
|
|
tb_top.u_tb_eth.set_L2_custom_header(42,336'h01_02_03_04_05_06_11_12_13_14_15_16_08_06_00_01_11_22_06_04_00_01_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_0A_01_01_01);//L2 unicast
|
59 |
|
|
tb_top.u_tb_eth.print_packet_parameters();
|
60 |
|
|
tb_top.u_tb_eth.transmit_packet_sequence(1, 96, 1, 500000);
|
61 |
|
|
#1000; // wait for IFG
|
62 |
|
|
// Send IP Packet + ICMP Request
|
63 |
|
|
tb_top.u_tb_eth.set_L2_custom_header(42,336'h01_02_03_04_05_06_11_12_13_14_15_16_08_00_00_01_11_22_06_04_00_01_00_01_00_00_00_00_00_00_0A_01_01_01_08_00_00_00_0A_01_01_01);//L2 unicast
|
64 |
|
|
tb_top.u_tb_eth.print_packet_parameters();
|
65 |
|
|
tb_top.u_tb_eth.transmit_packet_sequence(1, 96, 1, 500000);
|
66 |
|
|
#1000; // wait for IFG
|
67 |
|
|
|
68 |
|
|
// Packet No: 3
|
69 |
|
|
// Send IP4 + TCP + Flag with SYNC
|
70 |
|
|
tb_top.u_tb_eth.set_flow_type(5);//L4
|
71 |
|
|
tb_top.u_tb_eth.set_L2_protocol(0); // Ethernet without VLAN
|
72 |
|
|
tb_top.u_tb_eth.set_L3_protocol(4); // IPV4
|
73 |
|
|
tb_top.u_tb_eth.set_L4_protocol(0); // TCP
|
74 |
|
|
tb_top.u_tb_eth.set_IP_header(32'h0a010102,32'h0a010101,0,1,0,0,0,6);
|
75 |
|
|
tb_top.u_tb_eth.set_TCP_header_fields(0,8'h2,0,0);
|
76 |
|
|
tb_top.u_tb_eth.set_TCP_port_numbers(16'h1000,16'h50); // decimal: 80. Hex:50
|
77 |
|
|
tb_top.u_tb_eth.print_packet_parameters();
|
78 |
|
|
tb_top.u_tb_eth.transmit_packet_sequence(1, 96, 1, 500000);
|
79 |
|
|
#1000; // wait for IFG
|
80 |
|
|
|
81 |
|
|
// Packet No: 4
|
82 |
|
|
// Send IP4 + TCP + Flag with ACk
|
83 |
|
|
tb_top.u_tb_eth.set_flow_type(5);//L4
|
84 |
|
|
tb_top.u_tb_eth.set_L2_protocol(0); // Ethernet without VLAN
|
85 |
|
|
tb_top.u_tb_eth.set_L3_protocol(4); // IPV4
|
86 |
|
|
tb_top.u_tb_eth.set_L4_protocol(0); // TCP
|
87 |
|
|
tb_top.u_tb_eth.set_IP_header(32'h0a010102,32'h0a010101,0,1,0,0,0,6);
|
88 |
|
|
tb_top.u_tb_eth.set_TCP_header_fields(0,16'h10,0,0);
|
89 |
|
|
tb_top.u_tb_eth.set_TCP_port_numbers(16'h1000,16'h50); // decimal: 80. Hex:50
|
90 |
|
|
tb_top.u_tb_eth.print_packet_parameters();
|
91 |
|
|
tb_top.u_tb_eth.transmit_packet_sequence(1, 96, 1, 500000);
|
92 |
|
|
#1000; // wait for IFG
|
93 |
|
|
$display("Status: End of Transmission Loop");
|
94 |
|
|
end
|
95 |
|
|
begin
|
96 |
|
|
tb_top.u_tb_eth.wait_for_event(3, 0);
|
97 |
|
|
tb_top.u_tb_eth.wait_for_event(3, 0);
|
98 |
|
|
$display("Status: End of Waiting Event Loop");
|
99 |
|
|
end
|
100 |
|
|
join
|
101 |
|
|
|
102 |
|
|
#3500000;
|
103 |
|
|
$display("Status: End of Waiting Delay Loop");
|
104 |
|
|
|
105 |
|
|
`TB_AGENTS_GMAC.full_mii.status; // test status
|
106 |
|
|
|
107 |
|
|
// Check the Transmitted & Received Frame cnt
|
108 |
|
|
if(`TB_AGENTS_GMAC.full_mii.transmitted_packet_count != `TB_AGENTS_GMAC.full_mii.receive_packet_count)
|
109 |
|
|
`TB_GLBL.test_err;
|
110 |
|
|
|
111 |
|
|
// Check the Transmitted & Received Byte cnt
|
112 |
|
|
if(`TB_AGENTS_GMAC.full_mii.transmitted_packet_byte_count != `TB_AGENTS_GMAC.full_mii.receive_packet_byte_count)
|
113 |
|
|
`TB_GLBL.test_err;
|
114 |
|
|
|
115 |
|
|
if(`TB_AGENTS_GMAC.full_mii.receive_crc_err_count)
|
116 |
|
|
`TB_GLBL.test_err;
|
117 |
|
|
|
118 |
|
|
|
119 |
|
|
endtask
|
120 |
|
|
|