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dbrochart |
######################################################################
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#### ####
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#### README.txt ####
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#### ####
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#### This file is part of the turbo decoder IP core project ####
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#### http://www.opencores.org/projects/turbocodes/ ####
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#### ####
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#### Author(s): ####
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#### - David Brochart(dbrochart@opencores.org) ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2005 Authors ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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Turbo Decoder Release 0.3
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=========================
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MAIN FEATURES
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-------------
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* Double binary, DVB-RCS code
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* Soft Output Viterbi Algorithm
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* MyHDL cycle/bit accurate model
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* Synthesizable VHDL model
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MyHDL MODEL
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-----------
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For help : python launchTurbo.py -help
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For default execution : python launchTurbo.py
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It writes the Bit Error Rate for each iteration into a file:
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turbo0.txt <- BER before decoding
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turbo1.txt <- BER for iteration #1
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turbo2.txt <- BER for iteration #2
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turbo3.txt <- BER for iteration #3
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VHDL MODEL
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----------
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The top-level entity is "turboDec".
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All the turbo decoder parameters are stored in the "turbopack.vhd" file.
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You can modify:
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- the code rate (RATE)
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- the number of decoding iterations (IT)
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- the interleaver frame size (FRSIZE)
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- the trellis' length (TREL1_LEN and TREL2_LEN)
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- the received decoder signal width (SIG_WIDTH)
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- the extrinsic information signal width (Z_WIDTH)
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- the accumulated distance signal width (ACC_DIST_WIDTH)
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AUTHOR
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------
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David Brochart
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