| 1 |
7 |
dbrochart |
######################################################################
|
| 2 |
|
|
#### ####
|
| 3 |
|
|
#### clock.py ####
|
| 4 |
|
|
#### ####
|
| 5 |
|
|
#### This file is part of the turbo decoder IP core project ####
|
| 6 |
|
|
#### http://www.opencores.org/projects/turbocodes/ ####
|
| 7 |
|
|
#### ####
|
| 8 |
|
|
#### Author(s): ####
|
| 9 |
|
|
#### - David Brochart(dbrochart@opencores.org) ####
|
| 10 |
|
|
#### ####
|
| 11 |
|
|
#### All additional information is available in the README.txt ####
|
| 12 |
|
|
#### file. ####
|
| 13 |
|
|
#### ####
|
| 14 |
|
|
######################################################################
|
| 15 |
|
|
#### ####
|
| 16 |
|
|
#### Copyright (C) 2005 Authors ####
|
| 17 |
|
|
#### ####
|
| 18 |
|
|
#### This source file may be used and distributed without ####
|
| 19 |
|
|
#### restriction provided that this copyright statement is not ####
|
| 20 |
|
|
#### removed from the file and that any derivative work contains ####
|
| 21 |
|
|
#### the original copyright notice and the associated disclaimer. ####
|
| 22 |
|
|
#### ####
|
| 23 |
|
|
#### This source file is free software; you can redistribute it ####
|
| 24 |
|
|
#### and/or modify it under the terms of the GNU Lesser General ####
|
| 25 |
|
|
#### Public License as published by the Free Software Foundation; ####
|
| 26 |
|
|
#### either version 2.1 of the License, or (at your option) any ####
|
| 27 |
|
|
#### later version. ####
|
| 28 |
|
|
#### ####
|
| 29 |
|
|
#### This source is distributed in the hope that it will be ####
|
| 30 |
|
|
#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
|
| 31 |
|
|
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
|
| 32 |
|
|
#### PURPOSE. See the GNU Lesser General Public License for more ####
|
| 33 |
|
|
#### details. ####
|
| 34 |
|
|
#### ####
|
| 35 |
|
|
#### You should have received a copy of the GNU Lesser General ####
|
| 36 |
|
|
#### Public License along with this source; if not, download it ####
|
| 37 |
|
|
#### from http://www.opencores.org/lgpl.shtml ####
|
| 38 |
|
|
#### ####
|
| 39 |
|
|
######################################################################
|
| 40 |
|
|
|
| 41 |
|
|
|
| 42 |
|
|
|
| 43 |
|
|
from myhdl import Signal, delay, posedge, negedge, instance, always
|
| 44 |
|
|
|
| 45 |
|
|
def clkGen(clk, duration_1 = 10, duration_2 = 10):
|
| 46 |
|
|
""" Clock signal generator.
|
| 47 |
|
|
|
| 48 |
|
|
duration_1 -- first level duration
|
| 49 |
|
|
duration_2 -- second level duration
|
| 50 |
|
|
clk -- out : generated clock signal
|
| 51 |
|
|
|
| 52 |
|
|
"""
|
| 53 |
|
|
@instance
|
| 54 |
|
|
def clkGenLogic():
|
| 55 |
|
|
while 1:
|
| 56 |
|
|
yield delay(duration_1)
|
| 57 |
|
|
clk.next = not clk.val
|
| 58 |
|
|
yield delay(duration_2)
|
| 59 |
|
|
clk.next = not clk.val
|
| 60 |
|
|
return clkGenLogic
|
| 61 |
|
|
|
| 62 |
|
|
def rstGen(rst, start = 5, duration = 10):
|
| 63 |
|
|
""" Reset signal generator.
|
| 64 |
|
|
|
| 65 |
|
|
start -- reset pulse start time
|
| 66 |
|
|
duration -- reset pulse duration
|
| 67 |
|
|
rst -- out : generated reset signal
|
| 68 |
|
|
|
| 69 |
|
|
"""
|
| 70 |
|
|
@instance
|
| 71 |
|
|
def rstGenLogic():
|
| 72 |
|
|
yield delay(start)
|
| 73 |
|
|
rst.next = not rst.val
|
| 74 |
|
|
yield delay(duration)
|
| 75 |
|
|
rst.next = not rst.val
|
| 76 |
|
|
return rstGenLogic
|
| 77 |
|
|
|
| 78 |
|
|
def clkDiv(clk, rst, clkout):
|
| 79 |
|
|
""" Clock divider (freq/2).
|
| 80 |
|
|
|
| 81 |
|
|
clk, rst -- in : clock and negative reset
|
| 82 |
|
|
clkout -- out : clock which frequency is half of the input clock
|
| 83 |
|
|
|
| 84 |
|
|
"""
|
| 85 |
|
|
@always(clk.posedge, rst.negedge)
|
| 86 |
|
|
def clkDivLogic():
|
| 87 |
|
|
if rst.val == 0:
|
| 88 |
|
|
clkout.next = False
|
| 89 |
|
|
else:
|
| 90 |
|
|
clkout.next = not clkout.val
|
| 91 |
|
|
return clkDivLogic
|
