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dbrochart |
######################################################################
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#### ####
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#### coder.py ####
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#### ####
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#### This file is part of the turbo decoder IP core project ####
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#### http://www.opencores.org/projects/turbocodes/ ####
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#### ####
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#### Author(s): ####
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#### - David Brochart(dbrochart@opencores.org) ####
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#### ####
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#### All additional information is available in the README.txt ####
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#### file. ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2005 Authors ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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from myhdl import Signal, posedge, negedge, always_comb, always
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def coderState(clk, rst, a, b, q1, q2, q3):
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""" Coder state registers.
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clk, rst -- in : clock and negative reset
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a, b -- in : original data
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q1, q2, q3 -- out : coder registers
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"""
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@always(clk.posedge, rst.negedge)
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def coderStateLogic():
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if rst.val == 0:
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q1.next = 0
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q2.next = 0
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q3.next = 0
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else:
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q1.next = a.val ^ b.val ^ q1.val ^ q3.val
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q2.next = q1.val ^ b.val
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q3.next = q2.val ^ b.val
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return coderStateLogic
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def coderY1Y2(a, b, q1, q2, q3, y1, y2):
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""" Coder redundant output generation.
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a, b -- in : original data signals
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q1, q2, q3 -- in : coder registers
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y1, y2 -- out : coder redundant data signals
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"""
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@always_comb
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def coderY1Y2Logic():
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y1.next = a.val ^ b.val ^ q1.val ^ q3.val ^ q2.val ^ q3.val
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y2.next = a.val ^ b.val ^ q1.val ^ q3.val ^ q3.val
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return coderY1Y2Logic
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def coder(clk, rst, a, b, y1, y2):
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""" Coder top level.
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clk, rst -- in : clock and negative reset
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a, b -- in : original data signals (= systematic data)
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y1, y2 -- out : coder redundant data signals
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"""
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q1 = Signal(bool(0))
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q2 = Signal(bool(0))
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q3 = Signal(bool(0))
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coderState_i0 = coderState(clk, rst, a, b, q1, q2, q3)
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coderY1Y2_i0 = coderY1Y2(a, b, q1, q2, q3, y1, y2)
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return coderState_i0, coderY1Y2_i0
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