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dbrochart |
######################################################################
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#### ####
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#### interleaver.py ####
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#### ####
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#### This file is part of the turbo decoder IP core project ####
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#### http://www.opencores.org/projects/turbocodes/ ####
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#### ####
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#### Author(s): ####
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#### - David Brochart(dbrochart@opencores.org) ####
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#### ####
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#### All additional information is available in the README.txt ####
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#### file. ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2005 Authors ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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from myhdl import Signal, intbv, posedge, negedge, always
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def interleaver(clk, rst, d, q, frSize = 48, delay = 0, minVal = 0, maxVal = 2, dim = 2, way = 0):
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""" DVB-RCS (de)interleaver.
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frSize -- frame size
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delay -- number of clock cycles to wait before starting the (de)interleaver
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minVal, maxVal -- min and max values of the stored signals
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dim -- number of dimensions of the stored signals
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way -- 0 for interleaving, 1 for deinterleaving
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clk, rst -- in : clock and negative reset
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d -- in : input data
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q -- out : interleaved data
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"""
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array1 = [[Signal(intbv(0, minVal, maxVal)) for l in range(dim)] for k in range(frSize)]
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array2 = [[Signal(intbv(0, minVal, maxVal)) for l in range(dim)] for k in range(frSize)]
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full = Signal(bool(0))
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i = Signal(intbv(0, 0, frSize))
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j = Signal(intbv(0, 0, frSize))
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iTmp = Signal(intbv(0, 0, frSize))
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iTmp1 = intbv(0, 0, 2 * frSize)
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iTmp2 = intbv(0, 0, 2 * frSize)
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iTmp3 = intbv(0, 0, 2 * frSize)
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cnt = Signal(intbv(0, 0, delay + 1))
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if frSize == 48:
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p0 = 11
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p1 = 24
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p2 = 0
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p3 = 24
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elif frSize == 64:
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p0 = 7
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p1 = 34
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p2 = 32
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p3 = 2
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elif frSize == 212:
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p0 = 13
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p1 = 106
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p2 = 108
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p3 = 2
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elif frSize == 220:
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p0 = 23
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p1 = 112
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p2 = 4
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p3 = 116
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elif frSize == 228:
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p0 = 17
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p1 = 116
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p2 = 72
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p3 = 188
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elif frSize == 424:
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p0 = 11
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p1 = 6
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p2 = 8
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p3 = 2
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elif frSize == 432:
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p0 = 13
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p1 = 0
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p2 = 4
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p3 = 8
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elif frSize == 440:
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p0 = 13
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p1 = 10
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p2 = 4
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p3 = 2
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elif frSize == 848:
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p0 = 19
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p1 = 2
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p2 = 16
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p3 = 6
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elif frSize == 856:
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p0 = 19
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p1 = 428
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p2 = 224
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p3 = 652
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elif frSize == 864:
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p0 = 19
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p1 = 2
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p2 = 16
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p3 = 6
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elif frSize == 752:
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p0 = 19
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p1 = 376
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p2 = 224
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p3 = 600
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else:
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print "ERROR: interleaver does not have a valid DVB-RCS frame size!"
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@always(clk.posedge, rst.negedge)
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def interleaverLogic():
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if rst.val == 0:
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iTmp.next = 0
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i.next = 0
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j.next = 0
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cnt.next = 0
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full.next = 0
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for l in range(dim):
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q[l].next = 0
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for k in range(frSize):
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for l in range(dim):
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array1[k][l].next = 0
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array2[k][l].next = 0
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else:
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if cnt.val < delay:
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cnt.next = cnt.val + 1
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else:
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if j.val[2:0] == 0:
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p = 0
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elif j.val[2:0] == 1:
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p = frSize / 2 + p1
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elif j.val[2:0] == 2:
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p = p2
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else: # if j.val[2:0] == 3:
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p = frSize / 2 + p3
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iTmp1 = iTmp.val + p0
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if iTmp1 >= frSize:
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iTmp2 = iTmp1 - frSize
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else:
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iTmp2 = iTmp1
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iTmp.next = iTmp2
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iTmp3 = iTmp2 + p + 1
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if iTmp3 >= 2 * frSize:
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i.next = iTmp3 - 2 * frSize
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elif iTmp3 >= frSize:
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i.next = iTmp3 - frSize
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else:
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i.next = iTmp3
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# i.next = intbv((p0 * j.val + p + 1) % frSize)
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if j.val == (frSize - 1):
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j.next = 0
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full.next = not full.val
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else:
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j.next = j.val + 1
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if way == 0:
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ii = i.val
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jj = j.val
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else:
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ii = j.val
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jj = i.val
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if full.val == 0:
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for l in range(dim):
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array1[int(jj)][l].next = d[l].val
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q[l].next = array2[int(ii)][l].val
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else:
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for l in range(dim):
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array2[int(jj)][l].next = d[l].val
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q[l].next = array1[int(ii)][l].val
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return interleaverLogic
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