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Subversion Repositories turbocodes

[/] [turbocodes/] [trunk/] [src/] [myhdl/] [synthesis.py] - Blame information for rev 7

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from myhdl import toVHDL, Signal
from misc import delayer
 
clk = Signal(bool(0))
rst = Signal(bool(0))
d = Signal(bool(0))
q = Signal(bool(0))
 
synthesis_i0 = toVHDL(delayer, clk, rst, d, q)

Line No.	Rev	Author	Line
1	7	dbrochart	`from myhdl import toVHDL, Signal`
2			`from misc import delayer`
3
4			`clk = Signal(bool(0))`
5			`rst = Signal(bool(0))`
6			`d = Signal(bool(0))`
7			`q = Signal(bool(0))`
8
9			`synthesis_i0 = toVHDL(delayer, clk, rst, d, q)`

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[/] [turbocodes/] [trunk/] [src/] [myhdl/] [synthesis.py] - Blame information for rev 7