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dbrochart |
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---- ----
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---- accDistSel_synth.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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architecture synth of accDistSel is
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signal comp : std_logic_vector(23 downto 0);
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signal accDistCod_s : ARRAY8b;
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begin
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accDistCod <= accDistCod_s;
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min4_g : for i in 0 to 7 generate
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min4_i : min4 port map (
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op1 => accDist(FROM2TO(4 * i)),
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op2 => accDist(FROM2TO(4 * i + 1)),
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op3 => accDist(FROM2TO(4 * i + 2)),
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op4 => accDist(FROM2TO(4 * i + 3)),
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res1 => comp(3 * i),
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res2 => comp(3 * i + 1),
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res3 => comp(3 * i + 2)
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);
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end generate;
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cod2_g : for i in 0 to 7 generate
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cod2_i : cod2 port map (
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in1 => comp(3 * i),
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in2 => comp(3 * i + 1),
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in3 => comp(3 * i + 2),
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outCod => accDistCod_s(i)
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);
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end generate;
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mux4_g : for i in 0 to 7 generate
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mux4_i : mux4 port map (
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in1 => accDist(FROM2TO(4 * i)),
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in2 => accDist(FROM2TO(4 * i + 1)),
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in3 => accDist(FROM2TO(4 * i + 2)),
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in4 => accDist(FROM2TO(4 * i + 3)),
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sel => accDistCod_s(i),
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outSel => accDistOut(i)
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);
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end generate;
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end;
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