| 1 |
7 |
dbrochart |
----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- acs_synth.vhd ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the turbo decoder IP core project ----
|
| 6 |
|
|
---- http://www.opencores.org/projects/turbocodes/ ----
|
| 7 |
|
|
---- ----
|
| 8 |
|
|
---- Author(s): ----
|
| 9 |
|
|
---- - David Brochart(dbrochart@opencores.org) ----
|
| 10 |
|
|
---- ----
|
| 11 |
|
|
---- All additional information is available in the README.txt ----
|
| 12 |
|
|
---- file. ----
|
| 13 |
|
|
---- ----
|
| 14 |
|
|
----------------------------------------------------------------------
|
| 15 |
|
|
---- ----
|
| 16 |
|
|
---- Copyright (C) 2005 Authors ----
|
| 17 |
|
|
---- ----
|
| 18 |
|
|
---- This source file may be used and distributed without ----
|
| 19 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 20 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 21 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 22 |
|
|
---- ----
|
| 23 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 24 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 25 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 26 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 27 |
|
|
---- later version. ----
|
| 28 |
|
|
---- ----
|
| 29 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 30 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 31 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 32 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 33 |
|
|
---- details. ----
|
| 34 |
|
|
---- ----
|
| 35 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 36 |
|
|
---- Public License along with this source; if not, download it ----
|
| 37 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 38 |
|
|
---- ----
|
| 39 |
|
|
----------------------------------------------------------------------
|
| 40 |
|
|
|
| 41 |
|
|
|
| 42 |
|
|
|
| 43 |
|
|
architecture synth of acs is
|
| 44 |
|
|
signal distance16 : ARRAY16a;
|
| 45 |
|
|
signal accDist8 : ARRAY8a;
|
| 46 |
|
|
signal accDist32 : ARRAY32c;
|
| 47 |
|
|
signal accDistDel32 : ARRAY32c;
|
| 48 |
|
|
signal accDistDel4 : ARRAY4a;
|
| 49 |
|
|
signal selAccDistL : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
|
| 50 |
|
|
begin
|
| 51 |
|
|
distances_i0 : distances port map (
|
| 52 |
|
|
a => a,
|
| 53 |
|
|
b => b,
|
| 54 |
|
|
y => y,
|
| 55 |
|
|
w => w,
|
| 56 |
|
|
z => z,
|
| 57 |
|
|
distance16 => distance16
|
| 58 |
|
|
);
|
| 59 |
|
|
accDist_i0 : accDist port map (
|
| 60 |
|
|
clk => clk,
|
| 61 |
|
|
rst => rst,
|
| 62 |
|
|
accDistReg => accDist8,
|
| 63 |
|
|
dist => distance16,
|
| 64 |
|
|
accDistNew => accDist32
|
| 65 |
|
|
);
|
| 66 |
|
|
delayer_g0 : for i in 0 to 31 generate
|
| 67 |
|
|
delayer_i : delayer generic map (
|
| 68 |
|
|
delay => TREL1_LEN - 1
|
| 69 |
|
|
)
|
| 70 |
|
|
port map (
|
| 71 |
|
|
clk => clk,
|
| 72 |
|
|
rst => rst,
|
| 73 |
|
|
d => accDist32(FROM2TO(i)),
|
| 74 |
|
|
q => accDistDel32(i)
|
| 75 |
|
|
);
|
| 76 |
|
|
end generate;
|
| 77 |
|
|
mux8_i0 : mux8 port map (
|
| 78 |
|
|
in8x4 => accDistDel32,
|
| 79 |
|
|
sel => selStateL,
|
| 80 |
|
|
outSel4 => accDistDel4
|
| 81 |
|
|
);
|
| 82 |
|
|
mux4_i0 : mux4 port map (
|
| 83 |
|
|
in1 => accDistDel4(0),
|
| 84 |
|
|
in2 => accDistDel4(1),
|
| 85 |
|
|
in3 => accDistDel4(2),
|
| 86 |
|
|
in4 => accDistDel4(3),
|
| 87 |
|
|
sel => selTransL,
|
| 88 |
|
|
outSel => selAccDistL
|
| 89 |
|
|
);
|
| 90 |
|
|
subs_g : for i in 0 to 3 generate
|
| 91 |
|
|
subs_i : subs port map (
|
| 92 |
|
|
op1 => accDistDel4(i),
|
| 93 |
|
|
op2 => selAccDistL,
|
| 94 |
|
|
res => weight(i)
|
| 95 |
|
|
);
|
| 96 |
|
|
end generate;
|
| 97 |
|
|
accDistSel_i0 : accDistSel port map (
|
| 98 |
|
|
accDist => accDist32,
|
| 99 |
|
|
accDistCod => stateDist,
|
| 100 |
|
|
accDistOut => accDist8
|
| 101 |
|
|
);
|
| 102 |
|
|
stateSel_i0 : stateSel port map (
|
| 103 |
|
|
stateDist => accDist8,
|
| 104 |
|
|
selState => selState
|
| 105 |
|
|
);
|
| 106 |
|
|
end;
|
