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[/] [turbocodes/] [trunk/] [src/] [vhdl/] [cod2_synth.vhd] - Blame information for rev 7
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dbrochart |
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---- ----
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---- cod2_synth.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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architecture synth of cod2 is
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begin
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process (in1, in2, in3)
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variable tmp : std_logic_vector(2 downto 0);
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begin
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tmp := in1 & in2 & in3;
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case tmp is
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when "101" =>
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outCod <= "00";
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when "111" =>
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outCod <= "00";
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when "001" =>
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outCod <= "01";
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when "011" =>
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outCod <= "01";
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when "010" =>
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outCod <= "10";
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when "110" =>
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outCod <= "10";
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when "000" =>
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outCod <= "11";
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when others =>
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outCod <= "11";
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end case;
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end process;
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end;
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