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dbrochart |
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---- ----
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---- min8_synth.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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architecture synth of min8 is
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signal tmp : ARRAY6a;
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signal res_s : std_logic_vector(6 downto 0);
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begin
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res <= res_s;
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cmp2_i0 : cmp2 port map (
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op1 => op(0),
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op2 => op(1),
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res => res_s(0)
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);
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cmp2_i1 : cmp2 port map (
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op1 => op(2),
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op2 => op(3),
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res => res_s(1)
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);
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cmp2_i2 : cmp2 port map (
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op1 => op(4),
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op2 => op(5),
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res => res_s(2)
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);
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cmp2_i3 : cmp2 port map (
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op1 => op(6),
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op2 => op(7),
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res => res_s(3)
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);
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mux2_i0 : mux2 port map (
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in1 => op(0),
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in2 => op(1),
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sel => res_s(0),
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outSel => tmp(0)
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);
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mux2_i1 : mux2 port map (
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in1 => op(2),
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in2 => op(3),
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sel => res_s(1),
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outSel => tmp(1)
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);
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mux2_i2 : mux2 port map (
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in1 => op(4),
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in2 => op(5),
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sel => res_s(2),
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outSel => tmp(2)
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);
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mux2_i3 : mux2 port map (
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in1 => op(6),
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in2 => op(7),
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sel => res_s(3),
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outSel => tmp(3)
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);
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cmp2_i4 : cmp2 port map (
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op1 => tmp(0),
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op2 => tmp(1),
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res => res_s(4)
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);
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cmp2_i5 : cmp2 port map (
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op1 => tmp(2),
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op2 => tmp(3),
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res => res_s(5)
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);
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mux2_i4 : mux2 port map (
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in1 => tmp(0),
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in2 => tmp(1),
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sel => res_s(4),
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outSel => tmp(4)
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);
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mux2_i5 : mux2 port map (
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in1 => tmp(2),
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in2 => tmp(3),
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sel => res_s(5),
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outSel => tmp(5)
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);
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cmp2_i6 : cmp2 port map (
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op1 => tmp(4),
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op2 => tmp(5),
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res => res_s(6)
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);
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end;
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