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dbrochart |
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---- ----
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---- sova_synth.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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architecture synth of sova is
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signal selStateL2 : std_logic_vector(2 downto 0);
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signal selStateL1 : std_logic_vector(2 downto 0);
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signal selState : std_logic_vector(2 downto 0);
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signal selTransL2 : std_logic_vector(1 downto 0);
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signal selTrans : ARRAY8b;
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signal selTransL1 : ARRAY8b;
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signal weight : ARRAY4a;
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signal stateL1 : ARRAY4d;
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signal llr0 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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signal llr1 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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signal llr2 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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signal llr3 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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signal zinDel : ARRAY4c;
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signal aNoisyDel : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal bNoisyDel : std_logic_vector(SIG_WIDTH - 1 downto 0);
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begin
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acs_i0 : acs port map (
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clk => clk,
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rst => rst,
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a => aNoisy,
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b => bNoisy,
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y => yNoisy,
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w => wNoisy,
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z => zin,
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selStateL => selStateL2,
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selTransL => selTransL2,
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selState => selState,
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stateDist => selTrans,
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weight => weight
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);
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trellis1_i0 : trellis1 port map (
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clk => clk,
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rst => rst,
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selState => selState,
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selTrans => selTrans,
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selStateL2 => selStateL2,
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selStateL1 => selStateL1,
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stateL1 => stateL1,
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selTransL2 => selTransL2
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);
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trellis2_i0 : trellis2 port map (
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clk => clk,
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rst => rst,
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selState => selStateL1,
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state => stateL1,
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selTrans => selTransL1,
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weight => weight,
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llr0 => llr0,
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llr1 => llr1,
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llr2 => llr2,
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llr3 => llr3,
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a => aClean,
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b => bClean
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);
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delayer_g0 : for i in 0 to 7 generate
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delayer_i : delayer generic map (
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delay => TREL1_LEN - 1
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)
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port map (
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clk => clk,
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rst => rst,
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d => selTrans(i),
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q => selTransL1(i)
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);
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end generate;
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delayer_g1 : for i in 0 to 3 generate
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delayer_i : delayer generic map (
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delay => TREL1_LEN + TREL2_LEN
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)
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port map (
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clk => clk,
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rst => rst,
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d => zin(i),
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q => zinDel(i)
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);
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end generate;
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delayer_i0 : delayer generic map (
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delay => TREL1_LEN + TREL2_LEN
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)
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port map (
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clk => clk,
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rst => rst,
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d => aNoisy,
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q => aNoisyDel
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);
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delayer_i1 : delayer generic map (
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delay => TREL1_LEN + TREL2_LEN
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)
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port map (
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clk => clk,
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rst => rst,
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d => bNoisy,
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q => bNoisyDel
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);
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extInf_i0 : extInf port map (
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llr0 => llr0,
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llr1 => llr1,
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llr2 => llr2,
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llr3 => llr3,
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zin => zinDel,
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a => aNoisyDel,
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b => bNoisyDel,
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zout => zout
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);
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end;
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