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dbrochart |
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---- ----
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---- trellis1_synth.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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architecture synth of trellis1 is
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signal pathIdReg : ARRAY8d;
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signal reg : ARRAY_TREL1_LENx8;
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begin
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process (clk, rst)
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variable free : std_logic_vector(7 downto 0);
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variable freeBeg : std_logic_vector(7 downto 0);
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variable pastState : ARRAY8d;
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variable pathId : ARRAY8d;
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variable current_state : INT3BIT;
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variable freePathId : INT3BIT;
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variable state_l3 : INT2BIT;
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variable state_l2 : INT2BIT;
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variable state_l1 : INT2BIT;
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variable outState_l2 : std_logic_vector(2 downto 0);
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variable outState_l1 : std_logic_vector(2 downto 0);
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begin
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if rst = '0' then
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for i in 0 to 3 loop
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stateL1(i) <= (others => '0');
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end loop;
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selStateL1 <= (others => '0');
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selStateL2 <= (others => '0');
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selTransL2 <= (others => '0');
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for i in 0 to 7 loop
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pathIdReg(i) <= 0;
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for j in 0 to TREL1_LEN - 1 loop
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reg(j * 8 + i) <= 0;
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end loop;
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end loop;
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elsif clk = '1' and clk'event then
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free := "11111111";
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for i in 0 to 7 loop
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pastState(i) := TRANS2STATE(i * 4 + conv_integer(unsigned(selTrans(i))));
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pathId(i) := pathIdReg(pastState(i));
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free(pathId(i)) := '0';
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end loop;
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freeBeg := "11111111";
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for i in 0 to 7 loop
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current_state := i;
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if freeBeg(pathId(current_state)) = '1' then
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reg(pathId(current_state)) <= conv_integer(unsigned(std_logic_vector(conv_unsigned(current_state, 3))(1 downto 0)));
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freeBeg(pathId(i)) := '0';
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pathIdReg(current_state) <= pathId(current_state);
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for j in 0 to TREL1_LEN - 2 loop
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reg((j + 1) * 8 + pathId(current_state)) <= reg(j * 8 + pathId(current_state));
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end loop;
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else
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if free(0) = '1' then
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freePathId := 0;
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end if;
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if free(1 downto 0) = "10" then
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freePathId := 1;
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end if;
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if free(2 downto 0) = "100" then
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freePathId := 2;
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end if;
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if free(3 downto 0) = "1000" then
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freePathId := 3;
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end if;
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if free(4 downto 0) = "10000" then
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freePathId := 4;
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end if;
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if free(5 downto 0) = "100000" then
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freePathId := 5;
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end if;
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if free(6 downto 0) = "1000000" then
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freePathId := 6;
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end if;
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if free(7 downto 0) = "10000000" then
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freePathId := 7;
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end if;
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reg(freePathId) <= conv_integer(unsigned(std_logic_vector(conv_unsigned(current_state, 3))(1 downto 0)));
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free(freePathId) := '0';
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pathIdReg(current_state) <= freePathId;
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for j in 0 to TREL1_LEN - 2 loop
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reg((j + 1) * 8 + freePathId) <= reg(j * 8 + pathId(current_state));
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end loop;
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end if;
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end loop;
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state_l3 := reg((TREL1_LEN - 3) * 8 + pathId(conv_integer(unsigned(selState))));
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state_l2 := reg((TREL1_LEN - 2) * 8 + pathId(conv_integer(unsigned(selState))));
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state_l1 := reg((TREL1_LEN - 1) * 8 + pathId(conv_integer(unsigned(selState))));
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outState_l2(2) := std_logic_vector(conv_unsigned(state_l3, 2))(1) xor (std_logic_vector(conv_unsigned(state_l3, 2))(0) xor std_logic_vector(conv_unsigned(state_l2, 2))(1));
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outState_l2(1 downto 0) := std_logic_vector(conv_unsigned(state_l2, 2));
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outState_l1(2) := std_logic_vector(conv_unsigned(state_l2, 2))(1) xor (std_logic_vector(conv_unsigned(state_l2, 2))(0) xor std_logic_vector(conv_unsigned(state_l1, 2))(1));
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outState_l1(1 downto 0) := std_logic_vector(conv_unsigned(state_l1, 2));
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selStateL1 <= outState_l1;
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selStateL2 <= outState_l2;
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selTransL2 <= std_logic_vector(conv_unsigned(STATE2TRANS(conv_integer(unsigned(outState_l2)) * 4 + state_l1), 2));
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for i in 0 to 3 loop
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stateL1(i) <= std_logic_vector(conv_unsigned(TRANS2STATE(conv_integer(unsigned(outState_l2)) * 4 + i), 3));
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end loop;
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end if;
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end process;
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end;
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