| 1 |
7 |
dbrochart |
----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- trellis1_synth.vhd ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the turbo decoder IP core project ----
|
| 6 |
|
|
---- http://www.opencores.org/projects/turbocodes/ ----
|
| 7 |
|
|
---- ----
|
| 8 |
|
|
---- Author(s): ----
|
| 9 |
|
|
---- - David Brochart(dbrochart@opencores.org) ----
|
| 10 |
|
|
---- ----
|
| 11 |
|
|
---- All additional information is available in the README.txt ----
|
| 12 |
|
|
---- file. ----
|
| 13 |
|
|
---- ----
|
| 14 |
|
|
----------------------------------------------------------------------
|
| 15 |
|
|
---- ----
|
| 16 |
|
|
---- Copyright (C) 2005 Authors ----
|
| 17 |
|
|
---- ----
|
| 18 |
|
|
---- This source file may be used and distributed without ----
|
| 19 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 20 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 21 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 22 |
|
|
---- ----
|
| 23 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 24 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 25 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 26 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 27 |
|
|
---- later version. ----
|
| 28 |
|
|
---- ----
|
| 29 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 30 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 31 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 32 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 33 |
|
|
---- details. ----
|
| 34 |
|
|
---- ----
|
| 35 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 36 |
|
|
---- Public License along with this source; if not, download it ----
|
| 37 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 38 |
|
|
---- ----
|
| 39 |
|
|
----------------------------------------------------------------------
|
| 40 |
|
|
|
| 41 |
|
|
|
| 42 |
|
|
|
| 43 |
|
|
architecture synth of trellis1 is
|
| 44 |
|
|
signal pathIdReg : ARRAY8d;
|
| 45 |
|
|
signal reg : ARRAY_TREL1_LENx8;
|
| 46 |
|
|
begin
|
| 47 |
|
|
process (clk, rst)
|
| 48 |
|
|
variable free : std_logic_vector(7 downto 0);
|
| 49 |
|
|
variable freeBeg : std_logic_vector(7 downto 0);
|
| 50 |
|
|
variable pastState : ARRAY8d;
|
| 51 |
|
|
variable pathId : ARRAY8d;
|
| 52 |
|
|
variable current_state : INT3BIT;
|
| 53 |
|
|
variable freePathId : INT3BIT;
|
| 54 |
|
|
variable state_l3 : INT2BIT;
|
| 55 |
|
|
variable state_l2 : INT2BIT;
|
| 56 |
|
|
variable state_l1 : INT2BIT;
|
| 57 |
|
|
variable outState_l2 : std_logic_vector(2 downto 0);
|
| 58 |
|
|
variable outState_l1 : std_logic_vector(2 downto 0);
|
| 59 |
|
|
begin
|
| 60 |
|
|
if rst = '0' then
|
| 61 |
|
|
for i in 0 to 3 loop
|
| 62 |
|
|
stateL1(i) <= (others => '0');
|
| 63 |
|
|
end loop;
|
| 64 |
|
|
selStateL1 <= (others => '0');
|
| 65 |
|
|
selStateL2 <= (others => '0');
|
| 66 |
|
|
selTransL2 <= (others => '0');
|
| 67 |
|
|
for i in 0 to 7 loop
|
| 68 |
|
|
pathIdReg(i) <= 0;
|
| 69 |
|
|
for j in 0 to TREL1_LEN - 1 loop
|
| 70 |
|
|
reg(j * 8 + i) <= 0;
|
| 71 |
|
|
end loop;
|
| 72 |
|
|
end loop;
|
| 73 |
|
|
elsif clk = '1' and clk'event then
|
| 74 |
|
|
free := "11111111";
|
| 75 |
|
|
for i in 0 to 7 loop
|
| 76 |
|
|
pastState(i) := TRANS2STATE(i * 4 + conv_integer(unsigned(selTrans(i))));
|
| 77 |
|
|
pathId(i) := pathIdReg(pastState(i));
|
| 78 |
|
|
free(pathId(i)) := '0';
|
| 79 |
|
|
end loop;
|
| 80 |
|
|
freeBeg := "11111111";
|
| 81 |
|
|
for i in 0 to 7 loop
|
| 82 |
|
|
current_state := i;
|
| 83 |
|
|
if freeBeg(pathId(current_state)) = '1' then
|
| 84 |
|
|
reg(pathId(current_state)) <= conv_integer(unsigned(std_logic_vector(conv_unsigned(current_state, 3))(1 downto 0)));
|
| 85 |
|
|
freeBeg(pathId(i)) := '0';
|
| 86 |
|
|
pathIdReg(current_state) <= pathId(current_state);
|
| 87 |
|
|
for j in 0 to TREL1_LEN - 2 loop
|
| 88 |
|
|
reg((j + 1) * 8 + pathId(current_state)) <= reg(j * 8 + pathId(current_state));
|
| 89 |
|
|
end loop;
|
| 90 |
|
|
else
|
| 91 |
|
|
if free(0) = '1' then
|
| 92 |
|
|
freePathId := 0;
|
| 93 |
|
|
end if;
|
| 94 |
|
|
if free(1 downto 0) = "10" then
|
| 95 |
|
|
freePathId := 1;
|
| 96 |
|
|
end if;
|
| 97 |
|
|
if free(2 downto 0) = "100" then
|
| 98 |
|
|
freePathId := 2;
|
| 99 |
|
|
end if;
|
| 100 |
|
|
if free(3 downto 0) = "1000" then
|
| 101 |
|
|
freePathId := 3;
|
| 102 |
|
|
end if;
|
| 103 |
|
|
if free(4 downto 0) = "10000" then
|
| 104 |
|
|
freePathId := 4;
|
| 105 |
|
|
end if;
|
| 106 |
|
|
if free(5 downto 0) = "100000" then
|
| 107 |
|
|
freePathId := 5;
|
| 108 |
|
|
end if;
|
| 109 |
|
|
if free(6 downto 0) = "1000000" then
|
| 110 |
|
|
freePathId := 6;
|
| 111 |
|
|
end if;
|
| 112 |
|
|
if free(7 downto 0) = "10000000" then
|
| 113 |
|
|
freePathId := 7;
|
| 114 |
|
|
end if;
|
| 115 |
|
|
reg(freePathId) <= conv_integer(unsigned(std_logic_vector(conv_unsigned(current_state, 3))(1 downto 0)));
|
| 116 |
|
|
free(freePathId) := '0';
|
| 117 |
|
|
pathIdReg(current_state) <= freePathId;
|
| 118 |
|
|
for j in 0 to TREL1_LEN - 2 loop
|
| 119 |
|
|
reg((j + 1) * 8 + freePathId) <= reg(j * 8 + pathId(current_state));
|
| 120 |
|
|
end loop;
|
| 121 |
|
|
end if;
|
| 122 |
|
|
end loop;
|
| 123 |
|
|
state_l3 := reg((TREL1_LEN - 3) * 8 + pathId(conv_integer(unsigned(selState))));
|
| 124 |
|
|
state_l2 := reg((TREL1_LEN - 2) * 8 + pathId(conv_integer(unsigned(selState))));
|
| 125 |
|
|
state_l1 := reg((TREL1_LEN - 1) * 8 + pathId(conv_integer(unsigned(selState))));
|
| 126 |
|
|
outState_l2(2) := std_logic_vector(conv_unsigned(state_l3, 2))(1) xor (std_logic_vector(conv_unsigned(state_l3, 2))(0) xor std_logic_vector(conv_unsigned(state_l2, 2))(1));
|
| 127 |
|
|
outState_l2(1 downto 0) := std_logic_vector(conv_unsigned(state_l2, 2));
|
| 128 |
|
|
outState_l1(2) := std_logic_vector(conv_unsigned(state_l2, 2))(1) xor (std_logic_vector(conv_unsigned(state_l2, 2))(0) xor std_logic_vector(conv_unsigned(state_l1, 2))(1));
|
| 129 |
|
|
outState_l1(1 downto 0) := std_logic_vector(conv_unsigned(state_l1, 2));
|
| 130 |
|
|
selStateL1 <= outState_l1;
|
| 131 |
|
|
selStateL2 <= outState_l2;
|
| 132 |
|
|
selTransL2 <= std_logic_vector(conv_unsigned(STATE2TRANS(conv_integer(unsigned(outState_l2)) * 4 + state_l1), 2));
|
| 133 |
|
|
for i in 0 to 3 loop
|
| 134 |
|
|
stateL1(i) <= std_logic_vector(conv_unsigned(TRANS2STATE(conv_integer(unsigned(outState_l2)) * 4 + i), 3));
|
| 135 |
|
|
end loop;
|
| 136 |
|
|
end if;
|
| 137 |
|
|
end process;
|
| 138 |
|
|
end;
|
