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dbrochart |
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---- ----
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---- turboDec_synth.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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architecture synth of turboDec is
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signal flipflop : std_logic;
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signal aLim : ARRAY_ITa;
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signal bLim : ARRAY_ITa;
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signal yLim : ARRAY_ITa;
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signal wLim : ARRAY_ITa;
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signal yIntLim : ARRAY_ITa;
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signal wIntLim : ARRAY_ITa;
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signal z : ARRAY_ITb;
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signal yFull : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal wFull : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal yIntFull : std_logic_vector(SIG_WIDTH - 1 downto 0);
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signal wIntFull : std_logic_vector(SIG_WIDTH - 1 downto 0);
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begin
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limiter_i0 : limiter port map (
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a => aNoisy,
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b => bNoisy,
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y => yNoisy,
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w => wNoisy,
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yInt => yIntNoisy,
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wInt => wIntNoisy,
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aLim => aLim(0),
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bLim => bLim(0),
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yLim => yFull,
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wLim => wFull,
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yIntLim => yIntFull,
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wIntLim => wIntFull
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);
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punct_i0 : punct port map (
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clk => clk,
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rst => rst,
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y => yFull,
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w => wFull,
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yInt => yIntFull,
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wInt => wIntFull,
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yPunct => yLim(0),
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wPunct => wLim(0),
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yIntPunct => yIntLim(0),
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wIntPunct => wIntLim(0)
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);
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clkDiv_i0 : clkDiv port map (
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clk => clk,
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rst => rst,
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clkout => flipflop
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);
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z(0) <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
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iteration_g : for i in 0 to (IT - 1) generate
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iteration_i : iteration generic map (
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delay => 2 * i * (TREL1_LEN + TREL2_LEN + 2) + 2 * i * FRSIZE + 2
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)
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port map (
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clk => clk,
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rst => rst,
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flipflop => flipflop,
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a => aLim(i),
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b => bLim(i),
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y => yLim(i),
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w => wLim(i),
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yInt => yIntLim(i),
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wInt => wIntLim(i),
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zin => z(i),
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zout => z(i + 1),
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aDec => aDec(i),
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bDec => bDec(i),
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aDel => aLim(i + 1),
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bDel => bLim(i + 1),
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yDel => yLim(i + 1),
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wDel => wLim(i + 1),
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yIntDel => yIntLim(i + 1),
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wIntDel => wIntLim(i + 1)
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);
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end generate;
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end;
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