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----------------------------------------------------------------------
----                                                              ----
----  turbopack.vhd                                               ----
----                                                              ----
----  This file is part of the turbo decoder IP core project      ----
----  http://www.opencores.org/projects/turbocodes/               ----
----                                                              ----
----  Author(s):                                                  ----
----      - David Brochart(dbrochart@opencores.org)               ----
----                                                              ----
----  All additional information is available in the README.txt   ----
----  file.                                                       ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2005 Authors                                   ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
 
 
 
library ieee;
use ieee.std_logic_1164.all;
 
package turbopack is
    constant RATE           : integer := 12;    -- code rate (e.g. 13 for rate 1/3)
    constant IT             : integer := 5;     -- number of decoding iterations
    constant FRSIZE         : integer := 64;    -- interleaver frame size in bit couples
    constant TREL1_LEN      : integer := 24;    -- first trellis length
    constant TREL2_LEN      : integer := 12;    -- second trellis length
    constant SIG_WIDTH      : integer := 4;     -- received decoder signal width
    constant Z_WIDTH        : integer := 5;     -- extrinsic information width
    constant ACC_DIST_WIDTH : integer := 9;     -- accumulated distance width
    subtype INT2BIT         is integer range 0 to 3;
    subtype INT3BIT         is integer range 0 to 7;
    subtype SUBINT0         is integer range -(2**(SIG_WIDTH-1)) - (2**Z_WIDTH) to 2**ACC_DIST_WIDTH + 2**(SIG_WIDTH-1) - 1;
    subtype SUBINT1         is integer range 0 to 2**ACC_DIST_WIDTH + 2**(SIG_WIDTH-1) + 2**(SIG_WIDTH-1) + 2**Z_WIDTH - 1;
    type ARRAY32a           is array (0 to 31)  of integer;
    type ARRAY32b           is array (0 to 31)  of std_logic_vector(ACC_DIST_WIDTH downto 0);
    type ARRAY32c           is array (0 to 31)  of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
    constant FROM2TO        : ARRAY32a := (0, 25,  6, 31,  8, 17, 14, 23, 20, 13, 18, 11, 28,  5, 26,  3,  4, 29,  2, 27, 12, 21, 10, 19, 16,  9, 22, 15, 24,  1, 30,  7);
    constant DISTINDEX      : ARRAY32a := (0,  7, 11, 12,  0,  7, 11, 12,  2,  5,  9, 14,  2,  5,  9, 14,  3,  4,  8, 15,  3,  4,  8, 15,  1,  6, 10, 13,  1,  6, 10, 13);
    constant TRANS2STATE    : ARRAY32a := (0,  6,  1,  7,  2,  4,  3,  5,  5,  3,  4,  2,  7,  1,  6,  0,  1,  7,  0,  6,  3,  5,  2,  4,  4,  2,  5,  3,  6,  0,  7,  1);
    constant STATE2TRANS    : ARRAY32a := (0,  2,  1,  3,  1,  3,  0,  2,  2,  0,  3,  1,  3,  1,  2,  0,  2,  0,  3,  1,  3,  1,  2,  0,  0,  2,  1,  3,  1,  3,  0,  2);
    type ARRAY2a            is array (0 to 1)   of std_logic_vector(SIG_WIDTH - 1 downto 0);
    type ARRAY3a            is array (0 to 2)   of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
    type ARRAY4a            is array (0 to 3)   of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
    type ARRAY4b            is array (0 to 3)   of std_logic_vector(ACC_DIST_WIDTH downto 0);
    type ARRAY4c            is array (0 to 3)   of std_logic_vector(Z_WIDTH - 1 downto 0);
    type ARRAY4d            is array (0 to 3)   of std_logic_vector(2 downto 0);
    type ARRAY4e            is array (0 to 3)   of SUBINT1;
    type ARRAY6a            is array (0 to 5)   of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
    type ARRAY6b            is array (0 to 5)   of INT2BIT;
    type ARRAY7a            is array (0 to 6)   of SUBINT0;
    type ARRAY8a            is array (0 to 7)   of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
    type ARRAY8b            is array (0 to 7)   of std_logic_vector(1 downto 0);
    type ARRAY8d            is array (0 to 7)   of INT3BIT;
    type ARRAY16a           is array (0 to 15)  of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
    type ARRAY16b           is array (0 to 15)  of std_logic_vector(SIG_WIDTH + 1 downto 0);
    type ARRAY_TREL1_LENx8  is array (0 to TREL1_LEN * 8 - 1) of INT2BIT;
    type ARRAY_TREL2_LENx8  is array (0 to TREL2_LEN * 8 - 1) of std_logic_vector(1 downto 0);
    type ARRAY_4xTREL2_LEN  is array (0 to 4 * TREL2_LEN - 1) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
    type ARRAY_ITa          is array (0 to IT) of std_logic_vector(SIG_WIDTH - 1 downto 0);
    type ARRAY_ITb          is array (0 to IT) of ARRAY4c;
 
    component delayer
        generic (
                delay   : integer := 1          -- number of clock cycles to delay
                );
        port    (
                clk     : in  std_logic;        -- clock
                rst     : in  std_logic;        -- negative reset
                d       : in  std_logic_vector; -- signal to be delayed by "delay" clock cycles
                q       : out std_logic_vector  -- delayed signal
                );
    end component;
 
    component subs
        port    (
                op1     : in  std_logic_vector; -- first operand
                op2     : in  std_logic_vector; -- second operand
                res     : out std_logic_vector  -- result of the substraction
                );
    end component;
 
    component mux4
        port    (
                in1     : in  std_logic_vector;             -- first input signal
                in2     : in  std_logic_vector;             -- second input signal
                in3     : in  std_logic_vector;             -- third input signal
                in4     : in  std_logic_vector;             -- fourth input signal
                sel     : in  std_logic_vector(1 downto 0); -- 2-bit control signal
                outSel  : out std_logic_vector              -- selected output signal
                );
    end component;
 
    component mux8
        port    (
                in8x4   : in  ARRAY32c; -- 8x4 input signals
                sel     : in  std_logic_vector(2 downto 0); -- 3-bit control signal
                outSel4 : out ARRAY4a   -- selected output signals
                );
    end component;
 
    component distances
        port    (
                a           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                b           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                y           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                w           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                z           : in  ARRAY4c;                                  -- extrinsic information array
                distance16  : out ARRAY16a                                  -- distance signals (x16)
                );
    end component;
 
    component partDistance
        generic (
                ref : integer := 0                                  -- reference to compute the distance from
                );
        port    (
                a   : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                b   : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                y   : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                w   : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                res : out std_logic_vector(SIG_WIDTH + 1 downto 0)  -- partial distance signal
                );
    end component;
 
    component opposite
        port    (
                pos : in  std_logic_vector(SIG_WIDTH + 1 downto 0); -- original number
                neg : out std_logic_vector(SIG_WIDTH + 1 downto 0)  -- opposite number
                );
    end component;
 
    component distance
        port    (
                partDist    : in  std_logic_vector(SIG_WIDTH + 1 downto 0);     -- sum of the decoder input signals
                z           : in  std_logic_vector(Z_WIDTH - 1 downto 0);       -- extrinsic information
                dist        : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0) -- distance
                );
    end component;
 
    component reg
        port    (
                clk     : in  std_logic;        -- clock
                rst     : in  std_logic;        -- negative reset
                d       : in  std_logic_vector; -- next value
                q       : out std_logic_vector  -- current value
                );
    end component;
 
    component adder
        port    (
                op1     : in  std_logic_vector; -- first operand
                op2     : in  std_logic_vector; -- second operand
                res     : out std_logic_vector  -- result of the addition
                );
    end component;
 
    component reduction
        port    (
                org : in  ARRAY8a;  -- original array of 8 accumulated distances
                chd : out ARRAY8a   -- reduced array of 8 accumulated distances
                );
    end component;
 
    component accDist
        port    (
                clk         : in  std_logic;    -- clock
                rst         : in  std_logic;    -- negative reset
                accDistReg  : in  ARRAY8a;      -- original array of 8 accumulated distance registers
                dist        : in  ARRAY16a;     -- array of 16 distances
                accDistNew  : out ARRAY32c      -- array of 32 accumulated distances
                );
    end component;
 
    component cmp2
        port    (
                op1     : in  std_logic_vector; -- first operand
                op2     : in  std_logic_vector; -- second operand
                res     : out std_logic         -- compare result (0 if op2 < op1, 1 otherwise)
                );
    end component;
 
    component mux2
        port    (
                in1     : in  std_logic_vector; -- first input signal
                in2     : in  std_logic_vector; -- second input signal
                sel     : in  std_logic;        -- 1-bit control signal
                outSel  : out std_logic_vector  -- selected output signal
                );
    end component;
 
    component min4
        port    (
                op1     : in  std_logic_vector; -- first input signal
                op2     : in  std_logic_vector; -- second input signal
                op3     : in  std_logic_vector; -- third input signal
                op4     : in  std_logic_vector; -- fourth input signal
                res1    : out std_logic;        -- partial code of the minimum value
                res2    : out std_logic;        -- partial code of the minimum value
                res3    : out std_logic         -- partial code of the minimum value
                );
    end component;
 
    component accDistSel
        port    (
                accDist     : in  ARRAY32c; -- array of 32 accumulated distances
                accDistCod  : out ARRAY8b;  -- array of 8 2-bit selection signals
                accDistOut  : out ARRAY8a   -- array of 8 selected accumulated distances
                );
    end component;
 
    component cod2
        port    (
                in1     : in  std_logic;                    -- 1-bit first input signal
                in2     : in  std_logic;                    -- 1-bit second input signal
                in3     : in  std_logic;                    -- 1-bit third input signal
                outCod  : out std_logic_vector(1 downto 0)  -- 2-bit coded value
                );
    end component;
 
    component min8
        port    (
                op  : in  ARRAY8a;                      -- input signals
                res : out std_logic_vector(6 downto 0)  -- code of the minimum value
                );
    end component;
 
    component cod3
        port    (
                inSig   : in  std_logic_vector(6 downto 0); -- 7 1-bit input signals
                outCod  : out std_logic_vector(2 downto 0)  -- 3-bit coded value
                );
    end component;
 
    component stateSel
        port    (
                stateDist   : in ARRAY8a;                       -- state accumulated distance
                selState    : out std_logic_vector(2 downto 0)  -- selected state code
                );
    end component;
 
    component acs
        port    (
                clk         : in  std_logic;                            -- clock
                rst         : in  std_logic;                            -- negative reset
                a           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                b           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                y           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                w           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                z           : in  ARRAY4c;                              -- extrinsic information array
                selStateL   : in  std_logic_vector(2 downto 0);         -- selected state at t = L
                selTransL   : in  std_logic_vector(1 downto 0);         -- selected transition at selStateL
                selState    : out std_logic_vector(2 downto 0);         -- selected state
                stateDist   : out ARRAY8b;                              -- selected accumulated distances (per state)
                weight      : out ARRAY4a                               -- four weights sorted by transition code
                );
    end component;
 
    component trellis1
        port    (
                clk         : in  std_logic;                    -- clock
                rst         : in  std_logic;                    -- negative reset
                selState    : in  std_logic_vector(2 downto 0); -- selected state at time 0
                selTrans    : in  ARRAY8b;                      -- 8 selected transitions (1 per state) at time 0
                selStateL2  : out std_logic_vector(2 downto 0); -- selected state at time (l - 2)
                selStateL1  : out std_logic_vector(2 downto 0); -- selected state at time (l - 1)
                stateL1     : out ARRAY4d;                      -- 4 possible states at time (l - 1)
                selTransL2  : out std_logic_vector(1 downto 0)  -- selected transition at time (l - 2)
                );
    end component;
 
    component trellis2
        port    (
                clk         : in  std_logic;                    -- clock
                rst         : in  std_logic;                    -- negative reset
                selState    : in  std_logic_vector(2 downto 0); -- selected state at time (l - 1)
                state       : in  ARRAY4d;                      -- 4 possible states at time (l - 1)
                selTrans    : in  ARRAY8b;                      -- 8 selected transitions (1 per state) at time (l - 1)
                weight      : in  ARRAY4a;                      -- four weights sorted by transition code at time (l - 1)
                llr0        : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (0, 0) at time (l + m - 1)
                llr1        : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (0, 1) at time (l + m - 1)
                llr2        : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (1, 0) at time (l + m - 1)
                llr3        : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (1, 1) at time (l + m - 1)
                a           : out std_logic;                    -- decoded value of a at time (l + m - 1)
                b           : out std_logic                     -- decoded value of b at time (l + m - 1)
                );
    end component;
 
    component extInf
        port    (
                llr0    : in  std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (0, 0)
                llr1    : in  std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (0, 1)
                llr2    : in  std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (1, 0)
                llr3    : in  std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (1, 1)
                zin     : in  ARRAY4c;                                          -- extrinsic information input signal
                a       : in  std_logic_vector(SIG_WIDTH - 1 downto 0);         -- decoder systematic input signal
                b       : in  std_logic_vector(SIG_WIDTH - 1 downto 0);         -- decoder systematic input signal
                zout    : out ARRAY4c                                           -- extrinsic information output signal
                );
    end component;
 
    component sova
        port    (
                clk     : in  std_logic;                                -- clock
                rst     : in  std_logic;                                -- negative reset
                aNoisy  : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                bNoisy  : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                yNoisy  : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                wNoisy  : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                zin     : in  ARRAY4c;                                  -- extrinsic information input
                zout    : out ARRAY4c;                                  -- extrinsic information output
                aClean  : out std_logic;                                -- decoded systematic data
                bClean  : out std_logic                                 -- decoded systematic data
                );
    end component;
 
    component zPermut
        generic (
                flip        : integer := 0      -- initialisation (permutation on/off)
                );
        port    (
                flipflop    : in  std_logic;    -- permutation control signal (on/off)
                z           : in  ARRAY4c;      -- original extrinsic information
                zPerm       : out ARRAY4c       -- permuted extrinsic information
                );
    end component;
 
    component interleaver
        generic (
                delay       : integer := 0;     -- number of clock cycles to wait before starting the (de)interleaver
                way         : integer := 0      -- 0 for interleaving, 1 for deinterleaving
                );
        port    (
                clk         : in  std_logic;        -- clock
                rst         : in  std_logic;        -- negative reset
                d           : in  std_logic_vector; -- input data
                q           : out std_logic_vector  -- interleaved data
                );
    end component;
 
    component abPermut
        generic (
                flip        : integer := 0                                  -- initialisation (permutation on/off)
                );
        port    (
                flipflop    : in  std_logic;                                -- permutation control signal (on/off)
                a           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
                b           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
                abPerm      : out ARRAY2a                                   -- permuted systematic information
                );
    end component;
 
    component iteration
        generic (
                delay       : integer := 0                                  -- additional delay created by the previous iterations
                );
        port    (
                clk         : in  std_logic;                                -- clock
                rst         : in  std_logic;                                -- negative reset
                flipflop    : in  std_logic;                                -- permutation control signal (on/off)
                a           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                b           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                y           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                w           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                yInt        : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                wInt        : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                zin         : in  ARRAY4c;                                  -- extrinsic information from the previous iteration
                zout        : out ARRAY4c;                                  -- extrinsic information to the next iteration
                aDec        : out std_logic;                                -- decoded signal
                bDec        : out std_logic;                                -- decoded signal
                aDel        : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                bDel        : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                yDel        : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                wDel        : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                yIntDel     : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                wIntDel     : out std_logic_vector(SIG_WIDTH - 1 downto 0)  -- delayed received decoder signal
                );
    end component;
 
    component clkDiv
        port    (
                clk     : in  std_logic;    -- clock
                rst     : in  std_logic;    -- negative reset
                clkout  : out std_logic     -- clock which frequency is half of the input clock
                );
    end component;
 
    component limiter
        port    (
                a       : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                b       : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                y       : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                w       : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                yInt    : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                wInt    : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                aLim    : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                bLim    : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                yLim    : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                wLim    : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                yIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                wIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0)  -- limited signal
                );
    end component;
 
    component punct
        port    (
                clk         : in  std_logic;                                -- clock
                rst         : in  std_logic;                                -- negative reset
                y           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
                w           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
                yInt        : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
                wInt        : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
                yPunct      : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
                wPunct      : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
                yIntPunct   : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
                wIntPunct   : out std_logic_vector(SIG_WIDTH - 1 downto 0)  -- punctured data
                );
    end component;
end;

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[/] [turbocodes/] [trunk/] [src/] [vhdl/] [turbopack.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	dbrochart	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- turbopack.vhd ----`
4			`---- ----`
5			`---- This file is part of the turbo decoder IP core project ----`
6			`---- http://www.opencores.org/projects/turbocodes/ ----`
7			`---- ----`
8			`---- Author(s): ----`
9			`---- - David Brochart(dbrochart@opencores.org) ----`
10			`---- ----`
11			`---- All additional information is available in the README.txt ----`
12			`---- file. ----`
13			`---- ----`
14			`----------------------------------------------------------------------`
15			`---- ----`
16			`---- Copyright (C) 2005 Authors ----`
17			`---- ----`
18			`---- This source file may be used and distributed without ----`
19			`---- restriction provided that this copyright statement is not ----`
20			`---- removed from the file and that any derivative work contains ----`
21			`---- the original copyright notice and the associated disclaimer. ----`
22			`---- ----`
23			`---- This source file is free software; you can redistribute it ----`
24			`---- and/or modify it under the terms of the GNU Lesser General ----`
25			`---- Public License as published by the Free Software Foundation; ----`
26			`---- either version 2.1 of the License, or (at your option) any ----`
27			`---- later version. ----`
28			`---- ----`
29			`---- This source is distributed in the hope that it will be ----`
30			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
31			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
32			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
33			`---- details. ----`
34			`---- ----`
35			`---- You should have received a copy of the GNU Lesser General ----`
36			`---- Public License along with this source; if not, download it ----`
37			`---- from http://www.opencores.org/lgpl.shtml ----`
38			`---- ----`
39			`----------------------------------------------------------------------`
40
41
42
43			`library ieee;`
44			`use ieee.std_logic_1164.all;`
45
46			`package turbopack is`
47			`constant RATE : integer := 12; -- code rate (e.g. 13 for rate 1/3)`
48			`constant IT : integer := 5; -- number of decoding iterations`
49			`constant FRSIZE : integer := 64; -- interleaver frame size in bit couples`
50			`constant TREL1_LEN : integer := 24; -- first trellis length`
51			`constant TREL2_LEN : integer := 12; -- second trellis length`
52			`constant SIG_WIDTH : integer := 4; -- received decoder signal width`
53			`constant Z_WIDTH : integer := 5; -- extrinsic information width`
54			`constant ACC_DIST_WIDTH : integer := 9; -- accumulated distance width`
55			`subtype INT2BIT is integer range 0 to 3;`
56			`subtype INT3BIT is integer range 0 to 7;`
57			`subtype SUBINT0 is integer range -(2(SIG_WIDTH-1)) - (2Z_WIDTH) to 2ACC_DIST_WIDTH + 2(SIG_WIDTH-1) - 1;`
58			`subtype SUBINT1 is integer range 0 to 2ACC_DIST_WIDTH + 2(SIG_WIDTH-1) + 2(SIG_WIDTH-1) + 2Z_WIDTH - 1;`
59			`type ARRAY32a is array (0 to 31) of integer;`
60			`type ARRAY32b is array (0 to 31) of std_logic_vector(ACC_DIST_WIDTH downto 0);`
61			`type ARRAY32c is array (0 to 31) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);`
62			`constant FROM2TO : ARRAY32a := (0, 25, 6, 31, 8, 17, 14, 23, 20, 13, 18, 11, 28, 5, 26, 3, 4, 29, 2, 27, 12, 21, 10, 19, 16, 9, 22, 15, 24, 1, 30, 7);`
63			`constant DISTINDEX : ARRAY32a := (0, 7, 11, 12, 0, 7, 11, 12, 2, 5, 9, 14, 2, 5, 9, 14, 3, 4, 8, 15, 3, 4, 8, 15, 1, 6, 10, 13, 1, 6, 10, 13);`
64			`constant TRANS2STATE : ARRAY32a := (0, 6, 1, 7, 2, 4, 3, 5, 5, 3, 4, 2, 7, 1, 6, 0, 1, 7, 0, 6, 3, 5, 2, 4, 4, 2, 5, 3, 6, 0, 7, 1);`
65			`constant STATE2TRANS : ARRAY32a := (0, 2, 1, 3, 1, 3, 0, 2, 2, 0, 3, 1, 3, 1, 2, 0, 2, 0, 3, 1, 3, 1, 2, 0, 0, 2, 1, 3, 1, 3, 0, 2);`
66			`type ARRAY2a is array (0 to 1) of std_logic_vector(SIG_WIDTH - 1 downto 0);`
67			`type ARRAY3a is array (0 to 2) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);`
68			`type ARRAY4a is array (0 to 3) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);`
69			`type ARRAY4b is array (0 to 3) of std_logic_vector(ACC_DIST_WIDTH downto 0);`
70			`type ARRAY4c is array (0 to 3) of std_logic_vector(Z_WIDTH - 1 downto 0);`
71			`type ARRAY4d is array (0 to 3) of std_logic_vector(2 downto 0);`
72			`type ARRAY4e is array (0 to 3) of SUBINT1;`
73			`type ARRAY6a is array (0 to 5) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);`
74			`type ARRAY6b is array (0 to 5) of INT2BIT;`
75			`type ARRAY7a is array (0 to 6) of SUBINT0;`
76			`type ARRAY8a is array (0 to 7) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);`
77			`type ARRAY8b is array (0 to 7) of std_logic_vector(1 downto 0);`
78			`type ARRAY8d is array (0 to 7) of INT3BIT;`
79			`type ARRAY16a is array (0 to 15) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);`
80			`type ARRAY16b is array (0 to 15) of std_logic_vector(SIG_WIDTH + 1 downto 0);`
81			`type ARRAY_TREL1_LENx8 is array (0 to TREL1_LEN * 8 - 1) of INT2BIT;`
82			`type ARRAY_TREL2_LENx8 is array (0 to TREL2_LEN * 8 - 1) of std_logic_vector(1 downto 0);`
83			`type ARRAY_4xTREL2_LEN is array (0 to 4 * TREL2_LEN - 1) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);`
84			`type ARRAY_ITa is array (0 to IT) of std_logic_vector(SIG_WIDTH - 1 downto 0);`
85			`type ARRAY_ITb is array (0 to IT) of ARRAY4c;`
86
87			`component delayer`
88			`generic (`
89			`delay : integer := 1 -- number of clock cycles to delay`
90			`);`
91			`port (`
92			`clk : in std_logic; -- clock`
93			`rst : in std_logic; -- negative reset`
94			`d : in std_logic_vector; -- signal to be delayed by "delay" clock cycles`
95			`q : out std_logic_vector -- delayed signal`
96			`);`
97			`end component;`
98
99			`component subs`
100			`port (`
101			`op1 : in std_logic_vector; -- first operand`
102			`op2 : in std_logic_vector; -- second operand`
103			`res : out std_logic_vector -- result of the substraction`
104			`);`
105			`end component;`
106
107			`component mux4`
108			`port (`
109			`in1 : in std_logic_vector; -- first input signal`
110			`in2 : in std_logic_vector; -- second input signal`
111			`in3 : in std_logic_vector; -- third input signal`
112			`in4 : in std_logic_vector; -- fourth input signal`
113			`sel : in std_logic_vector(1 downto 0); -- 2-bit control signal`
114			`outSel : out std_logic_vector -- selected output signal`
115			`);`
116			`end component;`
117
118			`component mux8`
119			`port (`
120			`in8x4 : in ARRAY32c; -- 8x4 input signals`
121			`sel : in std_logic_vector(2 downto 0); -- 3-bit control signal`
122			`outSel4 : out ARRAY4a -- selected output signals`
123			`);`
124			`end component;`
125
126			`component distances`
127			`port (`
128			`a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
129			`b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
130			`y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
131			`w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
132			`z : in ARRAY4c; -- extrinsic information array`
133			`distance16 : out ARRAY16a -- distance signals (x16)`
134			`);`
135			`end component;`
136
137			`component partDistance`
138			`generic (`
139			`ref : integer := 0 -- reference to compute the distance from`
140			`);`
141			`port (`
142			`a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
143			`b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
144			`y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
145			`w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
146			`res : out std_logic_vector(SIG_WIDTH + 1 downto 0) -- partial distance signal`
147			`);`
148			`end component;`
149
150			`component opposite`
151			`port (`
152			`pos : in std_logic_vector(SIG_WIDTH + 1 downto 0); -- original number`
153			`neg : out std_logic_vector(SIG_WIDTH + 1 downto 0) -- opposite number`
154			`);`
155			`end component;`
156
157			`component distance`
158			`port (`
159			`partDist : in std_logic_vector(SIG_WIDTH + 1 downto 0); -- sum of the decoder input signals`
160			`z : in std_logic_vector(Z_WIDTH - 1 downto 0); -- extrinsic information`
161			`dist : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0) -- distance`
162			`);`
163			`end component;`
164
165			`component reg`
166			`port (`
167			`clk : in std_logic; -- clock`
168			`rst : in std_logic; -- negative reset`
169			`d : in std_logic_vector; -- next value`
170			`q : out std_logic_vector -- current value`
171			`);`
172			`end component;`
173
174			`component adder`
175			`port (`
176			`op1 : in std_logic_vector; -- first operand`
177			`op2 : in std_logic_vector; -- second operand`
178			`res : out std_logic_vector -- result of the addition`
179			`);`
180			`end component;`
181
182			`component reduction`
183			`port (`
184			`org : in ARRAY8a; -- original array of 8 accumulated distances`
185			`chd : out ARRAY8a -- reduced array of 8 accumulated distances`
186			`);`
187			`end component;`
188
189			`component accDist`
190			`port (`
191			`clk : in std_logic; -- clock`
192			`rst : in std_logic; -- negative reset`
193			`accDistReg : in ARRAY8a; -- original array of 8 accumulated distance registers`
194			`dist : in ARRAY16a; -- array of 16 distances`
195			`accDistNew : out ARRAY32c -- array of 32 accumulated distances`
196			`);`
197			`end component;`
198
199			`component cmp2`
200			`port (`
201			`op1 : in std_logic_vector; -- first operand`
202			`op2 : in std_logic_vector; -- second operand`
203			`res : out std_logic -- compare result (0 if op2 < op1, 1 otherwise)`
204			`);`
205			`end component;`
206
207			`component mux2`
208			`port (`
209			`in1 : in std_logic_vector; -- first input signal`
210			`in2 : in std_logic_vector; -- second input signal`
211			`sel : in std_logic; -- 1-bit control signal`
212			`outSel : out std_logic_vector -- selected output signal`
213			`);`
214			`end component;`
215
216			`component min4`
217			`port (`
218			`op1 : in std_logic_vector; -- first input signal`
219			`op2 : in std_logic_vector; -- second input signal`
220			`op3 : in std_logic_vector; -- third input signal`
221			`op4 : in std_logic_vector; -- fourth input signal`
222			`res1 : out std_logic; -- partial code of the minimum value`
223			`res2 : out std_logic; -- partial code of the minimum value`
224			`res3 : out std_logic -- partial code of the minimum value`
225			`);`
226			`end component;`
227
228			`component accDistSel`
229			`port (`
230			`accDist : in ARRAY32c; -- array of 32 accumulated distances`
231			`accDistCod : out ARRAY8b; -- array of 8 2-bit selection signals`
232			`accDistOut : out ARRAY8a -- array of 8 selected accumulated distances`
233			`);`
234			`end component;`
235
236			`component cod2`
237			`port (`
238			`in1 : in std_logic; -- 1-bit first input signal`
239			`in2 : in std_logic; -- 1-bit second input signal`
240			`in3 : in std_logic; -- 1-bit third input signal`
241			`outCod : out std_logic_vector(1 downto 0) -- 2-bit coded value`
242			`);`
243			`end component;`
244
245			`component min8`
246			`port (`
247			`op : in ARRAY8a; -- input signals`
248			`res : out std_logic_vector(6 downto 0) -- code of the minimum value`
249			`);`
250			`end component;`
251
252			`component cod3`
253			`port (`
254			`inSig : in std_logic_vector(6 downto 0); -- 7 1-bit input signals`
255			`outCod : out std_logic_vector(2 downto 0) -- 3-bit coded value`
256			`);`
257			`end component;`
258
259			`component stateSel`
260			`port (`
261			`stateDist : in ARRAY8a; -- state accumulated distance`
262			`selState : out std_logic_vector(2 downto 0) -- selected state code`
263			`);`
264			`end component;`
265
266			`component acs`
267			`port (`
268			`clk : in std_logic; -- clock`
269			`rst : in std_logic; -- negative reset`
270			`a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
271			`b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
272			`y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
273			`w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
274			`z : in ARRAY4c; -- extrinsic information array`
275			`selStateL : in std_logic_vector(2 downto 0); -- selected state at t = L`
276			`selTransL : in std_logic_vector(1 downto 0); -- selected transition at selStateL`
277			`selState : out std_logic_vector(2 downto 0); -- selected state`
278			`stateDist : out ARRAY8b; -- selected accumulated distances (per state)`
279			`weight : out ARRAY4a -- four weights sorted by transition code`
280			`);`
281			`end component;`
282
283			`component trellis1`
284			`port (`
285			`clk : in std_logic; -- clock`
286			`rst : in std_logic; -- negative reset`
287			`selState : in std_logic_vector(2 downto 0); -- selected state at time 0`
288			`selTrans : in ARRAY8b; -- 8 selected transitions (1 per state) at time 0`
289			`selStateL2 : out std_logic_vector(2 downto 0); -- selected state at time (l - 2)`
290			`selStateL1 : out std_logic_vector(2 downto 0); -- selected state at time (l - 1)`
291			`stateL1 : out ARRAY4d; -- 4 possible states at time (l - 1)`
292			`selTransL2 : out std_logic_vector(1 downto 0) -- selected transition at time (l - 2)`
293			`);`
294			`end component;`
295
296			`component trellis2`
297			`port (`
298			`clk : in std_logic; -- clock`
299			`rst : in std_logic; -- negative reset`
300			`selState : in std_logic_vector(2 downto 0); -- selected state at time (l - 1)`
301			`state : in ARRAY4d; -- 4 possible states at time (l - 1)`
302			`selTrans : in ARRAY8b; -- 8 selected transitions (1 per state) at time (l - 1)`
303			`weight : in ARRAY4a; -- four weights sorted by transition code at time (l - 1)`
304			`llr0 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 0) at time (l + m - 1)`
305			`llr1 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 1) at time (l + m - 1)`
306			`llr2 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 0) at time (l + m - 1)`
307			`llr3 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 1) at time (l + m - 1)`
308			`a : out std_logic; -- decoded value of a at time (l + m - 1)`
309			`b : out std_logic -- decoded value of b at time (l + m - 1)`
310			`);`
311			`end component;`
312
313			`component extInf`
314			`port (`
315			`llr0 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 0)`
316			`llr1 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 1)`
317			`llr2 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 0)`
318			`llr3 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 1)`
319			`zin : in ARRAY4c; -- extrinsic information input signal`
320			`a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder systematic input signal`
321			`b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder systematic input signal`
322			`zout : out ARRAY4c -- extrinsic information output signal`
323			`);`
324			`end component;`
325
326			`component sova`
327			`port (`
328			`clk : in std_logic; -- clock`
329			`rst : in std_logic; -- negative reset`
330			`aNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
331			`bNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
332			`yNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
333			`wNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
334			`zin : in ARRAY4c; -- extrinsic information input`
335			`zout : out ARRAY4c; -- extrinsic information output`
336			`aClean : out std_logic; -- decoded systematic data`
337			`bClean : out std_logic -- decoded systematic data`
338			`);`
339			`end component;`
340
341			`component zPermut`
342			`generic (`
343			`flip : integer := 0 -- initialisation (permutation on/off)`
344			`);`
345			`port (`
346			`flipflop : in std_logic; -- permutation control signal (on/off)`
347			`z : in ARRAY4c; -- original extrinsic information`
348			`zPerm : out ARRAY4c -- permuted extrinsic information`
349			`);`
350			`end component;`
351
352			`component interleaver`
353			`generic (`
354			`delay : integer := 0; -- number of clock cycles to wait before starting the (de)interleaver`
355			`way : integer := 0 -- 0 for interleaving, 1 for deinterleaving`
356			`);`
357			`port (`
358			`clk : in std_logic; -- clock`
359			`rst : in std_logic; -- negative reset`
360			`d : in std_logic_vector; -- input data`
361			`q : out std_logic_vector -- interleaved data`
362			`);`
363			`end component;`
364
365			`component abPermut`
366			`generic (`
367			`flip : integer := 0 -- initialisation (permutation on/off)`
368			`);`
369			`port (`
370			`flipflop : in std_logic; -- permutation control signal (on/off)`
371			`a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information`
372			`b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information`
373			`abPerm : out ARRAY2a -- permuted systematic information`
374			`);`
375			`end component;`
376
377			`component iteration`
378			`generic (`
379			`delay : integer := 0 -- additional delay created by the previous iterations`
380			`);`
381			`port (`
382			`clk : in std_logic; -- clock`
383			`rst : in std_logic; -- negative reset`
384			`flipflop : in std_logic; -- permutation control signal (on/off)`
385			`a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
386			`b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
387			`y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
388			`w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
389			`yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
390			`wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal`
391			`zin : in ARRAY4c; -- extrinsic information from the previous iteration`
392			`zout : out ARRAY4c; -- extrinsic information to the next iteration`
393			`aDec : out std_logic; -- decoded signal`
394			`bDec : out std_logic; -- decoded signal`
395			`aDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal`
396			`bDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal`
397			`yDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal`
398			`wDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal`
399			`yIntDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal`
400			`wIntDel : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- delayed received decoder signal`
401			`);`
402			`end component;`
403
404			`component clkDiv`
405			`port (`
406			`clk : in std_logic; -- clock`
407			`rst : in std_logic; -- negative reset`
408			`clkout : out std_logic -- clock which frequency is half of the input clock`
409			`);`
410			`end component;`
411
412			`component limiter`
413			`port (`
414			`a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal`
415			`b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal`
416			`y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal`
417			`w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal`
418			`yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal`
419			`wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal`
420			`aLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal`
421			`bLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal`
422			`yLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal`
423			`wLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal`
424			`yIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal`
425			`wIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- limited signal`
426			`);`
427			`end component;`
428
429			`component punct`
430			`port (`
431			`clk : in std_logic; -- clock`
432			`rst : in std_logic; -- negative reset`
433			`y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data`
434			`w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data`
435			`yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data`
436			`wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data`
437			`yPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data`
438			`wPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data`
439			`yIntPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data`
440			`wIntPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- punctured data`
441			`);`
442			`end component;`
443			`end;`