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dbrochart |
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---- ----
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---- turbopack.vhd ----
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---- ----
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---- This file is part of the turbo decoder IP core project ----
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---- http://www.opencores.org/projects/turbocodes/ ----
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---- ----
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---- Author(s): ----
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---- - David Brochart(dbrochart@opencores.org) ----
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---- ----
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---- All additional information is available in the README.txt ----
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---- file. ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package turbopack is
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constant RATE : integer := 12; -- code rate (e.g. 13 for rate 1/3)
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constant IT : integer := 5; -- number of decoding iterations
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constant FRSIZE : integer := 64; -- interleaver frame size in bit couples
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constant TREL1_LEN : integer := 24; -- first trellis length
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constant TREL2_LEN : integer := 12; -- second trellis length
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constant SIG_WIDTH : integer := 4; -- received decoder signal width
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constant Z_WIDTH : integer := 5; -- extrinsic information width
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constant ACC_DIST_WIDTH : integer := 9; -- accumulated distance width
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subtype INT2BIT is integer range 0 to 3;
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subtype INT3BIT is integer range 0 to 7;
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subtype SUBINT0 is integer range -(2**(SIG_WIDTH-1)) - (2**Z_WIDTH) to 2**ACC_DIST_WIDTH + 2**(SIG_WIDTH-1) - 1;
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subtype SUBINT1 is integer range 0 to 2**ACC_DIST_WIDTH + 2**(SIG_WIDTH-1) + 2**(SIG_WIDTH-1) + 2**Z_WIDTH - 1;
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type ARRAY32a is array (0 to 31) of integer;
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type ARRAY32b is array (0 to 31) of std_logic_vector(ACC_DIST_WIDTH downto 0);
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type ARRAY32c is array (0 to 31) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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constant FROM2TO : ARRAY32a := (0, 25, 6, 31, 8, 17, 14, 23, 20, 13, 18, 11, 28, 5, 26, 3, 4, 29, 2, 27, 12, 21, 10, 19, 16, 9, 22, 15, 24, 1, 30, 7);
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constant DISTINDEX : ARRAY32a := (0, 7, 11, 12, 0, 7, 11, 12, 2, 5, 9, 14, 2, 5, 9, 14, 3, 4, 8, 15, 3, 4, 8, 15, 1, 6, 10, 13, 1, 6, 10, 13);
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constant TRANS2STATE : ARRAY32a := (0, 6, 1, 7, 2, 4, 3, 5, 5, 3, 4, 2, 7, 1, 6, 0, 1, 7, 0, 6, 3, 5, 2, 4, 4, 2, 5, 3, 6, 0, 7, 1);
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constant STATE2TRANS : ARRAY32a := (0, 2, 1, 3, 1, 3, 0, 2, 2, 0, 3, 1, 3, 1, 2, 0, 2, 0, 3, 1, 3, 1, 2, 0, 0, 2, 1, 3, 1, 3, 0, 2);
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type ARRAY2a is array (0 to 1) of std_logic_vector(SIG_WIDTH - 1 downto 0);
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type ARRAY3a is array (0 to 2) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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type ARRAY4a is array (0 to 3) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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type ARRAY4b is array (0 to 3) of std_logic_vector(ACC_DIST_WIDTH downto 0);
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type ARRAY4c is array (0 to 3) of std_logic_vector(Z_WIDTH - 1 downto 0);
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type ARRAY4d is array (0 to 3) of std_logic_vector(2 downto 0);
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type ARRAY4e is array (0 to 3) of SUBINT1;
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type ARRAY6a is array (0 to 5) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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type ARRAY6b is array (0 to 5) of INT2BIT;
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type ARRAY7a is array (0 to 6) of SUBINT0;
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type ARRAY8a is array (0 to 7) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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type ARRAY8b is array (0 to 7) of std_logic_vector(1 downto 0);
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type ARRAY8d is array (0 to 7) of INT3BIT;
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type ARRAY16a is array (0 to 15) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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type ARRAY16b is array (0 to 15) of std_logic_vector(SIG_WIDTH + 1 downto 0);
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type ARRAY_TREL1_LENx8 is array (0 to TREL1_LEN * 8 - 1) of INT2BIT;
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type ARRAY_TREL2_LENx8 is array (0 to TREL2_LEN * 8 - 1) of std_logic_vector(1 downto 0);
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type ARRAY_4xTREL2_LEN is array (0 to 4 * TREL2_LEN - 1) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
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type ARRAY_ITa is array (0 to IT) of std_logic_vector(SIG_WIDTH - 1 downto 0);
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type ARRAY_ITb is array (0 to IT) of ARRAY4c;
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component delayer
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generic (
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delay : integer := 1 -- number of clock cycles to delay
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);
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port (
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clk : in std_logic; -- clock
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rst : in std_logic; -- negative reset
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d : in std_logic_vector; -- signal to be delayed by "delay" clock cycles
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q : out std_logic_vector -- delayed signal
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);
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end component;
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component subs
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port (
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op1 : in std_logic_vector; -- first operand
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op2 : in std_logic_vector; -- second operand
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res : out std_logic_vector -- result of the substraction
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);
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end component;
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component mux4
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port (
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in1 : in std_logic_vector; -- first input signal
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in2 : in std_logic_vector; -- second input signal
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in3 : in std_logic_vector; -- third input signal
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in4 : in std_logic_vector; -- fourth input signal
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sel : in std_logic_vector(1 downto 0); -- 2-bit control signal
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outSel : out std_logic_vector -- selected output signal
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);
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end component;
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component mux8
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port (
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in8x4 : in ARRAY32c; -- 8x4 input signals
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sel : in std_logic_vector(2 downto 0); -- 3-bit control signal
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outSel4 : out ARRAY4a -- selected output signals
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);
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end component;
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component distances
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port (
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a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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z : in ARRAY4c; -- extrinsic information array
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distance16 : out ARRAY16a -- distance signals (x16)
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);
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end component;
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component partDistance
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generic (
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ref : integer := 0 -- reference to compute the distance from
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);
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port (
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a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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res : out std_logic_vector(SIG_WIDTH + 1 downto 0) -- partial distance signal
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);
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end component;
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component opposite
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port (
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pos : in std_logic_vector(SIG_WIDTH + 1 downto 0); -- original number
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neg : out std_logic_vector(SIG_WIDTH + 1 downto 0) -- opposite number
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);
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end component;
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component distance
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port (
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partDist : in std_logic_vector(SIG_WIDTH + 1 downto 0); -- sum of the decoder input signals
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z : in std_logic_vector(Z_WIDTH - 1 downto 0); -- extrinsic information
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dist : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0) -- distance
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);
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end component;
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component reg
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port (
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clk : in std_logic; -- clock
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rst : in std_logic; -- negative reset
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d : in std_logic_vector; -- next value
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q : out std_logic_vector -- current value
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);
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end component;
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component adder
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port (
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op1 : in std_logic_vector; -- first operand
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op2 : in std_logic_vector; -- second operand
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res : out std_logic_vector -- result of the addition
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);
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end component;
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component reduction
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port (
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org : in ARRAY8a; -- original array of 8 accumulated distances
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chd : out ARRAY8a -- reduced array of 8 accumulated distances
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);
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end component;
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component accDist
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port (
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clk : in std_logic; -- clock
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rst : in std_logic; -- negative reset
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accDistReg : in ARRAY8a; -- original array of 8 accumulated distance registers
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dist : in ARRAY16a; -- array of 16 distances
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accDistNew : out ARRAY32c -- array of 32 accumulated distances
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);
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end component;
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component cmp2
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port (
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op1 : in std_logic_vector; -- first operand
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op2 : in std_logic_vector; -- second operand
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res : out std_logic -- compare result (0 if op2 < op1, 1 otherwise)
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);
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end component;
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component mux2
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port (
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in1 : in std_logic_vector; -- first input signal
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in2 : in std_logic_vector; -- second input signal
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sel : in std_logic; -- 1-bit control signal
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outSel : out std_logic_vector -- selected output signal
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);
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end component;
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component min4
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port (
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op1 : in std_logic_vector; -- first input signal
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op2 : in std_logic_vector; -- second input signal
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op3 : in std_logic_vector; -- third input signal
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op4 : in std_logic_vector; -- fourth input signal
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res1 : out std_logic; -- partial code of the minimum value
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res2 : out std_logic; -- partial code of the minimum value
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res3 : out std_logic -- partial code of the minimum value
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);
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end component;
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component accDistSel
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port (
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accDist : in ARRAY32c; -- array of 32 accumulated distances
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accDistCod : out ARRAY8b; -- array of 8 2-bit selection signals
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accDistOut : out ARRAY8a -- array of 8 selected accumulated distances
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);
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end component;
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component cod2
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port (
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in1 : in std_logic; -- 1-bit first input signal
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in2 : in std_logic; -- 1-bit second input signal
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in3 : in std_logic; -- 1-bit third input signal
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outCod : out std_logic_vector(1 downto 0) -- 2-bit coded value
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);
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end component;
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component min8
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port (
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op : in ARRAY8a; -- input signals
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res : out std_logic_vector(6 downto 0) -- code of the minimum value
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);
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end component;
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component cod3
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port (
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inSig : in std_logic_vector(6 downto 0); -- 7 1-bit input signals
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outCod : out std_logic_vector(2 downto 0) -- 3-bit coded value
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);
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end component;
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component stateSel
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port (
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stateDist : in ARRAY8a; -- state accumulated distance
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selState : out std_logic_vector(2 downto 0) -- selected state code
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);
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end component;
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component acs
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port (
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clk : in std_logic; -- clock
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rst : in std_logic; -- negative reset
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a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
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z : in ARRAY4c; -- extrinsic information array
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selStateL : in std_logic_vector(2 downto 0); -- selected state at t = L
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selTransL : in std_logic_vector(1 downto 0); -- selected transition at selStateL
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selState : out std_logic_vector(2 downto 0); -- selected state
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stateDist : out ARRAY8b; -- selected accumulated distances (per state)
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weight : out ARRAY4a -- four weights sorted by transition code
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);
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end component;
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component trellis1
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port (
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clk : in std_logic; -- clock
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rst : in std_logic; -- negative reset
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selState : in std_logic_vector(2 downto 0); -- selected state at time 0
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selTrans : in ARRAY8b; -- 8 selected transitions (1 per state) at time 0
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selStateL2 : out std_logic_vector(2 downto 0); -- selected state at time (l - 2)
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selStateL1 : out std_logic_vector(2 downto 0); -- selected state at time (l - 1)
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stateL1 : out ARRAY4d; -- 4 possible states at time (l - 1)
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selTransL2 : out std_logic_vector(1 downto 0) -- selected transition at time (l - 2)
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);
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end component;
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component trellis2
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port (
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clk : in std_logic; -- clock
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rst : in std_logic; -- negative reset
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selState : in std_logic_vector(2 downto 0); -- selected state at time (l - 1)
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state : in ARRAY4d; -- 4 possible states at time (l - 1)
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selTrans : in ARRAY8b; -- 8 selected transitions (1 per state) at time (l - 1)
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weight : in ARRAY4a; -- four weights sorted by transition code at time (l - 1)
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llr0 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 0) at time (l + m - 1)
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llr1 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 1) at time (l + m - 1)
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llr2 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 0) at time (l + m - 1)
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llr3 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 1) at time (l + m - 1)
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a : out std_logic; -- decoded value of a at time (l + m - 1)
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|
|
b : out std_logic -- decoded value of b at time (l + m - 1)
|
310 |
|
|
);
|
311 |
|
|
end component;
|
312 |
|
|
|
313 |
|
|
component extInf
|
314 |
|
|
port (
|
315 |
|
|
llr0 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 0)
|
316 |
|
|
llr1 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 1)
|
317 |
|
|
llr2 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 0)
|
318 |
|
|
llr3 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 1)
|
319 |
|
|
zin : in ARRAY4c; -- extrinsic information input signal
|
320 |
|
|
a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder systematic input signal
|
321 |
|
|
b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder systematic input signal
|
322 |
|
|
zout : out ARRAY4c -- extrinsic information output signal
|
323 |
|
|
);
|
324 |
|
|
end component;
|
325 |
|
|
|
326 |
|
|
component sova
|
327 |
|
|
port (
|
328 |
|
|
clk : in std_logic; -- clock
|
329 |
|
|
rst : in std_logic; -- negative reset
|
330 |
|
|
aNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
331 |
|
|
bNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
332 |
|
|
yNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
333 |
|
|
wNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
334 |
|
|
zin : in ARRAY4c; -- extrinsic information input
|
335 |
|
|
zout : out ARRAY4c; -- extrinsic information output
|
336 |
|
|
aClean : out std_logic; -- decoded systematic data
|
337 |
|
|
bClean : out std_logic -- decoded systematic data
|
338 |
|
|
);
|
339 |
|
|
end component;
|
340 |
|
|
|
341 |
|
|
component zPermut
|
342 |
|
|
generic (
|
343 |
|
|
flip : integer := 0 -- initialisation (permutation on/off)
|
344 |
|
|
);
|
345 |
|
|
port (
|
346 |
|
|
flipflop : in std_logic; -- permutation control signal (on/off)
|
347 |
|
|
z : in ARRAY4c; -- original extrinsic information
|
348 |
|
|
zPerm : out ARRAY4c -- permuted extrinsic information
|
349 |
|
|
);
|
350 |
|
|
end component;
|
351 |
|
|
|
352 |
|
|
component interleaver
|
353 |
|
|
generic (
|
354 |
|
|
delay : integer := 0; -- number of clock cycles to wait before starting the (de)interleaver
|
355 |
|
|
way : integer := 0 -- 0 for interleaving, 1 for deinterleaving
|
356 |
|
|
);
|
357 |
|
|
port (
|
358 |
|
|
clk : in std_logic; -- clock
|
359 |
|
|
rst : in std_logic; -- negative reset
|
360 |
|
|
d : in std_logic_vector; -- input data
|
361 |
|
|
q : out std_logic_vector -- interleaved data
|
362 |
|
|
);
|
363 |
|
|
end component;
|
364 |
|
|
|
365 |
|
|
component abPermut
|
366 |
|
|
generic (
|
367 |
|
|
flip : integer := 0 -- initialisation (permutation on/off)
|
368 |
|
|
);
|
369 |
|
|
port (
|
370 |
|
|
flipflop : in std_logic; -- permutation control signal (on/off)
|
371 |
|
|
a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
|
372 |
|
|
b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
|
373 |
|
|
abPerm : out ARRAY2a -- permuted systematic information
|
374 |
|
|
);
|
375 |
|
|
end component;
|
376 |
|
|
|
377 |
|
|
component iteration
|
378 |
|
|
generic (
|
379 |
|
|
delay : integer := 0 -- additional delay created by the previous iterations
|
380 |
|
|
);
|
381 |
|
|
port (
|
382 |
|
|
clk : in std_logic; -- clock
|
383 |
|
|
rst : in std_logic; -- negative reset
|
384 |
|
|
flipflop : in std_logic; -- permutation control signal (on/off)
|
385 |
|
|
a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
386 |
|
|
b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
387 |
|
|
y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
388 |
|
|
w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
389 |
|
|
yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
390 |
|
|
wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
|
391 |
|
|
zin : in ARRAY4c; -- extrinsic information from the previous iteration
|
392 |
|
|
zout : out ARRAY4c; -- extrinsic information to the next iteration
|
393 |
|
|
aDec : out std_logic; -- decoded signal
|
394 |
|
|
bDec : out std_logic; -- decoded signal
|
395 |
|
|
aDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
|
396 |
|
|
bDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
|
397 |
|
|
yDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
|
398 |
|
|
wDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
|
399 |
|
|
yIntDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
|
400 |
|
|
wIntDel : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- delayed received decoder signal
|
401 |
|
|
);
|
402 |
|
|
end component;
|
403 |
|
|
|
404 |
|
|
component clkDiv
|
405 |
|
|
port (
|
406 |
|
|
clk : in std_logic; -- clock
|
407 |
|
|
rst : in std_logic; -- negative reset
|
408 |
|
|
clkout : out std_logic -- clock which frequency is half of the input clock
|
409 |
|
|
);
|
410 |
|
|
end component;
|
411 |
|
|
|
412 |
|
|
component limiter
|
413 |
|
|
port (
|
414 |
|
|
a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
|
415 |
|
|
b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
|
416 |
|
|
y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
|
417 |
|
|
w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
|
418 |
|
|
yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
|
419 |
|
|
wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
|
420 |
|
|
aLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
|
421 |
|
|
bLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
|
422 |
|
|
yLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
|
423 |
|
|
wLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
|
424 |
|
|
yIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
|
425 |
|
|
wIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- limited signal
|
426 |
|
|
);
|
427 |
|
|
end component;
|
428 |
|
|
|
429 |
|
|
component punct
|
430 |
|
|
port (
|
431 |
|
|
clk : in std_logic; -- clock
|
432 |
|
|
rst : in std_logic; -- negative reset
|
433 |
|
|
y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
|
434 |
|
|
w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
|
435 |
|
|
yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
|
436 |
|
|
wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
|
437 |
|
|
yPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
|
438 |
|
|
wPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
|
439 |
|
|
yIntPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
|
440 |
|
|
wIntPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- punctured data
|
441 |
|
|
);
|
442 |
|
|
end component;
|
443 |
|
|
end;
|