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<body>
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<table summary="layout" width="66%" border="0" cellpadding="0" cellspacing="0"><tr><td><table summary="layout" width="100%" border="0" cellpadding="2" cellspacing="1">
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<tr><td class="header">$Revision: 1.2 $</td><td class="header">G. Hutchison</td></tr>
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<tr><td class="header"> </td><td class="header">OpenCores.org</td></tr>
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<tr><td class="header"> </td><td class="header">October 2004</td></tr>
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</table></td></tr></table>
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<div align="right"><span class="title"><br />tv80 Core Documentation</span></div>
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<h3>Abstract</h3>
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<p>
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A synthesizable 8-bit microprocessor which is instruction-set compatable
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with the Z80, targetted at embedded and system-on-a-chip designs.
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</p><a name="toc"></a><br /><hr />
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<h3>Table of Contents</h3>
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<p class="toc">
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<a href="#anchor1">1.</a>
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Background<br />
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<a href="#anchor2">2.</a>
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Verification Environment<br />
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<a href="#anchor3">2.1</a>
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Memory Map<br />
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<a href="#anchor4">2.2</a>
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Control Registers<br />
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<a href="#anchor5">2.2.1</a>
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Simulation control (0x80)<br />
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<a href="#anchor6">2.2.2</a>
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Message output (0x81)<br />
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<a href="#anchor7">2.2.3</a>
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Timeout control (0x82)<br />
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<a href="#anchor8">2.2.4</a>
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Max timeout (0x84, 0x83)<br />
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<a href="#anchor9">2.2.5</a>
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Interrupt countdown (0x90)<br />
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<a href="#anchor10">2.2.6</a>
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Checksum value (0x91)<br />
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<a href="#anchor11">2.2.7</a>
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Checksum accumulate (0x92)<br />
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<a href="#anchor12">2.2.8</a>
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Increment on read (0x93)<br />
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<a href="#anchor13">2.3</a>
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Tool Chain<br />
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<a href="#anchor14">2.4</a>
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Tests<br />
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<a href="#tvs80">2.4.1</a>
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tvs80 test<br />
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<a href="#rfc.references1">3.</a>
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References<br />
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<a href="#rfc.authors">§</a>
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Author's Address<br />
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</p>
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<br clear="all" />
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<a name="anchor1"></a><br /><hr />
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<a name="rfc.section.1"></a><h3>1. Background</h3>
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<p>The tv80 core was created as a Verilog port of the <a class="info" href="#t80">VHDL T80 core<span>Wallner, D., VHDL T80 Core, .</span></a>[1], for use as a maintenence processor inside an ASIC.
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The tv80 has been modified since then for better synthesis
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timing/area results, and to incorporate several bug-fixes.
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</p>
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<p>The T80, and the tv80 derived from it, attempt to maintain the
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original cycle timings of the Z80, but have radically different
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internal designs and timings. With its target being ASIC and
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embedded applications, the tv80 does not attempt to maintain
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the original pinout of the Z80.
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</p>
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<a name="anchor2"></a><br /><hr />
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<a name="rfc.section.2"></a><h3>2. Verification Environment</h3>
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<a name="rfc.section.2.1"></a><h4><a name="anchor3">2.1</a> Memory Map</h4>
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<p>
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Environment memory space is divided into a 32k ROM region and a 32k RAM
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region, as follows:
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</p>
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<pre>
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0000-7FFF: ROM
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8000-FFFF: RAM
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</pre>
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<p>
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<p>Environment I/O space is allocated as follows:
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</p><pre>
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00-0F: Unused
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10-1F: Test devices
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20-7F: Unused
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80-9F: Environment control
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A0-FF: Unused
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</pre>
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<a name="rfc.section.2.2"></a><h4><a name="anchor4">2.2</a> Control Registers</h4>
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<a name="rfc.section.2.2.1"></a><h4><a name="anchor5">2.2.1</a> Simulation control (0x80)</h4>
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<ul class="text">
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<li> Write '01' to end simulation with test passed
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</li>
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<li> Write '02' to end with test failed
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</li>
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<li> Write '03' to turn on dumping
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</li>
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<li> Write '04' to turn off dumping
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</li>
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</ul>
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<a name="rfc.section.2.2.2"></a><h4><a name="anchor6">2.2.2</a> Message output (0x81)</h4>
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<p>
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Write characters to this port one at a time. When the
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newline ('\n', ASCII 0x0A) character is written, the
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environment will print out the collected string.
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</p>
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<a name="rfc.section.2.2.3"></a><h4><a name="anchor7">2.2.3</a> Timeout control (0x82)</h4>
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<p>
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Bit[0] enables the timeout counter,
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Bit[1] resets the counter to 0.
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Timeout counter defaults to enabled at simulation start.
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</p>
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<a name="rfc.section.2.2.4"></a><h4><a name="anchor8">2.2.4</a> Max timeout (0x84, 0x83)</h4>
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<p>
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| 238 |
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Holds 16-bit timeout value (amount of time in clocks before
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timeout error occurs).
|
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</p>
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<a name="rfc.section.2.2.5"></a><h4><a name="anchor9">2.2.5</a> Interrupt countdown (0x90)</h4>
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<p>
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When set, starts a countdown (in clocks) until assertion of
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the INT_N signal.
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</p>
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<a name="rfc.section.2.2.6"></a><h4><a name="anchor10">2.2.6</a> Checksum value (0x91)</h4>
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<p>This register holds the checksum value of all data
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written to the accumulate register. The checksum is a simple
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twos-complement checksum, so it can be compared with a CPU-generated
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checksum.
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</p>
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<p>This register is readable and writeable. Writing the register sets
|
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the current checksum value.
|
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</p>
|
| 259 |
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<a name="rfc.section.2.2.7"></a><h4><a name="anchor11">2.2.7</a> Checksum accumulate (0x92)</h4>
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<p>This write-only register adds the written value to the value
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contained in the Checksum Value register.
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</p>
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<a name="rfc.section.2.2.8"></a><h4><a name="anchor12">2.2.8</a> Increment on read (0x93)</h4>
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<p>This register increments every time it is read, so reading it
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repeatedly generates an incrementing sequence. It can be reset
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by writing it to a new starting value.
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</p>
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<a name="rfc.section.2.3"></a><h4><a name="anchor13">2.3</a> Tool Chain</h4>
|
| 271 |
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<p>The minimum toolchain required to simulate the tv80 is the
|
| 273 |
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<a class="info" href="#cver">CVer<span>Vanvick, A., GPL Cver Simulator, .</span></a>[3] Verilog simulator, and the
|
| 274 |
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<a class="info" href="#sdcc">SDCC<span>, Small Device C Compiler, .</span></a>[2] compiler/assembler/linker. In
|
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addition, to run the <a class="info" href="#tvs80">tvs80<span>tvs80 test</span></a> instruction
|
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test suite, the <a class="info" href="#dosbox">DOSBox<span>, DOSBox, .</span></a>[4] DOS emulator
|
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is required.
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</p>
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<a name="rfc.section.2.4"></a><h4><a name="anchor14">2.4</a> Tests</h4>
|
| 281 |
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|
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<p>Most of the tests in the tv80 environment are written in C, and should
|
| 283 |
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be compiled with the <a class="info" href="#sdcc">sdcc<span>, Small Device C Compiler, .</span></a>[2] compiler.
|
| 284 |
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</p>
|
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<a name="rfc.section.2.4.1"></a><h4><a name="tvs80">2.4.1</a> tvs80 test</h4>
|
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<p>The tvs80 test is different than the rest of the tests, and is
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written in its own flavor of assembly language. This test provides
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a fairly comprehensive Z80 instruction test.
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</p>
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<p>The assembler for this test only runs under DOS. To assemble
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under Unix/Linux, the <a class="info" href="#dosbox">"dosbox" DOS emulator<span>, DOSBox, .</span></a>[4] is required. A script
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to run the assembler under dosbox, as well as the tvs80.asm source,
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is checked in under the "tests/tvs80" directory.
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</p>
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<a name="rfc.references1"></a><br /><hr />
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<h3>3 References</h3>
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<table width="99%" border="0">
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<tr><td class="author-text" valign="top"><a name="t80">[1]</a></td>
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<td class="author-text">Wallner, D., "<a href="http://www.opencores.org/projects.cgi/web/t80/overview">VHDL T80 Core</a>".</td></tr>
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<tr><td class="author-text" valign="top"><a name="sdcc">[2]</a></td>
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<td class="author-text">"<a href="http://sdcc.sourceforge.net">Small Device C Compiler</a>".</td></tr>
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<tr><td class="author-text" valign="top"><a name="cver">[3]</a></td>
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<td class="author-text">Vanvick, A., "<a href="http://www.pragmatic-c.com/gpl-cver">GPL Cver Simulator</a>".</td></tr>
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<tr><td class="author-text" valign="top"><a name="dosbox">[4]</a></td>
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<td class="author-text">"<a href="http://dosbox.sourceforge.net">DOSBox</a>".</td></tr>
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</table>
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<a name="rfc.authors"></a><br /><hr />
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<h3>Author's Address</h3>
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<table width="99%" border="0" cellpadding="0" cellspacing="0">
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<tr><td class="author-text"> </td>
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<td class="author-text">Guy Hutchison</td></tr>
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<tr><td class="author-text"> </td>
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<td class="author-text">OpenCores.org</td></tr>
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<tr><td class="author" align="right">EMail: </td>
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<td class="author-text"><a href="mailto:ghutchis@opencores.org">ghutchis@opencores.org</a></td></tr>
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</table>
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</body></html>
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