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A synthesizable 8-bit microprocessor which is instruction-set compatable

with the Z80, targetted at embedded and system-on-a-chip designs.

        The tv80 core was created as a Verilog port of the VHDL T80 core, for use as a maintenence processor inside an ASIC.

            The tv80 has been modified since then for better synthesis

            timing/area results, and to incorporate several bug-fixes.

        The T80, and the tv80 derived from it, attempt to maintain the

            original cycle timings of the Z80, but have radically different

            internal designs and timings.  With its target being ASIC and

            embedded applications, the tv80 does not attempt to maintain

            the original pinout of the Z80.

Environment memory space is divided into a 32k ROM region and a 32k RAM

region, as follows:

  0000-7FFF:  ROM

  8000-FFFF:  RAM

Environment I/O space is allocated as follows:

  00-0F:  Unused

  10-1F:  Test devices

  20-7F:  Unused

  80-9F:  Environment control

  A0-FF:  Unused

The tv80 environment is controlled by the program under simulation.  The

program can affect the environment through a set of control registers,

which are mapped into I/O space.

        Write '01' to end simulation with test passed

        Write '02' to end with test failed

        Write '03' to turn on dumping

        Write '04' to turn off dumping

        Write characters to this port one at a time.  When the

        newline ('\n', ASCII 0x0A) character is written, the

        environment will print out the collected string.

        Bit[0] enables the timeout counter,

        Bit[1] resets the counter to 0.

        Timeout counter defaults to enabled at simulation start.

        Holds 16-bit timeout value (amount of time in clocks before

        timeout error occurs).

        When set, starts a countdown (in clocks) until assertion of

        the INT_N signal.

    This register holds the checksum value of all data

       written to the accumulate register.  The checksum is a simple

       twos-complement checksum, so it can be compared with a CPU-generated

       checksum.

    This register is readable and writeable.  Writing the register sets

       the current checksum value.

    This write-only register adds the written value to the value

       contained in the Checksum Value register.

    This register increments every time it is read, so reading it

       repeatedly generates an incrementing sequence.  It can be reset

       by writing it to a new starting value.

     The minimum toolchain required to simulate the tv80 is the

         CVer Verilog simulator, and the

         SDCC compiler/assembler/linker.  In

         addition, to run the tvs80 instruction

         test suite, the DOSBox DOS emulator

         is required.

   Most of the tests in the tv80 environment are written in C, and should

       be compiled with the sdcc compiler.

      The tvs80 test is different than the rest of the tests, and is

         written in its own flavor of assembly language.  This test provides

         a fairly comprehensive Z80 instruction test.

      The assembler for this test only runs under DOS.  To assemble

          under Unix/Linux, the "dosbox" DOS emulator is required.  A script

         to run the assembler under dosbox, as well as the tvs80.asm source,

         is checked in under the "tests/tvs80" directory.

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