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[/] [tv80/] [branches/] [restruc2/] [env/] [tb_top.v] - Blame information for rev 84

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`define TV80_CORE_PATH tb_top.tv80s_inst.i_tv80_core
 
module tb_top;
 
  reg         clk;
  reg         reset_n;
  reg         wait_n;
  reg         int_n;
  reg         nmi_n;
  reg         busrq_n;
  wire        m1_n;
  wire        mreq_n;
  wire        iorq_n;
  wire        rd_n;
  wire        wr_n;
  wire        rfsh_n;
  wire        halt_n;
  wire        busak_n;
  wire [15:0] A;
  wire [7:0]  di;
  wire [7:0]  do;
  wire        ram_rd_cs, ram_wr_cs, rom_rd_cs;
 
  always
    begin
      clk = 1;
      #5;
      clk = 0;
      #5;
    end
 
  assign rom_rd_cs = !mreq_n & !rd_n & !A[15];
  assign ram_rd_cs = !mreq_n & !rd_n & A[15];
  assign ram_wr_cs = !mreq_n & !wr_n & A[15];
 
  tv80s tv80s_inst
    (
     // Outputs
     .m1_n                              (m1_n),
     .mreq_n                            (mreq_n),
     .iorq_n                            (iorq_n),
     .rd_n                              (rd_n),
     .wr_n                              (wr_n),
     .rfsh_n                            (rfsh_n),
     .halt_n                            (halt_n),
     .busak_n                           (busak_n),
     .A                                 (A[15:0]),
     .do                                (do[7:0]),
     // Inputs
     .reset_n                           (reset_n),
     .clk                               (clk),
     .wait_n                            (wait_n),
     .int_n                             (int_n),
     .nmi_n                             (nmi_n),
     .busrq_n                           (busrq_n),
     .di                                (di[7:0]));
 
  async_mem ram
    (
     // Outputs
     .rd_data                           (di),
     // Inputs
     .wr_clk                            (clk),
     .wr_data                           (do),
     .wr_cs                             (ram_wr_cs),
     .addr                              (A[14:0]),
     .rd_cs                             (ram_rd_cs));
 
  async_mem rom
    (
     // Outputs
     .rd_data                           (di),
     // Inputs
     .wr_clk                            (),
     .wr_data                           (),
     .wr_cs                             (1'b0),
     .addr                              (A[14:0]),
     .rd_cs                             (rom_rd_cs));
 
  env_io env_io_inst
    (
     // Outputs
     .DI                                (di[7:0]),
     // Inputs
     .clk                               (clk),
     .iorq_n                            (iorq_n),
     .rd_n                              (rd_n),
     .wr_n                              (wr_n),
     .addr                              (A[7:0]),
     .DO                                (do[7:0]));
 
  initial
    begin
      clear_ram;
      reset_n = 0;
      wait_n = 1;
      int_n  = 1;
      nmi_n  = 1;
      busrq_n = 1;
      $readmemh (`PROGRAM_FILE,  tb_top.rom.mem);
      repeat (20) @(negedge clk);
      reset_n = 1;
    end // initial begin
 
`ifdef DUMP_START
  always
    begin
      if ($time > `DUMP_START)
        dumpon;
      #100;
    end
`endif
 
 
/*
  always
    begin
      while (mreq_n) @(posedge clk);
      wait_n <= #1 0;
      @(posedge clk);
      wait_n <= #1 1;
      while (!mreq_n) @(posedge clk);
    end
  */
 
`ifdef TV80_INSTRUCTION_DECODE
  reg [7:0] state;
  initial
    state = 0;
 
  always @(posedge clk)
    begin : inst_decode
      if ((`TV80_CORE_PATH.mcycle[6:0] == 1) &&
          (`TV80_CORE_PATH.tstate[6:0] == 8))
        begin
          op_decode.decode (`TV80_CORE_PATH.IR[7:0], state);
        end
      else if (`TV80_CORE_PATH.mcycle[6:0] != 1)
        state = 0;
    end
`endif
 
`include "env_tasks.v"
 
endmodule // tb_top

Line No.	Rev	Author	Line
1	31	ghutchis	`define TV80_CORE_PATH tb_top.tv80s_inst.i_tv80_core
2
3	2	ghutchis	`module tb_top;`
4
5			`reg clk;`
6			`reg reset_n;`
7			`reg wait_n;`
8			`reg int_n;`
9			`reg nmi_n;`
10			`reg busrq_n;`
11			`wire m1_n;`
12			`wire mreq_n;`
13			`wire iorq_n;`
14			`wire rd_n;`
15			`wire wr_n;`
16			`wire rfsh_n;`
17			`wire halt_n;`
18			`wire busak_n;`
19			`wire [15:0] A;`
20			`wire [7:0] di;`
21			`wire [7:0] do;`
22			`wire ram_rd_cs, ram_wr_cs, rom_rd_cs;`
23
24			`always`
25			`begin`
26			`clk = 1;`
27			`#5;`
28			`clk = 0;`
29			`#5;`
30			`end`
31
32			`assign rom_rd_cs = !mreq_n & !rd_n & !A[15];`
33			`assign ram_rd_cs = !mreq_n & !rd_n & A[15];`
34			`assign ram_wr_cs = !mreq_n & !wr_n & A[15];`
35
36			`tv80s tv80s_inst`
37			`(`
38			`// Outputs`
39			`.m1_n (m1_n),`
40			`.mreq_n (mreq_n),`
41			`.iorq_n (iorq_n),`
42			`.rd_n (rd_n),`
43			`.wr_n (wr_n),`
44			`.rfsh_n (rfsh_n),`
45			`.halt_n (halt_n),`
46			`.busak_n (busak_n),`
47			`.A (A[15:0]),`
48			`.do (do[7:0]),`
49			`// Inputs`
50			`.reset_n (reset_n),`
51			`.clk (clk),`
52			`.wait_n (wait_n),`
53			`.int_n (int_n),`
54			`.nmi_n (nmi_n),`
55			`.busrq_n (busrq_n),`
56			`.di (di[7:0]));`
57
58			`async_mem ram`
59			`(`
60			`// Outputs`
61			`.rd_data (di),`
62			`// Inputs`
63			`.wr_clk (clk),`
64			`.wr_data (do),`
65			`.wr_cs (ram_wr_cs),`
66			`.addr (A[14:0]),`
67			`.rd_cs (ram_rd_cs));`
68
69			`async_mem rom`
70			`(`
71			`// Outputs`
72			`.rd_data (di),`
73			`// Inputs`
74			`.wr_clk (),`
75			`.wr_data (),`
76			`.wr_cs (1'b0),`
77			`.addr (A[14:0]),`
78			`.rd_cs (rom_rd_cs));`
79
80			`env_io env_io_inst`
81			`(`
82			`// Outputs`
83			`.DI (di[7:0]),`
84			`// Inputs`
85			`.clk (clk),`
86			`.iorq_n (iorq_n),`
87			`.rd_n (rd_n),`
88			`.wr_n (wr_n),`
89			`.addr (A[7:0]),`
90			`.DO (do[7:0]));`
91
92			`initial`
93			`begin`
94	28	ghutchis	`clear_ram;`
95	2	ghutchis	`reset_n = 0;`
96			`wait_n = 1;`
97			`int_n = 1;`
98			`nmi_n = 1;`
99			`busrq_n = 1;`
100			$readmemh (`PROGRAM_FILE, tb_top.rom.mem);
101			`repeat (20) @(negedge clk);`
102			`reset_n = 1;`
103	42	ghutchis	`end // initial begin`
104
105			`ifdef DUMP_START
106			`always`
107			`begin`
108			if ($time > `DUMP_START)
109			`dumpon;`
110			`#100;`
111	2	ghutchis	`end`
112	42	ghutchis	`endif
113
114
115	36	ghutchis	`/*`
116			`always`
117			`begin`
118			`while (mreq_n) @(posedge clk);`
119			`wait_n <= #1 0;`
120			`@(posedge clk);`
121			`wait_n <= #1 1;`
122			`while (!mreq_n) @(posedge clk);`
123			`end`
124			`*/`
125	2	ghutchis
126	31	ghutchis	`ifdef TV80_INSTRUCTION_DECODE
127			`reg [7:0] state;`
128			`initial`
129			`state = 0;`
130
131			`always @(posedge clk)`
132			`begin : inst_decode`
133			if ((`TV80_CORE_PATH.mcycle[6:0] == 1) &&
134			(`TV80_CORE_PATH.tstate[6:0] == 8))
135			`begin`
136			op_decode.decode (`TV80_CORE_PATH.IR[7:0], state);
137			`end`
138			else if (`TV80_CORE_PATH.mcycle[6:0] != 1)
139			`state = 0;`
140			`end`
141			`endif
142
143	2	ghutchis	`include "env_tasks.v"
144
145			`endmodule // tb_top`

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[/] [tv80/] [branches/] [restruc2/] [env/] [tb_top.v] - Blame information for rev 84