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//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a 
// copy of this software and associated documentation files (the "Software"), 
// to deal in the Software without restriction, including without limitation 
// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
// and/or sell copies of the Software, and to permit persons to whom the 
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included 
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
module tv80_mcode
  (/*AUTOARG*/
  // Outputs
  MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,
  Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,
  Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,
  LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,
  ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR,
  I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write,
  // Inputs
  IR, ISet, MCycle, F, tstate, NMICycle, IntCycle
  );
 
  parameter             Mode   = 0;
  parameter             Flag_C = 0;
  parameter             Flag_N = 1;
  parameter             Flag_P = 2;
  parameter             Flag_X = 3;
  parameter             Flag_H = 4;
  parameter             Flag_Y = 5;
  parameter             Flag_Z = 6;
  parameter             Flag_S = 7;
 
  input [7:0]           IR;
  input [1:0]           ISet                    ;
  input [6:0]           MCycle                  ;
  input [7:0]           F                       ;
  input [6:0]           tstate;
  input                 NMICycle                ;
  input                 IntCycle                ;
  output [2:0]          MCycles                 ;
  output [2:0]          TStates                 ;
  output [1:0]          Prefix                  ; // None,BC,ED,DD/FD
  output                Inc_PC                  ;
  output                Inc_WZ                  ;
  output [3:0]          IncDec_16               ; // BC,DE,HL,SP   0 is inc
  output                Read_To_Reg             ;
  output                Read_To_Acc             ;
  output [3:0]          Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
  output [3:0]          Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
  output [3:0]          ALU_Op                  ;
  output                Save_ALU                ;
  output                PreserveC               ;
  output                Arith16                 ;
  output [2:0]          Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
  output                IORQ                    ;
  output                Jump                    ;
  output                JumpE                   ;
  output                JumpXY                  ;
  output                Call                    ;
  output                RstP                    ;
  output                LDZ                     ;
  output                LDW                     ;
  output                LDSPHL                  ;
  output [2:0]          Special_LD              ; // A,I;A,R;I,A;R,A;None
  output                ExchangeDH              ;
  output                ExchangeRp              ;
  output                ExchangeAF              ;
  output                ExchangeRS              ;
  output                I_DJNZ                  ;
  output                I_CPL                   ;
  output                I_CCF                   ;
  output                I_SCF                   ;
  output                I_RETN                  ;
  output                I_BT                    ;
  output                I_BC                    ;
  output                I_BTR                   ;
  output                I_RLD                   ;
  output                I_RRD                   ;
  output                I_INRC                  ;
  output                SetDI                   ;
  output                SetEI                   ;
  output [1:0]          IMode                   ;
  output                Halt                    ;
  output                NoRead                  ;
  output                Write   ;
 
  // regs
  reg [2:0]             MCycles                 ;
  reg [2:0]             TStates                 ;
  reg [1:0]             Prefix                  ; // None,BC,ED,DD/FD
  reg                   Inc_PC                  ;
  reg                   Inc_WZ                  ;
  reg [3:0]             IncDec_16               ; // BC,DE,HL,SP   0 is inc
  reg                   Read_To_Reg             ;
  reg                   Read_To_Acc             ;
  reg [3:0]             Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
  reg [3:0]             Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
  reg [3:0]             ALU_Op                  ;
  reg                   Save_ALU                ;
  reg                   PreserveC               ;
  reg                   Arith16                 ;
  reg [2:0]             Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
  reg                   IORQ                    ;
  reg                   Jump                    ;
  reg                   JumpE                   ;
  reg                   JumpXY                  ;
  reg                   Call                    ;
  reg                   RstP                    ;
  reg                   LDZ                     ;
  reg                   LDW                     ;
  reg                   LDSPHL                  ;
  reg [2:0]             Special_LD              ; // A,I;A,R;I,A;R,A;None
  reg                   ExchangeDH              ;
  reg                   ExchangeRp              ;
  reg                   ExchangeAF              ;
  reg                   ExchangeRS              ;
  reg                   I_DJNZ                  ;
  reg                   I_CPL                   ;
  reg                   I_CCF                   ;
  reg                   I_SCF                   ;
  reg                   I_RETN                  ;
  reg                   I_BT                    ;
  reg                   I_BC                    ;
  reg                   I_BTR                   ;
  reg                   I_RLD                   ;
  reg                   I_RRD                   ;
  reg                   I_INRC                  ;
  reg                   SetDI                   ;
  reg                   SetEI                   ;
  reg [1:0]             IMode                   ;
  reg                   Halt                    ;
  reg                   NoRead                  ;
  reg                   Write   ;
 
  parameter             aNone   = 3'b111;
  parameter             aBC     = 3'b000;
  parameter             aDE     = 3'b001;
  parameter             aXY     = 3'b010;
  parameter             aIOA    = 3'b100;
  parameter             aSP     = 3'b101;
  parameter             aZI     = 3'b110;
 
 
  reg [2:0] DDD;
  reg [2:0] SSS;
  reg [1:0] DPAIR;
 
  wire [67:0] vec_base, vec_cb, vec_ed;
  reg [67:0]  vec_final;
 
  // instruction decoders
  tv80_mcode_base #(Mode) dec_base
    (
     // Outputs
     .output_vector                     (vec_base),
     // Inputs
     .IR                                (IR),
     .MCycle                            (MCycle),
     .tstate                            (tstate),
     .F                                 (F),
     .NMICycle                          (NMICycle),
     .IntCycle                          (IntCycle));
 
  tv80_mcode_cb #(Mode) dec_cb
    (
     // Outputs
     .output_vector                     (vec_cb),
     // Inputs
     .IR                                (IR),
     .MCycle                            (MCycle));
 
  tv80_mcode_ed #(Mode) dec_ed
    (
     // Outputs
     .output_vector                     (vec_ed),
     // Inputs
     .IR                                (IR),
     .MCycle                            (MCycle));
 
  always @ (/*AUTOSENSE*/IR or ISet or MCycle or SSS or vec_base
            or vec_cb or vec_ed)
    begin
      case (ISet)
        2'b00  : vec_final = vec_base;
        2'b01  : vec_final = vec_cb;
        default : vec_final = vec_ed;
      endcase // case(ISet)
 
      { MCycles,
        TStates,
        Prefix,
        Inc_PC,
        Inc_WZ,
        IncDec_16,
        Read_To_Reg,
        Read_To_Acc,
        Set_BusA_To,
        Set_BusB_To,
        ALU_Op,
        Save_ALU,
        PreserveC,
        Arith16,
        Set_Addr_To,
        IORQ,
        Jump,
        JumpE,
        JumpXY,
        Call,
        RstP,
        LDZ,
        LDW,
        LDSPHL,
        Special_LD,
        ExchangeDH,
        ExchangeRp,
        ExchangeAF,
        ExchangeRS,
        I_DJNZ,
        I_CPL,
        I_CCF,
        I_SCF,
        I_RETN,
        I_BT,
        I_BC,
        I_BTR,
        I_RLD,
        I_RRD,
        I_INRC,
        SetDI,
        SetEI,
        IMode,
        Halt,
        NoRead,
        Write } = vec_final;
 
      if (Mode == 1 )
        begin
          if (MCycle[0] )
            begin
              //TStates = 3'b100;
            end
          else
            begin
              TStates = 3'b011;
            end
        end
 
      if (Mode == 3 )
        begin
          if (MCycle[0] )
            begin
              //TStates = 3'b100;
            end
          else
            begin
              TStates = 3'b100;
            end
        end
 
      if (Mode < 2 )
        begin
          if (MCycle[5] )
            begin
              Inc_PC = 1'b1;
              if (Mode == 1 )
                begin
                  Set_Addr_To = aXY;
                  TStates = 3'b100;
                  Set_BusB_To[2:0] = SSS;
                  Set_BusB_To[3] = 1'b0;
                end
              if (IR == 8'b00110110 || IR == 8'b11001011 )
                begin
                  Set_Addr_To = aNone;
                end
            end
          if (MCycle[6] )
            begin
              if (Mode == 0 )
                begin
                  TStates = 3'b101;
                end
              if (ISet != 2'b01 )
                begin
                  Set_Addr_To = aXY;
                end
              Set_BusB_To[2:0] = SSS;
              Set_BusB_To[3] = 1'b0;
              if (IR == 8'b00110110 || ISet == 2'b01 )
                begin
                  // LD (HL),n
                  Inc_PC = 1'b1;
                end
              else
                begin
                  NoRead = 1'b1;
                end
            end
        end // if (Mode < 2 )      
 
    end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
 
  // synopsys dc_script_begin
  // set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.5.4.2 2004-12-16 00:46:29 ghutchis Exp $" -type string -quiet
  // synopsys dc_script_end
endmodule // T80_MCode

Line No.	Rev	Author	Line
1	2	ghutchis	`//`
2			`// TV80 8-Bit Microprocessor Core`
3			`// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)`
4			`//`
5			`// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)`
6			`//`
7			`// Permission is hereby granted, free of charge, to any person obtaining a`
8			`// copy of this software and associated documentation files (the "Software"),`
9			`// to deal in the Software without restriction, including without limitation`
10			`// the rights to use, copy, modify, merge, publish, distribute, sublicense,`
11			`// and/or sell copies of the Software, and to permit persons to whom the`
12			`// Software is furnished to do so, subject to the following conditions:`
13			`//`
14			`// The above copyright notice and this permission notice shall be included`
15			`// in all copies or substantial portions of the Software.`
16			`//`
17			`// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,`
18			`// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF`
19			`// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.`
20			`// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY`
21			`// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,`
22			`// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE`
23			`// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.`
24
25	24	ghutchis	`module tv80_mcode`
26			`(/AUTOARG/`
27	48	ghutchis	`// Outputs`
28			`MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,`
29			`Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,`
30			`Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,`
31			`LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,`
32			`ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR,`
33			`I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write,`
34			`// Inputs`
35	51	ghutchis	`IR, ISet, MCycle, F, tstate, NMICycle, IntCycle`
36	48	ghutchis	`);`
37	2	ghutchis
38	24	ghutchis	`parameter Mode = 0;`
39			`parameter Flag_C = 0;`
40			`parameter Flag_N = 1;`
41			`parameter Flag_P = 2;`
42			`parameter Flag_X = 3;`
43			`parameter Flag_H = 4;`
44			`parameter Flag_Y = 5;`
45			`parameter Flag_Z = 6;`
46			`parameter Flag_S = 7;`
47	2	ghutchis
48			`input [7:0] IR;`
49	24	ghutchis	`input [1:0] ISet ;`
50			`input [6:0] MCycle ;`
51			`input [7:0] F ;`
52	51	ghutchis	`input [6:0] tstate;`
53	24	ghutchis	`input NMICycle ;`
54			`input IntCycle ;`
55			`output [2:0] MCycles ;`
56			`output [2:0] TStates ;`
57			`output [1:0] Prefix ; // None,BC,ED,DD/FD`
58			`output Inc_PC ;`
59			`output Inc_WZ ;`
60			`output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc`
61			`output Read_To_Reg ;`
62			`output Read_To_Acc ;`
63			`output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F`
64			`output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0`
65			`output [3:0] ALU_Op ;`
66			`output Save_ALU ;`
67			`output PreserveC ;`
68			`output Arith16 ;`
69			`output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI`
70			`output IORQ ;`
71			`output Jump ;`
72			`output JumpE ;`
73			`output JumpXY ;`
74			`output Call ;`
75			`output RstP ;`
76			`output LDZ ;`
77			`output LDW ;`
78			`output LDSPHL ;`
79			`output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None`
80			`output ExchangeDH ;`
81			`output ExchangeRp ;`
82			`output ExchangeAF ;`
83			`output ExchangeRS ;`
84			`output I_DJNZ ;`
85			`output I_CPL ;`
86			`output I_CCF ;`
87			`output I_SCF ;`
88			`output I_RETN ;`
89			`output I_BT ;`
90			`output I_BC ;`
91			`output I_BTR ;`
92			`output I_RLD ;`
93			`output I_RRD ;`
94			`output I_INRC ;`
95			`output SetDI ;`
96			`output SetEI ;`
97			`output [1:0] IMode ;`
98			`output Halt ;`
99			`output NoRead ;`
100			`output Write ;`
101	2	ghutchis
102			`// regs`
103	24	ghutchis	`reg [2:0] MCycles ;`
104			`reg [2:0] TStates ;`
105			`reg [1:0] Prefix ; // None,BC,ED,DD/FD`
106			`reg Inc_PC ;`
107			`reg Inc_WZ ;`
108			`reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc`
109			`reg Read_To_Reg ;`
110			`reg Read_To_Acc ;`
111			`reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F`
112			`reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0`
113			`reg [3:0] ALU_Op ;`
114			`reg Save_ALU ;`
115			`reg PreserveC ;`
116			`reg Arith16 ;`
117			`reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI`
118			`reg IORQ ;`
119			`reg Jump ;`
120			`reg JumpE ;`
121			`reg JumpXY ;`
122			`reg Call ;`
123			`reg RstP ;`
124			`reg LDZ ;`
125			`reg LDW ;`
126			`reg LDSPHL ;`
127			`reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None`
128			`reg ExchangeDH ;`
129			`reg ExchangeRp ;`
130			`reg ExchangeAF ;`
131			`reg ExchangeRS ;`
132			`reg I_DJNZ ;`
133			`reg I_CPL ;`
134			`reg I_CCF ;`
135			`reg I_SCF ;`
136			`reg I_RETN ;`
137			`reg I_BT ;`
138			`reg I_BC ;`
139			`reg I_BTR ;`
140			`reg I_RLD ;`
141			`reg I_RRD ;`
142			`reg I_INRC ;`
143			`reg SetDI ;`
144			`reg SetEI ;`
145			`reg [1:0] IMode ;`
146			`reg Halt ;`
147			`reg NoRead ;`
148			`reg Write ;`
149	2	ghutchis
150	24	ghutchis	`parameter aNone = 3'b111;`
151			`parameter aBC = 3'b000;`
152			`parameter aDE = 3'b001;`
153			`parameter aXY = 3'b010;`
154			`parameter aIOA = 3'b100;`
155			`parameter aSP = 3'b101;`
156			`parameter aZI = 3'b110;`
157	2	ghutchis
158
159			`reg [2:0] DDD;`
160			`reg [2:0] SSS;`
161			`reg [1:0] DPAIR;`
162	48	ghutchis
163			`wire [67:0] vec_base, vec_cb, vec_ed;`
164			`reg [67:0] vec_final;`
165	2	ghutchis
166	48	ghutchis	`// instruction decoders`
167			`tv80_mcode_base #(Mode) dec_base`
168			`(`
169			`// Outputs`
170			`.output_vector (vec_base),`
171			`// Inputs`
172			`.IR (IR),`
173			`.MCycle (MCycle),`
174	51	ghutchis	`.tstate (tstate),`
175	48	ghutchis	`.F (F),`
176			`.NMICycle (NMICycle),`
177			`.IntCycle (IntCycle));`
178
179			`tv80_mcode_cb #(Mode) dec_cb`
180			`(`
181			`// Outputs`
182			`.output_vector (vec_cb),`
183			`// Inputs`
184			`.IR (IR),`
185			`.MCycle (MCycle));`
186
187			`tv80_mcode_ed #(Mode) dec_ed`
188			`(`
189			`// Outputs`
190			`.output_vector (vec_ed),`
191			`// Inputs`
192			`.IR (IR),`
193			`.MCycle (MCycle));`
194
195			`always @ (/AUTOSENSE/IR or ISet or MCycle or SSS or vec_base`
196			`or vec_cb or vec_ed)`
197	2	ghutchis	`begin`
198			`case (ISet)`
199	48	ghutchis	`2'b00 : vec_final = vec_base;`
200			`2'b01 : vec_final = vec_cb;`
201			`default : vec_final = vec_ed;`
202	2	ghutchis	`endcase // case(ISet)`
203	24	ghutchis
204	48	ghutchis	`{ MCycles,`
205			`TStates,`
206			`Prefix,`
207			`Inc_PC,`
208			`Inc_WZ,`
209			`IncDec_16,`
210			`Read_To_Reg,`
211			`Read_To_Acc,`
212			`Set_BusA_To,`
213			`Set_BusB_To,`
214			`ALU_Op,`
215			`Save_ALU,`
216			`PreserveC,`
217			`Arith16,`
218			`Set_Addr_To,`
219			`IORQ,`
220			`Jump,`
221			`JumpE,`
222			`JumpXY,`
223			`Call,`
224			`RstP,`
225			`LDZ,`
226			`LDW,`
227			`LDSPHL,`
228			`Special_LD,`
229			`ExchangeDH,`
230			`ExchangeRp,`
231			`ExchangeAF,`
232			`ExchangeRS,`
233			`I_DJNZ,`
234			`I_CPL,`
235			`I_CCF,`
236			`I_SCF,`
237			`I_RETN,`
238			`I_BT,`
239			`I_BC,`
240			`I_BTR,`
241			`I_RLD,`
242			`I_RRD,`
243			`I_INRC,`
244			`SetDI,`
245			`SetEI,`
246			`IMode,`
247			`Halt,`
248			`NoRead,`
249			`Write } = vec_final;`
250
251	2	ghutchis	`if (Mode == 1 )`
252			`begin`
253	24	ghutchis	`if (MCycle[0] )`
254	2	ghutchis	`begin`
255			`//TStates = 3'b100;`
256	24	ghutchis	`end`
257	2	ghutchis	`else`
258			`begin`
259	24	ghutchis	`TStates = 3'b011;`
260			`end`
261			`end`
262	2	ghutchis
263			`if (Mode == 3 )`
264			`begin`
265	24	ghutchis	`if (MCycle[0] )`
266	2	ghutchis	`begin`
267	24	ghutchis	`//TStates = 3'b100;`
268			`end`
269	2	ghutchis	`else`
270			`begin`
271	24	ghutchis	`TStates = 3'b100;`
272			`end`
273			`end`
274	2	ghutchis
275			`if (Mode < 2 )`
276			`begin`
277	24	ghutchis	`if (MCycle[5] )`
278	2	ghutchis	`begin`
279	24	ghutchis	`Inc_PC = 1'b1;`
280			`if (Mode == 1 )`
281	2	ghutchis	`begin`
282	24	ghutchis	`Set_Addr_To = aXY;`
283			`TStates = 3'b100;`
284			`Set_BusB_To[2:0] = SSS;`
285			`Set_BusB_To[3] = 1'b0;`
286			`end`
287	48	ghutchis	`if (IR == 8'b00110110 \|\| IR == 8'b11001011 )`
288	2	ghutchis	`begin`
289	24	ghutchis	`Set_Addr_To = aNone;`
290			`end`
291			`end`
292			`if (MCycle[6] )`
293	2	ghutchis	`begin`
294	24	ghutchis	`if (Mode == 0 )`
295	2	ghutchis	`begin`
296	24	ghutchis	`TStates = 3'b101;`
297			`end`
298			`if (ISet != 2'b01 )`
299	2	ghutchis	`begin`
300	24	ghutchis	`Set_Addr_To = aXY;`
301			`end`
302			`Set_BusB_To[2:0] = SSS;`
303			`Set_BusB_To[3] = 1'b0;`
304	48	ghutchis	`if (IR == 8'b00110110 \|\| ISet == 2'b01 )`
305	2	ghutchis	`begin`
306	24	ghutchis	`// LD (HL),n`
307			`Inc_PC = 1'b1;`
308			`end`
309	2	ghutchis	`else`
310			`begin`
311	24	ghutchis	`NoRead = 1'b1;`
312			`end`
313			`end`
314			`end // if (Mode < 2 )`
315	2	ghutchis
316			`end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)`
317
318	24	ghutchis	`// synopsys dc_script_begin`
319	51	ghutchis	`// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.5.4.2 2004-12-16 00:46:29 ghutchis Exp $" -type string -quiet`
320	24	ghutchis	`// synopsys dc_script_end`
321	2	ghutchis	`endmodule // T80_MCode`

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