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ghutchis |
//
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// TV80 8-Bit Microprocessor Core
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// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
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//
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// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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module tv80_mcode_cb
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(/*AUTOARG*/
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// Outputs
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output_vector,
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// Inputs
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IR, MCycle
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);
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parameter Mode = 0;
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parameter Flag_C = 0;
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parameter Flag_N = 1;
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parameter Flag_P = 2;
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parameter Flag_X = 3;
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parameter Flag_H = 4;
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parameter Flag_Y = 5;
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parameter Flag_Z = 6;
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parameter Flag_S = 7;
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output [67:0] output_vector;
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input [7:0] IR;
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input [6:0] MCycle ;
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// regs
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reg [2:0] MCycles ;
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reg [2:0] TStates ;
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reg [1:0] Prefix ; // None,BC,ED,DD/FD
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reg Inc_PC ;
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reg Inc_WZ ;
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reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc
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reg Read_To_Reg ;
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reg Read_To_Acc ;
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reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
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reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
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reg [3:0] ALU_Op ;
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reg Save_ALU ;
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reg PreserveC ;
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reg Arith16 ;
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reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
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reg IORQ ;
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reg Jump ;
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reg JumpE ;
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reg JumpXY ;
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reg Call ;
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reg RstP ;
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reg LDZ ;
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reg LDW ;
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reg LDSPHL ;
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reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None
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reg ExchangeDH ;
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reg ExchangeRp ;
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reg ExchangeAF ;
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reg ExchangeRS ;
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reg I_DJNZ ;
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reg I_CPL ;
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reg I_CCF ;
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reg I_SCF ;
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reg I_RETN ;
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reg I_BT ;
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reg I_BC ;
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reg I_BTR ;
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reg I_RLD ;
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reg I_RRD ;
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reg I_INRC ;
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reg SetDI ;
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reg SetEI ;
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reg [1:0] IMode ;
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reg Halt ;
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reg NoRead ;
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reg Write ;
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parameter aNone = 3'b111;
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parameter aBC = 3'b000;
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parameter aDE = 3'b001;
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parameter aXY = 3'b010;
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parameter aIOA = 3'b100;
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parameter aSP = 3'b101;
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parameter aZI = 3'b110;
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// constant aNone : std_logic_vector[2:0] = 3'b000;
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// constant aXY : std_logic_vector[2:0] = 3'b001;
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// constant aIOA : std_logic_vector[2:0] = 3'b010;
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// constant aSP : std_logic_vector[2:0] = 3'b011;
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// constant aBC : std_logic_vector[2:0] = 3'b100;
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// constant aDE : std_logic_vector[2:0] = 3'b101;
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// constant aZI : std_logic_vector[2:0] = 3'b110;
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function is_cc_true;
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input [7:0] F;
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input [2:0] cc;
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begin
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if (Mode == 3 )
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begin
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case (cc)
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3'b000 : is_cc_true = F[7] == 1'b0; // NZ
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3'b001 : is_cc_true = F[7] == 1'b1; // Z
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3'b010 : is_cc_true = F[4] == 1'b0; // NC
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3'b011 : is_cc_true = F[4] == 1'b1; // C
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3'b100 : is_cc_true = 0;
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3'b101 : is_cc_true = 0;
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3'b110 : is_cc_true = 0;
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3'b111 : is_cc_true = 0;
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endcase
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end
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else
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begin
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case (cc)
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3'b000 : is_cc_true = F[6] == 1'b0; // NZ
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3'b001 : is_cc_true = F[6] == 1'b1; // Z
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3'b010 : is_cc_true = F[0] == 1'b0; // NC
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3'b011 : is_cc_true = F[0] == 1'b1; // C
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3'b100 : is_cc_true = F[2] == 1'b0; // PO
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3'b101 : is_cc_true = F[2] == 1'b1; // PE
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3'b110 : is_cc_true = F[7] == 1'b0; // P
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3'b111 : is_cc_true = F[7] == 1'b1; // M
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endcase
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end
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end
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endfunction // is_cc_true
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reg [2:0] DDD;
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reg [2:0] SSS;
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reg [1:0] DPAIR;
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reg [7:0] IRB;
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always @ (/*AUTOSENSE*/IR or MCycle)
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begin
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DDD = IR[5:3];
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SSS = IR[2:0];
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DPAIR = IR[5:4];
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IRB = IR;
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MCycles = 3'b001;
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if (MCycle[0] )
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begin
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TStates = 3'b100;
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end
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else
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begin
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TStates = 3'b011;
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end
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Prefix = 2'b00;
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Inc_PC = 1'b0;
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Inc_WZ = 1'b0;
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IncDec_16 = 4'b0000;
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Read_To_Acc = 1'b0;
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Read_To_Reg = 1'b0;
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Set_BusB_To = 4'b0000;
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Set_BusA_To = 4'b0000;
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ALU_Op = { 1'b0, IR[5:3] };
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Save_ALU = 1'b0;
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PreserveC = 1'b0;
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Arith16 = 1'b0;
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IORQ = 1'b0;
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Set_Addr_To = aNone;
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Jump = 1'b0;
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JumpE = 1'b0;
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JumpXY = 1'b0;
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Call = 1'b0;
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RstP = 1'b0;
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LDZ = 1'b0;
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LDW = 1'b0;
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LDSPHL = 1'b0;
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Special_LD = 3'b000;
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ExchangeDH = 1'b0;
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ExchangeRp = 1'b0;
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ExchangeAF = 1'b0;
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ExchangeRS = 1'b0;
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I_DJNZ = 1'b0;
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I_CPL = 1'b0;
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I_CCF = 1'b0;
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I_SCF = 1'b0;
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I_RETN = 1'b0;
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I_BT = 1'b0;
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I_BC = 1'b0;
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I_BTR = 1'b0;
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I_RLD = 1'b0;
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I_RRD = 1'b0;
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I_INRC = 1'b0;
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SetDI = 1'b0;
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SetEI = 1'b0;
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IMode = 2'b11;
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Halt = 1'b0;
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NoRead = 1'b0;
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Write = 1'b0;
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//----------------------------------------------------------------------------
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//
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// CB prefixed instructions
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//
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//----------------------------------------------------------------------------
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Set_BusA_To[2:0] = IR[2:0];
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Set_BusB_To[2:0] = IR[2:0];
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case (IRB)
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8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
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8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
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8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
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8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
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8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
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8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111,
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8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111,
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8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 :
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begin
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// RLC r
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// RL r
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// RRC r
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// RR r
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// SLA r
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// SRA r
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// SRL r
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// SLL r (Undocumented) / SWAP r
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if (MCycle[0] ) begin
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ALU_Op = 4'b1000;
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Read_To_Reg = 1'b1;
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Save_ALU = 1'b1;
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end
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end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
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8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 :
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begin
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// RLC (HL)
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// RL (HL)
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// RRC (HL)
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// RR (HL)
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// SRA (HL)
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// SRL (HL)
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// SLA (HL)
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// SLL (HL) (Undocumented) / SWAP (HL)
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MCycles = 3'b011;
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case (1'b1) // MCycle
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MCycle[0], MCycle[6] :
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Set_Addr_To = aXY;
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MCycle[1] :
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begin
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ALU_Op = 4'b1000;
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Read_To_Reg = 1'b1;
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Save_ALU = 1'b1;
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Set_Addr_To = aXY;
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TStates = 3'b100;
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end
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MCycle[2] :
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Write = 1'b1;
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default :;
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endcase // case(MCycle)
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end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
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| 275 |
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8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
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8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
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| 277 |
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8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
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| 278 |
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8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
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8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
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| 280 |
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8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
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| 281 |
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8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
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8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
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| 283 |
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begin
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| 284 |
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// BIT b,r
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| 285 |
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if (MCycle[0] )
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| 286 |
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begin
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| 287 |
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Set_BusB_To[2:0] = IR[2:0];
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| 288 |
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ALU_Op = 4'b1001;
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| 289 |
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end
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| 290 |
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end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
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| 291 |
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| 292 |
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8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 :
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| 293 |
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begin
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| 294 |
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// BIT b,(HL)
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| 295 |
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MCycles = 3'b010;
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| 296 |
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case (1'b1) // MCycle
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| 297 |
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MCycle[0], MCycle[6] :
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| 298 |
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Set_Addr_To = aXY;
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| 299 |
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MCycle[1] :
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| 300 |
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begin
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| 301 |
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ALU_Op = 4'b1001;
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| 302 |
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TStates = 3'b100;
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| 303 |
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end
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| 304 |
|
|
|
| 305 |
|
|
default :;
|
| 306 |
|
|
endcase // case(MCycle)
|
| 307 |
|
|
end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110
|
| 308 |
|
|
|
| 309 |
|
|
8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,
|
| 310 |
|
|
8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111,
|
| 311 |
|
|
8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111,
|
| 312 |
|
|
8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111,
|
| 313 |
|
|
8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111,
|
| 314 |
|
|
8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
|
| 315 |
|
|
8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
|
| 316 |
|
|
8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
|
| 317 |
|
|
begin
|
| 318 |
|
|
// SET b,r
|
| 319 |
|
|
if (MCycle[0] )
|
| 320 |
|
|
begin
|
| 321 |
|
|
ALU_Op = 4'b1010;
|
| 322 |
|
|
Read_To_Reg = 1'b1;
|
| 323 |
|
|
Save_ALU = 1'b1;
|
| 324 |
|
|
end
|
| 325 |
|
|
end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,...
|
| 326 |
|
|
|
| 327 |
|
|
8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 :
|
| 328 |
|
|
begin
|
| 329 |
|
|
// SET b,(HL)
|
| 330 |
|
|
MCycles = 3'b011;
|
| 331 |
|
|
case (1'b1) // MCycle
|
| 332 |
|
|
MCycle[0], MCycle[6] :
|
| 333 |
|
|
Set_Addr_To = aXY;
|
| 334 |
|
|
MCycle[1] :
|
| 335 |
|
|
begin
|
| 336 |
|
|
ALU_Op = 4'b1010;
|
| 337 |
|
|
Read_To_Reg = 1'b1;
|
| 338 |
|
|
Save_ALU = 1'b1;
|
| 339 |
|
|
Set_Addr_To = aXY;
|
| 340 |
|
|
TStates = 3'b100;
|
| 341 |
|
|
end
|
| 342 |
|
|
MCycle[2] :
|
| 343 |
|
|
Write = 1'b1;
|
| 344 |
|
|
default :;
|
| 345 |
|
|
endcase // case(MCycle)
|
| 346 |
|
|
end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
|
| 347 |
|
|
|
| 348 |
|
|
8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
|
| 349 |
|
|
8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
|
| 350 |
|
|
8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
|
| 351 |
|
|
8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
|
| 352 |
|
|
8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
|
| 353 |
|
|
8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
|
| 354 |
|
|
8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
|
| 355 |
|
|
8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
|
| 356 |
|
|
begin
|
| 357 |
|
|
// RES b,r
|
| 358 |
|
|
if (MCycle[0] )
|
| 359 |
|
|
begin
|
| 360 |
|
|
ALU_Op = 4'b1011;
|
| 361 |
|
|
Read_To_Reg = 1'b1;
|
| 362 |
|
|
Save_ALU = 1'b1;
|
| 363 |
|
|
end
|
| 364 |
|
|
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
|
| 365 |
|
|
|
| 366 |
|
|
8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 :
|
| 367 |
|
|
begin
|
| 368 |
|
|
// RES b,(HL)
|
| 369 |
|
|
MCycles = 3'b011;
|
| 370 |
|
|
case (1'b1) // MCycle
|
| 371 |
|
|
MCycle[0], MCycle[6] :
|
| 372 |
|
|
Set_Addr_To = aXY;
|
| 373 |
|
|
MCycle[1] :
|
| 374 |
|
|
begin
|
| 375 |
|
|
ALU_Op = 4'b1011;
|
| 376 |
|
|
Read_To_Reg = 1'b1;
|
| 377 |
|
|
Save_ALU = 1'b1;
|
| 378 |
|
|
Set_Addr_To = aXY;
|
| 379 |
|
|
TStates = 3'b100;
|
| 380 |
|
|
end
|
| 381 |
|
|
|
| 382 |
|
|
MCycle[2] :
|
| 383 |
|
|
Write = 1'b1;
|
| 384 |
|
|
default :;
|
| 385 |
|
|
endcase // case(MCycle)
|
| 386 |
|
|
end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
|
| 387 |
|
|
|
| 388 |
|
|
endcase // case(IRB)
|
| 389 |
|
|
|
| 390 |
|
|
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
|
| 391 |
|
|
|
| 392 |
|
|
assign output_vector = { MCycles,
|
| 393 |
|
|
TStates,
|
| 394 |
|
|
Prefix,
|
| 395 |
|
|
Inc_PC,
|
| 396 |
|
|
Inc_WZ,
|
| 397 |
|
|
IncDec_16,
|
| 398 |
|
|
Read_To_Reg,
|
| 399 |
|
|
Read_To_Acc,
|
| 400 |
|
|
Set_BusA_To,
|
| 401 |
|
|
Set_BusB_To,
|
| 402 |
|
|
ALU_Op,
|
| 403 |
|
|
Save_ALU,
|
| 404 |
|
|
PreserveC,
|
| 405 |
|
|
Arith16,
|
| 406 |
|
|
Set_Addr_To,
|
| 407 |
|
|
IORQ,
|
| 408 |
|
|
Jump,
|
| 409 |
|
|
JumpE,
|
| 410 |
|
|
JumpXY,
|
| 411 |
|
|
Call,
|
| 412 |
|
|
RstP,
|
| 413 |
|
|
LDZ,
|
| 414 |
|
|
LDW,
|
| 415 |
|
|
LDSPHL,
|
| 416 |
|
|
Special_LD,
|
| 417 |
|
|
ExchangeDH,
|
| 418 |
|
|
ExchangeRp,
|
| 419 |
|
|
ExchangeAF,
|
| 420 |
|
|
ExchangeRS,
|
| 421 |
|
|
I_DJNZ,
|
| 422 |
|
|
I_CPL,
|
| 423 |
|
|
I_CCF,
|
| 424 |
|
|
I_SCF,
|
| 425 |
|
|
I_RETN,
|
| 426 |
|
|
I_BT,
|
| 427 |
|
|
I_BC,
|
| 428 |
|
|
I_BTR,
|
| 429 |
|
|
I_RLD,
|
| 430 |
|
|
I_RRD,
|
| 431 |
|
|
I_INRC,
|
| 432 |
|
|
SetDI,
|
| 433 |
|
|
SetEI,
|
| 434 |
|
|
IMode,
|
| 435 |
|
|
Halt,
|
| 436 |
|
|
NoRead,
|
| 437 |
|
|
Write };
|
| 438 |
|
|
|
| 439 |
|
|
// synopsys dc_script_begin
|
| 440 |
|
|
// set_attribute current_design "revision" "$Id: tv80_mcode_cb.v,v 1.1.2.1 2004-11-30 21:58:10 ghutchis Exp $" -type string -quiet
|
| 441 |
|
|
// synopsys dc_script_end
|
| 442 |
|
|
endmodule // T80_MCode
|
