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//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a 
// copy of this software and associated documentation files (the "Software"), 
// to deal in the Software without restriction, including without limitation 
// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
// and/or sell copies of the Software, and to permit persons to whom the 
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included 
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
module tv80_mcode_ed
  (/*AUTOARG*/
  // Outputs
  output_vector,
  // Inputs
  IR, MCycle
  );
 
  parameter             Mode   = 0;
  parameter             Flag_C = 0;
  parameter             Flag_N = 1;
  parameter             Flag_P = 2;
  parameter             Flag_X = 3;
  parameter             Flag_H = 4;
  parameter             Flag_Y = 5;
  parameter             Flag_Z = 6;
  parameter             Flag_S = 7;
 
  output [67:0]         output_vector;
 
  input [7:0]            IR;
  input [6:0]            MCycle                  ;
 
  // regs
  reg [2:0]             MCycles                 ;
  reg [2:0]             TStates                 ;
  reg [1:0]             Prefix                  ; // None,BC,ED,DD/FD
  reg                   Inc_PC                  ;
  reg                   Inc_WZ                  ;
  reg [3:0]             IncDec_16               ; // BC,DE,HL,SP   0 is inc
  reg                   Read_To_Reg             ;
  reg                   Read_To_Acc             ;
  reg [3:0]             Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
  reg [3:0]             Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
  reg [3:0]             ALU_Op                  ;
  reg                   Save_ALU                ;
  reg                   PreserveC               ;
  reg                   Arith16                 ;
  reg [2:0]             Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
  reg                   IORQ                    ;
  reg                   Jump                    ;
  reg                   JumpE                   ;
  reg                   JumpXY                  ;
  reg                   Call                    ;
  reg                   RstP                    ;
  reg                   LDZ                     ;
  reg                   LDW                     ;
  reg                   LDSPHL                  ;
  reg [2:0]             Special_LD              ; // A,I;A,R;I,A;R,A;None
  reg                   ExchangeDH              ;
  reg                   ExchangeRp              ;
  reg                   ExchangeAF              ;
  reg                   ExchangeRS              ;
  reg                   I_DJNZ                  ;
  reg                   I_CPL                   ;
  reg                   I_CCF                   ;
  reg                   I_SCF                   ;
  reg                   I_RETN                  ;
  reg                   I_BT                    ;
  reg                   I_BC                    ;
  reg                   I_BTR                   ;
  reg                   I_RLD                   ;
  reg                   I_RRD                   ;
  reg                   I_INRC                  ;
  reg                   SetDI                   ;
  reg                   SetEI                   ;
  reg [1:0]             IMode                   ;
  reg                   Halt                    ;
  reg                   NoRead                  ;
  reg                   Write   ;
 
  parameter             aNone   = 3'b111;
  parameter             aBC     = 3'b000;
  parameter             aDE     = 3'b001;
  parameter             aXY     = 3'b010;
  parameter             aIOA    = 3'b100;
  parameter             aSP     = 3'b101;
  parameter             aZI     = 3'b110;
 
 
  reg [2:0] DDD;
  reg [2:0] SSS;
  reg [1:0] DPAIR;
  reg [7:0] IRB;
 
  always @ (/*AUTOSENSE*/IR or MCycle)
    begin
      DDD = IR[5:3];
      SSS = IR[2:0];
      DPAIR = IR[5:4];
      IRB = IR;
 
      MCycles = 3'b001;
      if (MCycle[0] )
        begin
          TStates = 3'b100;
        end
      else
        begin
          TStates = 3'b011;
        end
      Prefix = 2'b00;
      Inc_PC = 1'b0;
      Inc_WZ = 1'b0;
      IncDec_16 = 4'b0000;
      Read_To_Acc = 1'b0;
      Read_To_Reg = 1'b0;
      Set_BusB_To = 4'b0000;
      Set_BusA_To = 4'b0000;
      ALU_Op = { 1'b0, IR[5:3] };
      Save_ALU = 1'b0;
      PreserveC = 1'b0;
      Arith16 = 1'b0;
      IORQ = 1'b0;
      Set_Addr_To = aNone;
      Jump = 1'b0;
      JumpE = 1'b0;
      JumpXY = 1'b0;
      Call = 1'b0;
      RstP = 1'b0;
      LDZ = 1'b0;
      LDW = 1'b0;
      LDSPHL = 1'b0;
      Special_LD = 3'b000;
      ExchangeDH = 1'b0;
      ExchangeRp = 1'b0;
      ExchangeAF = 1'b0;
      ExchangeRS = 1'b0;
      I_DJNZ = 1'b0;
      I_CPL = 1'b0;
      I_CCF = 1'b0;
      I_SCF = 1'b0;
      I_RETN = 1'b0;
      I_BT = 1'b0;
      I_BC = 1'b0;
      I_BTR = 1'b0;
      I_RLD = 1'b0;
      I_RRD = 1'b0;
      I_INRC = 1'b0;
      SetDI = 1'b0;
      SetEI = 1'b0;
      IMode = 2'b11;
      Halt = 1'b0;
      NoRead = 1'b0;
      Write = 1'b0;
 
      //----------------------------------------------------------------------------
      //
      //  ED prefixed instructions
      //
      //----------------------------------------------------------------------------
 
      casex (IRB)
        // 8 BIT LOAD GROUP
        8'b01010111  :
          begin
            // LD A,I
            Special_LD = 3'b100;
            TStates = 3'b101;
          end
 
        8'b01011111  :
          begin
            // LD A,R
            Special_LD = 3'b101;
            TStates = 3'b101;
          end
 
        8'b01000111  :
          begin
            // LD I,A
            Special_LD = 3'b110;
            TStates = 3'b101;
          end
 
        8'b01001111  :
          begin
            // LD R,A
            Special_LD = 3'b111;
            TStates = 3'b101;
          end
 
        // 16 BIT LOAD GROUP
        8'b01xx1011 :
          begin
            // LD dd,(nn)
            MCycles = 3'b101;
            case (1'b1) // MCycle
              MCycle[1] :
                begin
                  Inc_PC = 1'b1;
                  LDZ = 1'b1;
                end
 
              MCycle[2] :
                begin
                  Set_Addr_To = aZI;
                  Inc_PC = 1'b1;
                  LDW = 1'b1;
                end
 
              MCycle[3] :
                begin
                  Read_To_Reg = 1'b1;
                  if (IR[5:4] == 2'b11 )
                    begin
                      Set_BusA_To = 4'b1000;
                    end
                  else
                    begin
                      Set_BusA_To[2:1] = IR[5:4];
                      Set_BusA_To[0] = 1'b1;
                    end
                  Inc_WZ = 1'b1;
                  Set_Addr_To = aZI;
                end // case: 4
 
              MCycle[4] :
                begin
                  Read_To_Reg = 1'b1;
                  if (IR[5:4] == 2'b11 )
                    begin
                      Set_BusA_To = 4'b1001;
                    end
                  else
                    begin
                      Set_BusA_To[2:1] = IR[5:4];
                      Set_BusA_To[0] = 1'b0;
                    end
                end // case: 5
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011
 
 
        8'b01xx0011  :
          begin
            // LD (nn),dd
            MCycles = 3'b101;
            case (1'b1) // MCycle
              MCycle[1] :
                begin
                  Inc_PC = 1'b1;
                  LDZ = 1'b1;
                end
 
              MCycle[2] :
                begin
                  Set_Addr_To = aZI;
                  Inc_PC = 1'b1;
                  LDW = 1'b1;
                  if (IR[5:4] == 2'b11 )
                    begin
                      Set_BusB_To = 4'b1000;
                    end
                  else
                    begin
                      Set_BusB_To[2:1] = IR[5:4];
                      Set_BusB_To[0] = 1'b1;
                      Set_BusB_To[3] = 1'b0;
                    end
                end // case: 3
 
              MCycle[3] :
                begin
                  Inc_WZ = 1'b1;
                  Set_Addr_To = aZI;
                  Write = 1'b1;
                  if (IR[5:4] == 2'b11 )
                    begin
                      Set_BusB_To = 4'b1001;
                    end
                  else
                    begin
                      Set_BusB_To[2:1] = IR[5:4];
                      Set_BusB_To[0] = 1'b0;
                      Set_BusB_To[3] = 1'b0;
                    end
                end // case: 4
 
              MCycle[4] :
                begin
                  Write = 1'b1;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011
 
        8'b101xx000 :
          begin
            // LDI, LDD, LDIR, LDDR
            MCycles = 3'b100;
            case (1'b1) // MCycle
              MCycle[0] :
                begin
                  Set_Addr_To = aXY;
                  IncDec_16 = 4'b1100; // BC
                end
 
              MCycle[1] :
                begin
                  Set_BusB_To = 4'b0110;
                  Set_BusA_To[2:0] = 3'b111;
                  ALU_Op = 4'b0000;
                  Set_Addr_To = aDE;
                  if (IR[3] == 1'b0 )
                    begin
                      IncDec_16 = 4'b0110; // IX
                    end
                  else
                    begin
                      IncDec_16 = 4'b1110;
                    end
                end // case: 2
 
              MCycle[2] :
                begin
                  I_BT = 1'b1;
                  TStates = 3'b101;
                  Write = 1'b1;
                  if (IR[3] == 1'b0 )
                    begin
                      IncDec_16 = 4'b0101; // DE
                    end
                  else
                    begin
                      IncDec_16 = 4'b1101;
                    end
                end // case: 3
 
              MCycle[3] :
                begin
                  NoRead = 1'b1;
                  TStates = 3'b101;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000
 
        8'b101xx001 :
          begin
            // CPI, CPD, CPIR, CPDR
            MCycles = 3'b100;
            case (1'b1) // MCycle
              MCycle[0] :
                begin
                  Set_Addr_To = aXY;
                  IncDec_16 = 4'b1100; // BC
                end
 
              MCycle[1] :
                begin
                  Set_BusB_To = 4'b0110;
                  Set_BusA_To[2:0] = 3'b111;
                  ALU_Op = 4'b0111;
                  Save_ALU = 1'b1;
                  PreserveC = 1'b1;
                  if (IR[3] == 1'b0 )
                    begin
                      IncDec_16 = 4'b0110;
                    end
                  else
                    begin
                      IncDec_16 = 4'b1110;
                    end
                end // case: 2
 
              MCycle[2] :
                begin
                  NoRead = 1'b1;
                  I_BC = 1'b1;
                  TStates = 3'b101;
                end
 
              MCycle[3] :
                begin
                  NoRead = 1'b1;
                  TStates = 3'b101;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001
 
        8'b01xxx100 :
          begin
            // NEG
            ALU_Op = 4'b0010;
            Set_BusB_To = 4'b0111;
            Set_BusA_To = 4'b1010;
            Read_To_Acc = 1'b1;
            Save_ALU = 1'b1;
          end
 
        8'b01000110,8'b01001110,8'b01100110,8'b01101110  :
          begin
            // IM 0
            IMode = 2'b00;
          end
 
        8'b01010110,8'b01110110  :
          // IM 1
          IMode = 2'b01;
 
        8'b01011110,8'b01110111  :
          // IM 2
          IMode = 2'b10;
 
        // 16 bit arithmetic
        8'b01001010,8'b01011010,8'b01101010,8'b01111010  :
          begin
            // ADC HL,ss
            MCycles = 3'b011;
            case (1'b1) // MCycle
              MCycle[1] :
                begin
                  NoRead = 1'b1;
                  ALU_Op = 4'b0001;
                  Read_To_Reg = 1'b1;
                  Save_ALU = 1'b1;
                  Set_BusA_To[2:0] = 3'b101;
                  case (IR[5:4])
                    0,1,2  :
                      begin
                        Set_BusB_To[2:1] = IR[5:4];
                        Set_BusB_To[0] = 1'b1;
                      end
                    default :
                      Set_BusB_To = 4'b1000;
                  endcase
                  TStates = 3'b100;
                end // case: 2
 
              MCycle[2] :
                begin
                  NoRead = 1'b1;
                  Read_To_Reg = 1'b1;
                  Save_ALU = 1'b1;
                  ALU_Op = 4'b0001;
                  Set_BusA_To[2:0] = 3'b100;
                  case (IR[5:4])
                    0,1,2  :
                      begin
                        Set_BusB_To[2:1] = IR[5:4];
                        Set_BusB_To[0] = 1'b0;
                      end
                    default :
                      Set_BusB_To = 4'b1001;
                  endcase // case(IR[5:4])
                end // case: 3
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010
 
        8'b01000010,8'b01010010,8'b01100010,8'b01110010  :
          begin
            // SBC HL,ss
            MCycles = 3'b011;
            case (1'b1) // MCycle
              MCycle[1] :
                begin
                  NoRead = 1'b1;
                  ALU_Op = 4'b0011;
                  Read_To_Reg = 1'b1;
                  Save_ALU = 1'b1;
                  Set_BusA_To[2:0] = 3'b101;
                  case (IR[5:4])
                    0,1,2  :
                      begin
                        Set_BusB_To[2:1] = IR[5:4];
                        Set_BusB_To[0] = 1'b1;
                      end
                    default :
                      Set_BusB_To = 4'b1000;
                  endcase
                  TStates = 3'b100;
                end // case: 2
 
              MCycle[2] :
                begin
                  NoRead = 1'b1;
                  ALU_Op = 4'b0011;
                  Read_To_Reg = 1'b1;
                  Save_ALU = 1'b1;
                  Set_BusA_To[2:0] = 3'b100;
                  case (IR[5:4])
                    0,1,2  :
                      Set_BusB_To[2:1] = IR[5:4];
                    default :
                      Set_BusB_To = 4'b1001;
                  endcase
                end // case: 3
 
              default :;
 
            endcase // case(MCycle)
          end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010
 
        8'b01101111  :
          begin
            // RLD
            MCycles = 3'b100;
            case (1'b1) // MCycle
              MCycle[1] :
                begin
                  NoRead = 1'b1;
                  Set_Addr_To = aXY;
                end
 
              MCycle[2] :
                begin
                  Read_To_Reg = 1'b1;
                  Set_BusB_To[2:0] = 3'b110;
                  Set_BusA_To[2:0] = 3'b111;
                  ALU_Op = 4'b1101;
                  TStates = 3'b100;
                  Set_Addr_To = aXY;
                  Save_ALU = 1'b1;
                end
 
              MCycle[3] :
                begin
                  I_RLD = 1'b1;
                  Write = 1'b1;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b01101111
 
        8'b01100111  :
          begin
            // RRD
            MCycles = 3'b100;
            case (1'b1) // MCycle
              MCycle[1] :
                Set_Addr_To = aXY;
              MCycle[2] :
                begin
                  Read_To_Reg = 1'b1;
                  Set_BusB_To[2:0] = 3'b110;
                  Set_BusA_To[2:0] = 3'b111;
                  ALU_Op = 4'b1110;
                  TStates = 3'b100;
                  Set_Addr_To = aXY;
                  Save_ALU = 1'b1;
                end
 
              MCycle[3] :
                begin
                  I_RRD = 1'b1;
                  Write = 1'b1;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b01100111
 
        8'b01xxx101 :
          begin
            // RETI, RETN
            MCycles = 3'b011;
            case (1'b1) // MCycle
              MCycle[0] :
                Set_Addr_To = aSP;
 
              MCycle[1] :
                begin
                  IncDec_16 = 4'b0111;
                  Set_Addr_To = aSP;
                  LDZ = 1'b1;
                end
 
              MCycle[2] :
                begin
                  Jump = 1'b1;
                  IncDec_16 = 4'b0111;
                  I_RETN = 1'b1;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101
 
        8'b01xxx000 :
          begin
            // IN r,(C)
            MCycles = 3'b010;
            case (1'b1) // MCycle
              MCycle[0] :
                Set_Addr_To = aBC;
 
              MCycle[1] :
                begin
                  IORQ = 1'b1;
                  if (IR[5:3] != 3'b110 )
                    begin
                      Read_To_Reg = 1'b1;
                      Set_BusA_To[2:0] = IR[5:3];
                    end
                  I_INRC = 1'b1;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000
 
        8'b01xxx001 :
          begin
            // OUT (C),r
            // OUT (C),0
            MCycles = 3'b010;
            case (1'b1) // MCycle
              MCycle[0] :
                begin
                  Set_Addr_To = aBC;
                  Set_BusB_To[2:0]        = IR[5:3];
                  if (IR[5:3] == 3'b110 )
                    begin
                      Set_BusB_To[3] = 1'b1;
                    end
                end
 
              MCycle[1] :
                begin
                  Write = 1'b1;
                  IORQ = 1'b1;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001
 
        8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010  :
          begin
            // INI, IND, INIR, INDR
            MCycles = 3'b100;
            case (1'b1) // MCycle
              MCycle[0] :
                begin
                  Set_Addr_To = aBC;
                  Set_BusB_To = 4'b1010;
                  Set_BusA_To = 4'b0000;
                  Read_To_Reg = 1'b1;
                  Save_ALU = 1'b1;
                  ALU_Op = 4'b0010;
                end
 
              MCycle[1] :
                begin
                  IORQ = 1'b1;
                  Set_BusB_To = 4'b0110;
                  Set_Addr_To = aXY;
                end
 
              MCycle[2] :
                begin
                  if (IR[3] == 1'b0 )
                    begin
                      IncDec_16 = 4'b0110;
                    end
                  else
                    begin
                      IncDec_16 = 4'b1110;
                    end
                  TStates = 3'b100;
                  Write = 1'b1;
                  I_BTR = 1'b1;
                end // case: 3
 
              MCycle[3] :
                begin
                  NoRead = 1'b1;
                  TStates = 3'b101;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010
 
        8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011  :
          begin
            // OUTI, OUTD, OTIR, OTDR
            MCycles = 3'b100;
            case (1'b1) // MCycle
              MCycle[0] :
                begin
                  TStates = 3'b101;
                  Set_Addr_To = aXY;
                  Set_BusB_To = 4'b1010;
                  Set_BusA_To = 4'b0000;
                  Read_To_Reg = 1'b1;
                  Save_ALU = 1'b1;
                  ALU_Op = 4'b0010;
                end
 
              MCycle[1] :
                begin
                  Set_BusB_To = 4'b0110;
                  Set_Addr_To = aBC;
                  if (IR[3] == 1'b0 )
                    begin
                      IncDec_16 = 4'b0110;
                    end
                  else
                    begin
                      IncDec_16 = 4'b1110;
                    end
                end
 
              MCycle[2] :
                begin
                  if (IR[3] == 1'b0 )
                    begin
                      IncDec_16 = 4'b0010;
                    end
                  else
                    begin
                      IncDec_16 = 4'b1010;
                    end
                  IORQ = 1'b1;
                  Write = 1'b1;
                  I_BTR = 1'b1;
                end // case: 3
 
              MCycle[3] :
                begin
                  NoRead = 1'b1;
                  TStates = 3'b101;
                end
 
              default :;
            endcase // case(MCycle)
          end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
 
        default : ;
 
      endcase // case(IRB)                  
 
    end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
 
  assign                output_vector = { MCycles,
                                          TStates,
                                          Prefix,
                                          Inc_PC,
                                          Inc_WZ,
                                          IncDec_16,
                                          Read_To_Reg,
                                          Read_To_Acc,
                                          Set_BusA_To,
                                          Set_BusB_To,
                                          ALU_Op,
                                          Save_ALU,
                                          PreserveC,
                                          Arith16,
                                          Set_Addr_To,
                                          IORQ,
                                          Jump,
                                          JumpE,
                                          JumpXY,
                                          Call,
                                          RstP,
                                          LDZ,
                                          LDW,
                                          LDSPHL,
                                          Special_LD,
                                          ExchangeDH,
                                          ExchangeRp,
                                          ExchangeAF,
                                          ExchangeRS,
                                          I_DJNZ,
                                          I_CPL,
                                          I_CCF,
                                          I_SCF,
                                          I_RETN,
                                          I_BT,
                                          I_BC,
                                          I_BTR,
                                          I_RLD,
                                          I_RRD,
                                          I_INRC,
                                          SetDI,
                                          SetEI,
                                          IMode,
                                          Halt,
                                          NoRead,
                                          Write };
 
  // synopsys dc_script_begin
  // set_attribute current_design "revision" "$Id: tv80_mcode_ed.v,v 1.1.2.1 2004-11-30 21:58:10 ghutchis Exp $" -type string -quiet
  // synopsys dc_script_end
endmodule // T80_MCode

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Line No.	Rev	Author	Line
1	48	ghutchis	`//`
2			`// TV80 8-Bit Microprocessor Core`
3			`// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)`
4			`//`
5			`// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)`
6			`//`
7			`// Permission is hereby granted, free of charge, to any person obtaining a`
8			`// copy of this software and associated documentation files (the "Software"),`
9			`// to deal in the Software without restriction, including without limitation`
10			`// the rights to use, copy, modify, merge, publish, distribute, sublicense,`
11			`// and/or sell copies of the Software, and to permit persons to whom the`
12			`// Software is furnished to do so, subject to the following conditions:`
13			`//`
14			`// The above copyright notice and this permission notice shall be included`
15			`// in all copies or substantial portions of the Software.`
16			`//`
17			`// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,`
18			`// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF`
19			`// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.`
20			`// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY`
21			`// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,`
22			`// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE`
23			`// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.`
24
25			`module tv80_mcode_ed`
26			`(/AUTOARG/`
27			`// Outputs`
28			`output_vector,`
29			`// Inputs`
30			`IR, MCycle`
31			`);`
32
33			`parameter Mode = 0;`
34			`parameter Flag_C = 0;`
35			`parameter Flag_N = 1;`
36			`parameter Flag_P = 2;`
37			`parameter Flag_X = 3;`
38			`parameter Flag_H = 4;`
39			`parameter Flag_Y = 5;`
40			`parameter Flag_Z = 6;`
41			`parameter Flag_S = 7;`
42
43			`output [67:0] output_vector;`
44
45			`input [7:0] IR;`
46			`input [6:0] MCycle ;`
47
48			`// regs`
49			`reg [2:0] MCycles ;`
50			`reg [2:0] TStates ;`
51			`reg [1:0] Prefix ; // None,BC,ED,DD/FD`
52			`reg Inc_PC ;`
53			`reg Inc_WZ ;`
54			`reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc`
55			`reg Read_To_Reg ;`
56			`reg Read_To_Acc ;`
57			`reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F`
58			`reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0`
59			`reg [3:0] ALU_Op ;`
60			`reg Save_ALU ;`
61			`reg PreserveC ;`
62			`reg Arith16 ;`
63			`reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI`
64			`reg IORQ ;`
65			`reg Jump ;`
66			`reg JumpE ;`
67			`reg JumpXY ;`
68			`reg Call ;`
69			`reg RstP ;`
70			`reg LDZ ;`
71			`reg LDW ;`
72			`reg LDSPHL ;`
73			`reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None`
74			`reg ExchangeDH ;`
75			`reg ExchangeRp ;`
76			`reg ExchangeAF ;`
77			`reg ExchangeRS ;`
78			`reg I_DJNZ ;`
79			`reg I_CPL ;`
80			`reg I_CCF ;`
81			`reg I_SCF ;`
82			`reg I_RETN ;`
83			`reg I_BT ;`
84			`reg I_BC ;`
85			`reg I_BTR ;`
86			`reg I_RLD ;`
87			`reg I_RRD ;`
88			`reg I_INRC ;`
89			`reg SetDI ;`
90			`reg SetEI ;`
91			`reg [1:0] IMode ;`
92			`reg Halt ;`
93			`reg NoRead ;`
94			`reg Write ;`
95
96			`parameter aNone = 3'b111;`
97			`parameter aBC = 3'b000;`
98			`parameter aDE = 3'b001;`
99			`parameter aXY = 3'b010;`
100			`parameter aIOA = 3'b100;`
101			`parameter aSP = 3'b101;`
102			`parameter aZI = 3'b110;`
103
104
105			`reg [2:0] DDD;`
106			`reg [2:0] SSS;`
107			`reg [1:0] DPAIR;`
108			`reg [7:0] IRB;`
109
110			`always @ (/AUTOSENSE/IR or MCycle)`
111			`begin`
112			`DDD = IR[5:3];`
113			`SSS = IR[2:0];`
114			`DPAIR = IR[5:4];`
115			`IRB = IR;`
116
117			`MCycles = 3'b001;`
118			`if (MCycle[0] )`
119			`begin`
120			`TStates = 3'b100;`
121			`end`
122			`else`
123			`begin`
124			`TStates = 3'b011;`
125			`end`
126			`Prefix = 2'b00;`
127			`Inc_PC = 1'b0;`
128			`Inc_WZ = 1'b0;`
129			`IncDec_16 = 4'b0000;`
130			`Read_To_Acc = 1'b0;`
131			`Read_To_Reg = 1'b0;`
132			`Set_BusB_To = 4'b0000;`
133			`Set_BusA_To = 4'b0000;`
134			`ALU_Op = { 1'b0, IR[5:3] };`
135			`Save_ALU = 1'b0;`
136			`PreserveC = 1'b0;`
137			`Arith16 = 1'b0;`
138			`IORQ = 1'b0;`
139			`Set_Addr_To = aNone;`
140			`Jump = 1'b0;`
141			`JumpE = 1'b0;`
142			`JumpXY = 1'b0;`
143			`Call = 1'b0;`
144			`RstP = 1'b0;`
145			`LDZ = 1'b0;`
146			`LDW = 1'b0;`
147			`LDSPHL = 1'b0;`
148			`Special_LD = 3'b000;`
149			`ExchangeDH = 1'b0;`
150			`ExchangeRp = 1'b0;`
151			`ExchangeAF = 1'b0;`
152			`ExchangeRS = 1'b0;`
153			`I_DJNZ = 1'b0;`
154			`I_CPL = 1'b0;`
155			`I_CCF = 1'b0;`
156			`I_SCF = 1'b0;`
157			`I_RETN = 1'b0;`
158			`I_BT = 1'b0;`
159			`I_BC = 1'b0;`
160			`I_BTR = 1'b0;`
161			`I_RLD = 1'b0;`
162			`I_RRD = 1'b0;`
163			`I_INRC = 1'b0;`
164			`SetDI = 1'b0;`
165			`SetEI = 1'b0;`
166			`IMode = 2'b11;`
167			`Halt = 1'b0;`
168			`NoRead = 1'b0;`
169			`Write = 1'b0;`
170
171			`//----------------------------------------------------------------------------`
172			`//`
173			`// ED prefixed instructions`
174			`//`
175			`//----------------------------------------------------------------------------`
176
177			`casex (IRB)`
178			`// 8 BIT LOAD GROUP`
179			`8'b01010111 :`
180			`begin`
181			`// LD A,I`
182			`Special_LD = 3'b100;`
183			`TStates = 3'b101;`
184			`end`
185
186			`8'b01011111 :`
187			`begin`
188			`// LD A,R`
189			`Special_LD = 3'b101;`
190			`TStates = 3'b101;`
191			`end`
192
193			`8'b01000111 :`
194			`begin`
195			`// LD I,A`
196			`Special_LD = 3'b110;`
197			`TStates = 3'b101;`
198			`end`
199
200			`8'b01001111 :`
201			`begin`
202			`// LD R,A`
203			`Special_LD = 3'b111;`
204			`TStates = 3'b101;`
205			`end`
206
207			`// 16 BIT LOAD GROUP`
208			`8'b01xx1011 :`
209			`begin`
210			`// LD dd,(nn)`
211			`MCycles = 3'b101;`
212			`case (1'b1) // MCycle`
213			`MCycle[1] :`
214			`begin`
215			`Inc_PC = 1'b1;`
216			`LDZ = 1'b1;`
217			`end`
218
219			`MCycle[2] :`
220			`begin`
221			`Set_Addr_To = aZI;`
222			`Inc_PC = 1'b1;`
223			`LDW = 1'b1;`
224			`end`
225
226			`MCycle[3] :`
227			`begin`
228			`Read_To_Reg = 1'b1;`
229			`if (IR[5:4] == 2'b11 )`
230			`begin`
231			`Set_BusA_To = 4'b1000;`
232			`end`
233			`else`
234			`begin`
235			`Set_BusA_To[2:1] = IR[5:4];`
236			`Set_BusA_To[0] = 1'b1;`
237			`end`
238			`Inc_WZ = 1'b1;`
239			`Set_Addr_To = aZI;`
240			`end // case: 4`
241
242			`MCycle[4] :`
243			`begin`
244			`Read_To_Reg = 1'b1;`
245			`if (IR[5:4] == 2'b11 )`
246			`begin`
247			`Set_BusA_To = 4'b1001;`
248			`end`
249			`else`
250			`begin`
251			`Set_BusA_To[2:1] = IR[5:4];`
252			`Set_BusA_To[0] = 1'b0;`
253			`end`
254			`end // case: 5`
255
256			`default :;`
257			`endcase // case(MCycle)`
258			`end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011`
259
260
261			`8'b01xx0011 :`
262			`begin`
263			`// LD (nn),dd`
264			`MCycles = 3'b101;`
265			`case (1'b1) // MCycle`
266			`MCycle[1] :`
267			`begin`
268			`Inc_PC = 1'b1;`
269			`LDZ = 1'b1;`
270			`end`
271
272			`MCycle[2] :`
273			`begin`
274			`Set_Addr_To = aZI;`
275			`Inc_PC = 1'b1;`
276			`LDW = 1'b1;`
277			`if (IR[5:4] == 2'b11 )`
278			`begin`
279			`Set_BusB_To = 4'b1000;`
280			`end`
281			`else`
282			`begin`
283			`Set_BusB_To[2:1] = IR[5:4];`
284			`Set_BusB_To[0] = 1'b1;`
285			`Set_BusB_To[3] = 1'b0;`
286			`end`
287			`end // case: 3`
288
289			`MCycle[3] :`
290			`begin`
291			`Inc_WZ = 1'b1;`
292			`Set_Addr_To = aZI;`
293			`Write = 1'b1;`
294			`if (IR[5:4] == 2'b11 )`
295			`begin`
296			`Set_BusB_To = 4'b1001;`
297			`end`
298			`else`
299			`begin`
300			`Set_BusB_To[2:1] = IR[5:4];`
301			`Set_BusB_To[0] = 1'b0;`
302			`Set_BusB_To[3] = 1'b0;`
303			`end`
304			`end // case: 4`
305
306			`MCycle[4] :`
307			`begin`
308			`Write = 1'b1;`
309			`end`
310
311			`default :;`
312			`endcase // case(MCycle)`
313			`end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011`
314
315			`8'b101xx000 :`
316			`begin`
317			`// LDI, LDD, LDIR, LDDR`
318			`MCycles = 3'b100;`
319			`case (1'b1) // MCycle`
320			`MCycle[0] :`
321			`begin`
322			`Set_Addr_To = aXY;`
323			`IncDec_16 = 4'b1100; // BC`
324			`end`
325
326			`MCycle[1] :`
327			`begin`
328			`Set_BusB_To = 4'b0110;`
329			`Set_BusA_To[2:0] = 3'b111;`
330			`ALU_Op = 4'b0000;`
331			`Set_Addr_To = aDE;`
332			`if (IR[3] == 1'b0 )`
333			`begin`
334			`IncDec_16 = 4'b0110; // IX`
335			`end`
336			`else`
337			`begin`
338			`IncDec_16 = 4'b1110;`
339			`end`
340			`end // case: 2`
341
342			`MCycle[2] :`
343			`begin`
344			`I_BT = 1'b1;`
345			`TStates = 3'b101;`
346			`Write = 1'b1;`
347			`if (IR[3] == 1'b0 )`
348			`begin`
349			`IncDec_16 = 4'b0101; // DE`
350			`end`
351			`else`
352			`begin`
353			`IncDec_16 = 4'b1101;`
354			`end`
355			`end // case: 3`
356
357			`MCycle[3] :`
358			`begin`
359			`NoRead = 1'b1;`
360			`TStates = 3'b101;`
361			`end`
362
363			`default :;`
364			`endcase // case(MCycle)`
365			`end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000`
366
367			`8'b101xx001 :`
368			`begin`
369			`// CPI, CPD, CPIR, CPDR`
370			`MCycles = 3'b100;`
371			`case (1'b1) // MCycle`
372			`MCycle[0] :`
373			`begin`
374			`Set_Addr_To = aXY;`
375			`IncDec_16 = 4'b1100; // BC`
376			`end`
377
378			`MCycle[1] :`
379			`begin`
380			`Set_BusB_To = 4'b0110;`
381			`Set_BusA_To[2:0] = 3'b111;`
382			`ALU_Op = 4'b0111;`
383			`Save_ALU = 1'b1;`
384			`PreserveC = 1'b1;`
385			`if (IR[3] == 1'b0 )`
386			`begin`
387			`IncDec_16 = 4'b0110;`
388			`end`
389			`else`
390			`begin`
391			`IncDec_16 = 4'b1110;`
392			`end`
393			`end // case: 2`
394
395			`MCycle[2] :`
396			`begin`
397			`NoRead = 1'b1;`
398			`I_BC = 1'b1;`
399			`TStates = 3'b101;`
400			`end`
401
402			`MCycle[3] :`
403			`begin`
404			`NoRead = 1'b1;`
405			`TStates = 3'b101;`
406			`end`
407
408			`default :;`
409			`endcase // case(MCycle)`
410			`end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001`
411
412			`8'b01xxx100 :`
413			`begin`
414			`// NEG`
415			`ALU_Op = 4'b0010;`
416			`Set_BusB_To = 4'b0111;`
417			`Set_BusA_To = 4'b1010;`
418			`Read_To_Acc = 1'b1;`
419			`Save_ALU = 1'b1;`
420			`end`
421
422			`8'b01000110,8'b01001110,8'b01100110,8'b01101110 :`
423			`begin`
424			`// IM 0`
425			`IMode = 2'b00;`
426			`end`
427
428			`8'b01010110,8'b01110110 :`
429			`// IM 1`
430			`IMode = 2'b01;`
431
432			`8'b01011110,8'b01110111 :`
433			`// IM 2`
434			`IMode = 2'b10;`
435
436			`// 16 bit arithmetic`
437			`8'b01001010,8'b01011010,8'b01101010,8'b01111010 :`
438			`begin`
439			`// ADC HL,ss`
440			`MCycles = 3'b011;`
441			`case (1'b1) // MCycle`
442			`MCycle[1] :`
443			`begin`
444			`NoRead = 1'b1;`
445			`ALU_Op = 4'b0001;`
446			`Read_To_Reg = 1'b1;`
447			`Save_ALU = 1'b1;`
448			`Set_BusA_To[2:0] = 3'b101;`
449			`case (IR[5:4])`
450			`0,1,2 :`
451			`begin`
452			`Set_BusB_To[2:1] = IR[5:4];`
453			`Set_BusB_To[0] = 1'b1;`
454			`end`
455			`default :`
456			`Set_BusB_To = 4'b1000;`
457			`endcase`
458			`TStates = 3'b100;`
459			`end // case: 2`
460
461			`MCycle[2] :`
462			`begin`
463			`NoRead = 1'b1;`
464			`Read_To_Reg = 1'b1;`
465			`Save_ALU = 1'b1;`
466			`ALU_Op = 4'b0001;`
467			`Set_BusA_To[2:0] = 3'b100;`
468			`case (IR[5:4])`
469			`0,1,2 :`
470			`begin`
471			`Set_BusB_To[2:1] = IR[5:4];`
472			`Set_BusB_To[0] = 1'b0;`
473			`end`
474			`default :`
475			`Set_BusB_To = 4'b1001;`
476			`endcase // case(IR[5:4])`
477			`end // case: 3`
478
479			`default :;`
480			`endcase // case(MCycle)`
481			`end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010`
482
483			`8'b01000010,8'b01010010,8'b01100010,8'b01110010 :`
484			`begin`
485			`// SBC HL,ss`
486			`MCycles = 3'b011;`
487			`case (1'b1) // MCycle`
488			`MCycle[1] :`
489			`begin`
490			`NoRead = 1'b1;`
491			`ALU_Op = 4'b0011;`
492			`Read_To_Reg = 1'b1;`
493			`Save_ALU = 1'b1;`
494			`Set_BusA_To[2:0] = 3'b101;`
495			`case (IR[5:4])`
496			`0,1,2 :`
497			`begin`
498			`Set_BusB_To[2:1] = IR[5:4];`
499			`Set_BusB_To[0] = 1'b1;`
500			`end`
501			`default :`
502			`Set_BusB_To = 4'b1000;`
503			`endcase`
504			`TStates = 3'b100;`
505			`end // case: 2`
506
507			`MCycle[2] :`
508			`begin`
509			`NoRead = 1'b1;`
510			`ALU_Op = 4'b0011;`
511			`Read_To_Reg = 1'b1;`
512			`Save_ALU = 1'b1;`
513			`Set_BusA_To[2:0] = 3'b100;`
514			`case (IR[5:4])`
515			`0,1,2 :`
516			`Set_BusB_To[2:1] = IR[5:4];`
517			`default :`
518			`Set_BusB_To = 4'b1001;`
519			`endcase`
520			`end // case: 3`
521
522			`default :;`
523
524			`endcase // case(MCycle)`
525			`end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010`
526
527			`8'b01101111 :`
528			`begin`
529			`// RLD`
530			`MCycles = 3'b100;`
531			`case (1'b1) // MCycle`
532			`MCycle[1] :`
533			`begin`
534			`NoRead = 1'b1;`
535			`Set_Addr_To = aXY;`
536			`end`
537
538			`MCycle[2] :`
539			`begin`
540			`Read_To_Reg = 1'b1;`
541			`Set_BusB_To[2:0] = 3'b110;`
542			`Set_BusA_To[2:0] = 3'b111;`
543			`ALU_Op = 4'b1101;`
544			`TStates = 3'b100;`
545			`Set_Addr_To = aXY;`
546			`Save_ALU = 1'b1;`
547			`end`
548
549			`MCycle[3] :`
550			`begin`
551			`I_RLD = 1'b1;`
552			`Write = 1'b1;`
553			`end`
554
555			`default :;`
556			`endcase // case(MCycle)`
557			`end // case: 8'b01101111`
558
559			`8'b01100111 :`
560			`begin`
561			`// RRD`
562			`MCycles = 3'b100;`
563			`case (1'b1) // MCycle`
564			`MCycle[1] :`
565			`Set_Addr_To = aXY;`
566			`MCycle[2] :`
567			`begin`
568			`Read_To_Reg = 1'b1;`
569			`Set_BusB_To[2:0] = 3'b110;`
570			`Set_BusA_To[2:0] = 3'b111;`
571			`ALU_Op = 4'b1110;`
572			`TStates = 3'b100;`
573			`Set_Addr_To = aXY;`
574			`Save_ALU = 1'b1;`
575			`end`
576
577			`MCycle[3] :`
578			`begin`
579			`I_RRD = 1'b1;`
580			`Write = 1'b1;`
581			`end`
582
583			`default :;`
584			`endcase // case(MCycle)`
585			`end // case: 8'b01100111`
586
587			`8'b01xxx101 :`
588			`begin`
589			`// RETI, RETN`
590			`MCycles = 3'b011;`
591			`case (1'b1) // MCycle`
592			`MCycle[0] :`
593			`Set_Addr_To = aSP;`
594
595			`MCycle[1] :`
596			`begin`
597			`IncDec_16 = 4'b0111;`
598			`Set_Addr_To = aSP;`
599			`LDZ = 1'b1;`
600			`end`
601
602			`MCycle[2] :`
603			`begin`
604			`Jump = 1'b1;`
605			`IncDec_16 = 4'b0111;`
606			`I_RETN = 1'b1;`
607			`end`
608
609			`default :;`
610			`endcase // case(MCycle)`
611			`end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101`
612
613			`8'b01xxx000 :`
614			`begin`
615			`// IN r,(C)`
616			`MCycles = 3'b010;`
617			`case (1'b1) // MCycle`
618			`MCycle[0] :`
619			`Set_Addr_To = aBC;`
620
621			`MCycle[1] :`
622			`begin`
623			`IORQ = 1'b1;`
624			`if (IR[5:3] != 3'b110 )`
625			`begin`
626			`Read_To_Reg = 1'b1;`
627			`Set_BusA_To[2:0] = IR[5:3];`
628			`end`
629			`I_INRC = 1'b1;`
630			`end`
631
632			`default :;`
633			`endcase // case(MCycle)`
634			`end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000`
635
636			`8'b01xxx001 :`
637			`begin`
638			`// OUT (C),r`
639			`// OUT (C),0`
640			`MCycles = 3'b010;`
641			`case (1'b1) // MCycle`
642			`MCycle[0] :`
643			`begin`
644			`Set_Addr_To = aBC;`
645			`Set_BusB_To[2:0] = IR[5:3];`
646			`if (IR[5:3] == 3'b110 )`
647			`begin`
648			`Set_BusB_To[3] = 1'b1;`
649			`end`
650			`end`
651
652			`MCycle[1] :`
653			`begin`
654			`Write = 1'b1;`
655			`IORQ = 1'b1;`
656			`end`
657
658			`default :;`
659			`endcase // case(MCycle)`
660			`end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001`
661
662			`8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 :`
663			`begin`
664			`// INI, IND, INIR, INDR`
665			`MCycles = 3'b100;`
666			`case (1'b1) // MCycle`
667			`MCycle[0] :`
668			`begin`
669			`Set_Addr_To = aBC;`
670			`Set_BusB_To = 4'b1010;`
671			`Set_BusA_To = 4'b0000;`
672			`Read_To_Reg = 1'b1;`
673			`Save_ALU = 1'b1;`
674			`ALU_Op = 4'b0010;`
675			`end`
676
677			`MCycle[1] :`
678			`begin`
679			`IORQ = 1'b1;`
680			`Set_BusB_To = 4'b0110;`
681			`Set_Addr_To = aXY;`
682			`end`
683
684			`MCycle[2] :`
685			`begin`
686			`if (IR[3] == 1'b0 )`
687			`begin`
688			`IncDec_16 = 4'b0110;`
689			`end`
690			`else`
691			`begin`
692			`IncDec_16 = 4'b1110;`
693			`end`
694			`TStates = 3'b100;`
695			`Write = 1'b1;`
696			`I_BTR = 1'b1;`
697			`end // case: 3`
698
699			`MCycle[3] :`
700			`begin`
701			`NoRead = 1'b1;`
702			`TStates = 3'b101;`
703			`end`
704
705			`default :;`
706			`endcase // case(MCycle)`
707			`end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010`
708
709			`8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 :`
710			`begin`
711			`// OUTI, OUTD, OTIR, OTDR`
712			`MCycles = 3'b100;`
713			`case (1'b1) // MCycle`
714			`MCycle[0] :`
715			`begin`
716			`TStates = 3'b101;`
717			`Set_Addr_To = aXY;`
718			`Set_BusB_To = 4'b1010;`
719			`Set_BusA_To = 4'b0000;`
720			`Read_To_Reg = 1'b1;`
721			`Save_ALU = 1'b1;`
722			`ALU_Op = 4'b0010;`
723			`end`
724
725			`MCycle[1] :`
726			`begin`
727			`Set_BusB_To = 4'b0110;`
728			`Set_Addr_To = aBC;`
729			`if (IR[3] == 1'b0 )`
730			`begin`
731			`IncDec_16 = 4'b0110;`
732			`end`
733			`else`
734			`begin`
735			`IncDec_16 = 4'b1110;`
736			`end`
737			`end`
738
739			`MCycle[2] :`
740			`begin`
741			`if (IR[3] == 1'b0 )`
742			`begin`
743			`IncDec_16 = 4'b0010;`
744			`end`
745			`else`
746			`begin`
747			`IncDec_16 = 4'b1010;`
748			`end`
749			`IORQ = 1'b1;`
750			`Write = 1'b1;`
751			`I_BTR = 1'b1;`
752			`end // case: 3`
753
754			`MCycle[3] :`
755			`begin`
756			`NoRead = 1'b1;`
757			`TStates = 3'b101;`
758			`end`
759
760			`default :;`
761			`endcase // case(MCycle)`
762			`end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011`
763
764			`default : ;`
765
766			`endcase // case(IRB)`
767
768			`end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)`
769
770			`assign output_vector = { MCycles,`
771			`TStates,`
772			`Prefix,`
773			`Inc_PC,`
774			`Inc_WZ,`
775			`IncDec_16,`
776			`Read_To_Reg,`
777			`Read_To_Acc,`
778			`Set_BusA_To,`
779			`Set_BusB_To,`
780			`ALU_Op,`
781			`Save_ALU,`
782			`PreserveC,`
783			`Arith16,`
784			`Set_Addr_To,`
785			`IORQ,`
786			`Jump,`
787			`JumpE,`
788			`JumpXY,`
789			`Call,`
790			`RstP,`
791			`LDZ,`
792			`LDW,`
793			`LDSPHL,`
794			`Special_LD,`
795			`ExchangeDH,`
796			`ExchangeRp,`
797			`ExchangeAF,`
798			`ExchangeRS,`
799			`I_DJNZ,`
800			`I_CPL,`
801			`I_CCF,`
802			`I_SCF,`
803			`I_RETN,`
804			`I_BT,`
805			`I_BC,`
806			`I_BTR,`
807			`I_RLD,`
808			`I_RRD,`
809			`I_INRC,`
810			`SetDI,`
811			`SetEI,`
812			`IMode,`
813			`Halt,`
814			`NoRead,`
815			`Write };`
816
817			`// synopsys dc_script_begin`
818			`// set_attribute current_design "revision" "$Id: tv80_mcode_ed.v,v 1.1.2.1 2004-11-30 21:58:10 ghutchis Exp $" -type string -quiet`
819			`// synopsys dc_script_end`
820			`endmodule // T80_MCode`