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1 2 ghutchis
//
2
// TV80 8-Bit Microprocessor Core
3
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
4
//
5
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
6
//
7
// Permission is hereby granted, free of charge, to any person obtaining a 
8
// copy of this software and associated documentation files (the "Software"), 
9
// to deal in the Software without restriction, including without limitation 
10
// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
11
// and/or sell copies of the Software, and to permit persons to whom the 
12
// Software is furnished to do so, subject to the following conditions:
13
//
14
// The above copyright notice and this permission notice shall be included 
15
// in all copies or substantial portions of the Software.
16
//
17
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
18
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
19
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
20
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
21
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
22
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
23
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24
 
25
module tv80_mcode (/*AUTOARG*/
26
  // Outputs
27
  MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,
28
  Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,
29
  Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,
30
  LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,
31
  ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR,
32
  I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write,
33
  // Inputs
34
  IR, ISet, MCycle, F, NMICycle, IntCycle
35
  );
36
 
37
  parameter             Mode   = 0;
38
  parameter             Flag_C = 0;
39
  parameter             Flag_N = 1;
40
  parameter             Flag_P = 2;
41
  parameter             Flag_X = 3;
42
  parameter             Flag_H = 4;
43
  parameter             Flag_Y = 5;
44
  parameter             Flag_Z = 6;
45
  parameter             Flag_S = 7;
46
 
47
  input [7:0]           IR;
48
  input [1:0]           ISet                     ;
49
  input [2:0]           MCycle                   ;
50
  input [7:0]           F                        ;
51
  input                 NMICycle                ;
52
  input                 IntCycle                ;
53
  output [2:0]          MCycles                  ;
54
  output [2:0]          TStates                  ;
55
  output [1:0]          Prefix                   ; // None,BC,ED,DD/FD
56
  output                Inc_PC                  ;
57
  output                Inc_WZ                  ;
58
  output [3:0]          IncDec_16                ; // BC,DE,HL,SP   0 is inc
59
  output                Read_To_Reg             ;
60
  output                Read_To_Acc             ;
61
  output [3:0]          Set_BusA_To      ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
62
  output [3:0]          Set_BusB_To      ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
63
  output [3:0]          ALU_Op                   ;
64
  output                Save_ALU                ;
65
  output                PreserveC               ;
66
  output                Arith16                 ;
67
  output [2:0]          Set_Addr_To              ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
68
  output                IORQ                    ;
69
  output                Jump                    ;
70
  output                JumpE                   ;
71
  output                JumpXY                  ;
72
  output                Call                    ;
73
  output                RstP                    ;
74
  output                LDZ                     ;
75
  output                LDW                     ;
76
  output                LDSPHL                  ;
77
  output [2:0]          Special_LD               ; // A,I;A,R;I,A;R,A;None
78
  output                ExchangeDH              ;
79
  output                ExchangeRp              ;
80
  output                ExchangeAF              ;
81
  output                ExchangeRS              ;
82
  output                I_DJNZ                  ;
83
  output                I_CPL                   ;
84
  output                I_CCF                   ;
85
  output                I_SCF                   ;
86
  output                I_RETN                  ;
87
  output                I_BT                    ;
88
  output                I_BC                    ;
89
  output                I_BTR                   ;
90
  output                I_RLD                   ;
91
  output                I_RRD                   ;
92
  output                I_INRC                  ;
93
  output                SetDI                   ;
94
  output                SetEI                   ;
95
  output [1:0]          IMode                    ;
96
  output                Halt                    ;
97
  output                NoRead                  ;
98
  output                Write   ;
99
 
100
  // regs
101
  reg [2:0]             MCycles                  ;
102
  reg [2:0]             TStates                  ;
103
  reg [1:0]             Prefix                   ; // None,BC,ED,DD/FD
104
  reg                   Inc_PC                  ;
105
  reg                   Inc_WZ                  ;
106
  reg [3:0]             IncDec_16                ; // BC,DE,HL,SP   0 is inc
107
  reg                   Read_To_Reg             ;
108
  reg                   Read_To_Acc             ;
109
  reg [3:0]             Set_BusA_To      ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
110
  reg [3:0]             Set_BusB_To      ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
111
  reg [3:0]             ALU_Op                   ;
112
  reg                   Save_ALU                ;
113
  reg                   PreserveC               ;
114
  reg                   Arith16                 ;
115
  reg [2:0]             Set_Addr_To              ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
116
  reg                   IORQ                    ;
117
  reg                   Jump                    ;
118
  reg                   JumpE                   ;
119
  reg                   JumpXY                  ;
120
  reg                   Call                    ;
121
  reg                   RstP                    ;
122
  reg                   LDZ                     ;
123
  reg                   LDW                     ;
124
  reg                   LDSPHL                  ;
125
  reg [2:0]             Special_LD               ; // A,I;A,R;I,A;R,A;None
126
  reg                   ExchangeDH              ;
127
  reg                   ExchangeRp              ;
128
  reg                   ExchangeAF              ;
129
  reg                   ExchangeRS              ;
130
  reg                   I_DJNZ                  ;
131
  reg                   I_CPL                   ;
132
  reg                   I_CCF                   ;
133
  reg                   I_SCF                   ;
134
  reg                   I_RETN                  ;
135
  reg                   I_BT                    ;
136
  reg                   I_BC                    ;
137
  reg                   I_BTR                   ;
138
  reg                   I_RLD                   ;
139
  reg                   I_RRD                   ;
140
  reg                   I_INRC                  ;
141
  reg                   SetDI                   ;
142
  reg                   SetEI                   ;
143
  reg [1:0]             IMode                    ;
144
  reg                   Halt                    ;
145
  reg                   NoRead                  ;
146
  reg                   Write   ;
147
 
148
        parameter aNone = 3'b111;
149
        parameter aBC   = 3'b000;
150
        parameter aDE   = 3'b001;
151
        parameter aXY   = 3'b010;
152
        parameter aIOA  = 3'b100;
153
        parameter aSP   = 3'b101;
154
        parameter aZI   = 3'b110;
155
//      constant aNone  : std_logic_vector[2:0] = 3'b000;
156
//      constant aXY    : std_logic_vector[2:0] = 3'b001;
157
//      constant aIOA   : std_logic_vector[2:0] = 3'b010;
158
//      constant aSP    : std_logic_vector[2:0] = 3'b011;
159
//      constant aBC    : std_logic_vector[2:0] = 3'b100;
160
//      constant aDE    : std_logic_vector[2:0] = 3'b101;
161
//      constant aZI    : std_logic_vector[2:0] = 3'b110;
162
 
163
  function is_cc_true;
164
    input [7:0] F;
165
    input [2:0] cc;
166
    begin
167
      if (Mode == 3 )
168
        begin
169
          case (cc)
170
            3'b000  : is_cc_true = F[7] == 1'b0; // NZ
171
            3'b001  : is_cc_true = F[7] == 1'b1; // Z
172
            3'b010  : is_cc_true = F[4] == 1'b0; // NC
173
            3'b011  : is_cc_true = F[4] == 1'b1; // C
174
            3'b100  : is_cc_true = 0;
175
            3'b101  : is_cc_true = 0;
176
            3'b110  : is_cc_true = 0;
177
            3'b111  : is_cc_true = 0;
178
          endcase
179
        end
180
      else
181
        begin
182
          case (cc)
183
            3'b000  : is_cc_true = F[6] == 1'b0; // NZ
184
            3'b001  : is_cc_true = F[6] == 1'b1; // Z
185
            3'b010  : is_cc_true = F[0] == 1'b0; // NC
186
            3'b011  : is_cc_true = F[0] == 1'b1; // C
187
            3'b100  : is_cc_true = F[2] == 1'b0; // PO
188
            3'b101  : is_cc_true = F[2] == 1'b1; // PE
189
            3'b110  : is_cc_true = F[7] == 1'b0; // P
190
            3'b111  : is_cc_true = F[7] == 1'b1; // M
191
          endcase
192
        end
193
    end
194
  endfunction // is_cc_true
195
 
196
 
197
  reg [2:0] DDD;
198
  reg [2:0] SSS;
199
  reg [1:0] DPAIR;
200
  reg [7:0] IRB;
201
 
202
  always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle
203
            or NMICycle)
204
    begin
205
      DDD = IR[5:3];
206
      SSS = IR[2:0];
207
      DPAIR = IR[5:4];
208
      IRB = IR;
209
 
210
      MCycles = 3'b001;
211
      if (MCycle == 3'b001 )
212
        begin
213
          TStates = 3'b100;
214
        end
215
      else
216
        begin
217
          TStates = 3'b011;
218
        end
219
      Prefix = 2'b00;
220
      Inc_PC = 1'b0;
221
      Inc_WZ = 1'b0;
222
      IncDec_16 = 4'b0000;
223
      Read_To_Acc = 1'b0;
224
      Read_To_Reg = 1'b0;
225
      Set_BusB_To = 4'b0000;
226
      Set_BusA_To = 4'b0000;
227
      ALU_Op = { 1'b0, IR[5:3] };
228
      Save_ALU = 1'b0;
229
      PreserveC = 1'b0;
230
      Arith16 = 1'b0;
231
      IORQ = 1'b0;
232
      Set_Addr_To = aNone;
233
      Jump = 1'b0;
234
      JumpE = 1'b0;
235
      JumpXY = 1'b0;
236
      Call = 1'b0;
237
      RstP = 1'b0;
238
      LDZ = 1'b0;
239
      LDW = 1'b0;
240
      LDSPHL = 1'b0;
241
      Special_LD = 3'b000;
242
      ExchangeDH = 1'b0;
243
      ExchangeRp = 1'b0;
244
      ExchangeAF = 1'b0;
245
      ExchangeRS = 1'b0;
246
      I_DJNZ = 1'b0;
247
      I_CPL = 1'b0;
248
      I_CCF = 1'b0;
249
      I_SCF = 1'b0;
250
      I_RETN = 1'b0;
251
      I_BT = 1'b0;
252
      I_BC = 1'b0;
253
      I_BTR = 1'b0;
254
      I_RLD = 1'b0;
255
      I_RRD = 1'b0;
256
      I_INRC = 1'b0;
257
      SetDI = 1'b0;
258
      SetEI = 1'b0;
259
      IMode = 2'b11;
260
      Halt = 1'b0;
261
      NoRead = 1'b0;
262
      Write = 1'b0;
263
 
264
      case (ISet)
265
        2'b00  :
266
          begin
267
 
268
//----------------------------------------------------------------------------
269
//
270
//      Unprefixed instructions
271
//
272
//----------------------------------------------------------------------------
273
 
274
            case (IRB)
275
// 8 BIT LOAD GROUP
276
              8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
277
              8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
278
              8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
279
              8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
280
              8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
281
              8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
282
              8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
283
                begin
284
 
285
                  // LD r,r'
286
                  Set_BusB_To[2:0] = SSS;
287
                  ExchangeRp = 1'b1;
288
                  Set_BusA_To[2:0] = DDD;
289
                  Read_To_Reg = 1'b1;
290
                end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
291
 
292
              8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110  :
293
                begin
294
                  // LD r,n
295
                  MCycles = 3'b010;
296
                  case (MCycle)
297
                        2  :
298
                          begin
299
                                Inc_PC = 1'b1;
300
                                Set_BusA_To[2:0] = DDD;
301
                                Read_To_Reg = 1'b1;
302
                          end
303
                    default :;
304
                  endcase // case(MCycle)
305
                end // case: 8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110
306
 
307
              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110  :
308
                  begin
309
                    // LD r,(HL)
310
                    MCycles = 3'b010;
311
                    case (MCycle)
312
                      1  :
313
                                Set_Addr_To = aXY;
314
                      2  :
315
                        begin
316
                          Set_BusA_To[2:0] = DDD;
317
                          Read_To_Reg = 1'b1;
318
                        end
319
                      default :;
320
                    endcase // case(MCycle)
321
                  end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110
322
 
323
              8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111  :
324
                  begin
325
                    // LD (HL),r
326
                    MCycles = 3'b010;
327
                    case (MCycle)
328
                      1  :
329
                        begin
330
                          Set_Addr_To = aXY;
331
                          Set_BusB_To[2:0] = SSS;
332
                          Set_BusB_To[3] = 1'b0;
333
                        end
334
                      2  :
335
                        Write = 1'b1;
336
                      default :;
337
                    endcase // case(MCycle)
338
                  end // case: 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111
339
 
340
              8'b00110110  :
341
                  begin
342
                    // LD (HL),n
343
                    MCycles = 3'b011;
344
                    case (MCycle)
345
                      2  :
346
                        begin
347
                          Inc_PC = 1'b1;
348
                          Set_Addr_To = aXY;
349
                          Set_BusB_To[2:0] = SSS;
350
                          Set_BusB_To[3] = 1'b0;
351
                        end
352
                      3  :
353
                        Write = 1'b1;
354
                      default :;
355
                    endcase // case(MCycle)
356
                  end // case: 8'b00110110
357
 
358
              8'b00001010  :
359
                begin
360
                  // LD A,(BC)
361
                  MCycles = 3'b010;
362
                  case (MCycle)
363
                    1  :
364
                      Set_Addr_To = aBC;
365
                    2  :
366
                      Read_To_Acc = 1'b1;
367
                    default :;
368
                  endcase // case(MCycle)
369
                end // case: 8'b00001010
370
 
371
              8'b00011010  :
372
                begin
373
                  // LD A,(DE)
374
                  MCycles = 3'b010;
375
                  case (MCycle)
376
                    1  :
377
                      Set_Addr_To = aDE;
378
                    2  :
379
                      Read_To_Acc = 1'b1;
380
                    default :;
381
                  endcase // case(MCycle)
382
                end // case: 8'b00011010
383
 
384
              8'b00111010  :
385
                begin
386
                  if (Mode == 3 )
387
                    begin
388
                      // LDD A,(HL)
389
                      MCycles = 3'b010;
390
                      case (MCycle)
391
                        1  :
392
                          Set_Addr_To = aXY;
393
                        2  :
394
                          begin
395
                            Read_To_Acc = 1'b1;
396
                            IncDec_16 = 4'b1110;
397
                          end
398
                        default :;
399
                      endcase
400
                    end
401
                  else
402
                    begin
403
                      // LD A,(nn)
404
                      MCycles = 3'b100;
405
                      case (MCycle)
406
                        2  :
407
                          begin
408
                            Inc_PC = 1'b1;
409
                            LDZ = 1'b1;
410
                          end
411
                        3  :
412
                          begin
413
                            Set_Addr_To = aZI;
414
                            Inc_PC = 1'b1;
415
                          end
416
                        4  :
417
                          begin
418
                            Read_To_Acc = 1'b1;
419
                          end
420
                        default :;
421
                      endcase
422
                    end // else: !if(Mode == 3 )
423
                end // case: 8'b00111010
424
 
425
              8'b00000010  :
426
                begin
427
                  // LD (BC),A
428
                  MCycles = 3'b010;
429
                  case (MCycle)
430
                    1  :
431
                      begin
432
                        Set_Addr_To = aBC;
433
                        Set_BusB_To = 4'b0111;
434
                      end
435
                    2  :
436
                      begin
437
                        Write = 1'b1;
438
                      end
439
                    default :;
440
                  endcase // case(MCycle)
441
                end // case: 8'b00000010
442
 
443
              8'b00010010  :
444
                begin
445
                  // LD (DE),A
446
                  MCycles = 3'b010;
447
                  case (MCycle)
448
                    1  :
449
                      begin
450
                        Set_Addr_To = aDE;
451
                        Set_BusB_To = 4'b0111;
452
                      end
453
                    2  :
454
                      Write = 1'b1;
455
                    default :;
456
                  endcase // case(MCycle)
457
                end // case: 8'b00010010
458
 
459
              8'b00110010  :
460
                begin
461
                  if (Mode == 3 )
462
                    begin
463
                      // LDD (HL),A
464
                      MCycles = 3'b010;
465
                      case (MCycle)
466
                        1  :
467
                          begin
468
                            Set_Addr_To = aXY;
469
                            Set_BusB_To = 4'b0111;
470
                          end
471
                        2  :
472
                          begin
473
                            Write = 1'b1;
474
                            IncDec_16 = 4'b1110;
475
                          end
476
                        default :;
477
                      endcase // case(MCycle)
478
 
479
                    end
480
                  else
481
                    begin
482
                      // LD (nn),A
483
                      MCycles = 3'b100;
484
                      case (MCycle)
485
                        2  :
486
                          begin
487
                            Inc_PC = 1'b1;
488
                            LDZ = 1'b1;
489
                          end
490
                        3  :
491
                          begin
492
                            Set_Addr_To = aZI;
493
                            Inc_PC = 1'b1;
494
                            Set_BusB_To = 4'b0111;
495
                          end
496
                        4  :
497
                          begin
498
                            Write = 1'b1;
499
                          end
500
                        default :;
501
                      endcase
502
                    end // else: !if(Mode == 3 )
503
                end // case: 8'b00110010
504
 
505
 
506
// 16 BIT LOAD GROUP
507
              8'b00000001,8'b00010001,8'b00100001,8'b00110001  :
508
                begin
509
                  // LD dd,nn
510
                  MCycles = 3'b011;
511
                  case (MCycle)
512
                    2  :
513
                      begin
514
                        Inc_PC = 1'b1;
515
                        Read_To_Reg = 1'b1;
516
                        if (DPAIR == 2'b11 )
517
                          begin
518
                            Set_BusA_To[3:0] = 4'b1000;
519
                          end
520
                        else
521
                          begin
522
                            Set_BusA_To[2:1] = DPAIR;
523
                            Set_BusA_To[0] = 1'b1;
524
                          end
525
                      end // case: 2
526
 
527
                    3  :
528
                      begin
529
                        Inc_PC = 1'b1;
530
                        Read_To_Reg = 1'b1;
531
                        if (DPAIR == 2'b11 )
532
                          begin
533
                            Set_BusA_To[3:0] = 4'b1001;
534
                          end
535
                        else
536
                          begin
537
                            Set_BusA_To[2:1] = DPAIR;
538
                            Set_BusA_To[0] = 1'b0;
539
                          end
540
                      end // case: 3
541
 
542
                    default :;
543
                  endcase // case(MCycle)
544
                end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001
545
 
546
              8'b00101010  :
547
                begin
548
                  if (Mode == 3 )
549
                    begin
550
                      // LDI A,(HL)
551
                      MCycles = 3'b010;
552
                      case (MCycle)
553
                        1  :
554
                          Set_Addr_To = aXY;
555
                        2  :
556
                          begin
557
                            Read_To_Acc = 1'b1;
558
                            IncDec_16 = 4'b0110;
559
                          end
560
 
561
                        default :;
562
                      endcase
563
                    end
564
                  else
565
                    begin
566
                      // LD HL,(nn)
567
                      MCycles = 3'b101;
568
                      case (MCycle)
569
                        2  :
570
                          begin
571
                            Inc_PC = 1'b1;
572
                            LDZ = 1'b1;
573
                          end
574
                        3  :
575
                          begin
576
                            Set_Addr_To = aZI;
577
                            Inc_PC = 1'b1;
578
                            LDW = 1'b1;
579
                          end
580
                        4  :
581
                          begin
582
                            Set_BusA_To[2:0] = 3'b101; // L
583
                            Read_To_Reg = 1'b1;
584
                            Inc_WZ = 1'b1;
585
                            Set_Addr_To = aZI;
586
                          end
587
                        5  :
588
                          begin
589
                            Set_BusA_To[2:0] = 3'b100; // H
590
                            Read_To_Reg = 1'b1;
591
                          end
592
                        default :;
593
                      endcase
594
                    end // else: !if(Mode == 3 )
595
                end // case: 8'b00101010
596
 
597
              8'b00100010  :
598
                begin
599
                  if (Mode == 3 )
600
                    begin
601
                      // LDI (HL),A
602
                      MCycles = 3'b010;
603
                      case (MCycle)
604
                        1  :
605
                          begin
606
                            Set_Addr_To = aXY;
607
                            Set_BusB_To = 4'b0111;
608
                          end
609
                        2  :
610
                          begin
611
                            Write = 1'b1;
612
                            IncDec_16 = 4'b0110;
613
                          end
614
                        default :;
615
                      endcase
616
                    end
617
                  else
618
                    begin
619
                      // LD (nn),HL
620
                      MCycles = 3'b101;
621
                      case (MCycle)
622
                        2  :
623
                          begin
624
                            Inc_PC = 1'b1;
625
                            LDZ = 1'b1;
626
                          end
627
 
628
                        3  :
629
                          begin
630
                            Set_Addr_To = aZI;
631
                            Inc_PC = 1'b1;
632
                            LDW = 1'b1;
633
                            Set_BusB_To = 4'b0101; // L
634
                          end
635
 
636
                        4  :
637
                          begin
638
                            Inc_WZ = 1'b1;
639
                            Set_Addr_To = aZI;
640
                            Write = 1'b1;
641
                            Set_BusB_To = 4'b0100; // H
642
                          end
643
                        5  :
644
                          Write = 1'b1;
645
                        default :;
646
                      endcase
647
                    end // else: !if(Mode == 3 )
648
                end // case: 8'b00100010
649
 
650
                8'b11111001  :
651
                  begin
652
                    // LD SP,HL
653
                    TStates = 3'b110;
654
                    LDSPHL = 1'b1;
655
                  end
656
 
657
              8'b11000101,8'b11010101,8'b11100101,8'b11110101  :
658
                begin
659
                  // PUSH qq
660
                  MCycles = 3'b011;
661
                  case (MCycle)
662
                    1  :
663
                      begin
664
                        TStates = 3'b101;
665
                        IncDec_16 = 4'b1111;
666
                        Set_Addr_To = aSP;
667
                        if (DPAIR == 2'b11 )
668
                          begin
669
                            Set_BusB_To = 4'b0111;
670
                          end
671
                        else
672
                          begin
673
                            Set_BusB_To[2:1] = DPAIR;
674
                            Set_BusB_To[0] = 1'b0;
675
                            Set_BusB_To[3] = 1'b0;
676
                          end
677
                      end // case: 1
678
 
679
                    2  :
680
                      begin
681
                        IncDec_16 = 4'b1111;
682
                        Set_Addr_To = aSP;
683
                        if (DPAIR == 2'b11 )
684
                          begin
685
                            Set_BusB_To = 4'b1011;
686
                          end
687
                        else
688
                          begin
689
                            Set_BusB_To[2:1] = DPAIR;
690
                            Set_BusB_To[0] = 1'b1;
691
                            Set_BusB_To[3] = 1'b0;
692
                          end
693
                        Write = 1'b1;
694
                      end // case: 2
695
 
696
                    3  :
697
                      Write = 1'b1;
698
                    default :;
699
                  endcase // case(MCycle)
700
                end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
701
 
702
              8'b11000001,8'b11010001,8'b11100001,8'b11110001  :
703
                begin
704
                  // POP qq
705
                  MCycles = 3'b011;
706
                  case (MCycle)
707
                    1  :
708
                      Set_Addr_To = aSP;
709
                    2  :
710
                      begin
711
                        IncDec_16 = 4'b0111;
712
                        Set_Addr_To = aSP;
713
                        Read_To_Reg = 1'b1;
714
                        if (DPAIR == 2'b11 )
715
                          begin
716
                            Set_BusA_To[3:0] = 4'b1011;
717
                          end
718
                        else
719
                          begin
720
                            Set_BusA_To[2:1] = DPAIR;
721
                            Set_BusA_To[0] = 1'b1;
722
                          end
723
                      end // case: 2
724
 
725
                    3  :
726
                      begin
727
                        IncDec_16 = 4'b0111;
728
                        Read_To_Reg = 1'b1;
729
                        if (DPAIR == 2'b11 )
730
                          begin
731
                            Set_BusA_To[3:0] = 4'b0111;
732
                          end
733
                        else
734
                          begin
735
                            Set_BusA_To[2:1] = DPAIR;
736
                            Set_BusA_To[0] = 1'b0;
737
                          end
738
                      end // case: 3
739
 
740
                    default :;
741
                  endcase // case(MCycle)
742
                end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001
743
 
744
 
745
// EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
746
              8'b11101011  :
747
                begin
748
                  if (Mode != 3 )
749
                    begin
750
                      // EX DE,HL
751
                      ExchangeDH = 1'b1;
752
                    end
753
                end
754
 
755
              8'b00001000  :
756
                begin
757
                  if (Mode == 3 )
758
                    begin
759
                      // LD (nn),SP
760
                      MCycles = 3'b101;
761
                      case (MCycle)
762
                        2  :
763
                          begin
764
                            Inc_PC = 1'b1;
765
                            LDZ = 1'b1;
766
                          end
767
 
768
                        3  :
769
                          begin
770
                            Set_Addr_To = aZI;
771
                            Inc_PC = 1'b1;
772
                            LDW = 1'b1;
773
                            Set_BusB_To = 4'b1000;
774
                          end
775
 
776
                        4  :
777
                          begin
778
                            Inc_WZ = 1'b1;
779
                            Set_Addr_To = aZI;
780
                            Write = 1'b1;
781
                            Set_BusB_To = 4'b1001;
782
                          end
783
 
784
                        5  :
785
                          Write = 1'b1;
786
                        default :;
787
                      endcase
788
                    end
789
                  else if (Mode < 2 )
790
                    begin
791
                      // EX AF,AF'
792
                      ExchangeAF = 1'b1;
793
                    end
794
                end // case: 8'b00001000
795
 
796
              8'b11011001  :
797
                begin
798
                  if (Mode == 3 )
799
                    begin
800
                      // RETI
801
                      MCycles = 3'b011;
802
                      case (MCycle)
803
                        1  :
804
                          Set_Addr_To = aSP;
805
                        2  :
806
                          begin
807
                            IncDec_16 = 4'b0111;
808
                            Set_Addr_To = aSP;
809
                            LDZ = 1'b1;
810
                          end
811
 
812
                        3  :
813
                          begin
814
                            Jump = 1'b1;
815
                            IncDec_16 = 4'b0111;
816
                            I_RETN = 1'b1;
817
                            SetEI = 1'b1;
818
                          end
819
                        default :;
820
                      endcase
821
                    end
822
                  else if (Mode < 2 )
823
                    begin
824
                      // EXX
825
                      ExchangeRS = 1'b1;
826
                    end
827
                end // case: 8'b11011001
828
 
829
              8'b11100011  :
830
                begin
831
                  if (Mode != 3 )
832
                    begin
833
                      // EX (SP),HL
834
                      MCycles = 3'b101;
835
                      case (MCycle)
836
                        1  :
837
                          Set_Addr_To = aSP;
838
                        2  :
839
                          begin
840
                            Read_To_Reg = 1'b1;
841
                            Set_BusA_To = 4'b0101;
842
                            Set_BusB_To = 4'b0101;
843
                            Set_Addr_To = aSP;
844
                          end
845
                        3  :
846
                          begin
847
                            IncDec_16 = 4'b0111;
848
                            Set_Addr_To = aSP;
849
                            TStates = 3'b100;
850
                            Write = 1'b1;
851
                          end
852
                        4  :
853
                          begin
854
                            Read_To_Reg = 1'b1;
855
                            Set_BusA_To = 4'b0100;
856
                            Set_BusB_To = 4'b0100;
857
                            Set_Addr_To = aSP;
858
                          end
859
                        5  :
860
                          begin
861
                            IncDec_16 = 4'b1111;
862
                            TStates = 3'b101;
863
                            Write = 1'b1;
864
                          end
865
 
866
                        default :;
867
                      endcase
868
                    end // if (Mode != 3 )
869
                end // case: 8'b11100011
870
 
871
 
872
// 8 BIT ARITHMETIC AND LOGICAL GROUP
873
              8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
874
              8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
875
              8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
876
              8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
877
              8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
878
              8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
879
              8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
880
              8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
881
                begin
882
                  // ADD A,r
883
                  // ADC A,r
884
                  // SUB A,r
885
                  // SBC A,r
886
                  // AND A,r
887
                  // OR A,r
888
                  // XOR A,r
889
                  // CP A,r
890
                  Set_BusB_To[2:0] = SSS;
891
                  Set_BusA_To[2:0] = 3'b111;
892
                  Read_To_Reg = 1'b1;
893
                  Save_ALU = 1'b1;
894
                end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
895
 
896
              8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110  :
897
                begin
898
                  // ADD A,(HL)
899
                  // ADC A,(HL)
900
                  // SUB A,(HL)
901
                  // SBC A,(HL)
902
                  // AND A,(HL)
903
                  // OR A,(HL)
904
                  // XOR A,(HL)
905
                  // CP A,(HL)
906
                  MCycles = 3'b010;
907
                  case (MCycle)
908
                    1  :
909
                      Set_Addr_To = aXY;
910
                    2  :
911
                      begin
912
                        Read_To_Reg = 1'b1;
913
                        Save_ALU = 1'b1;
914
                        Set_BusB_To[2:0] = SSS;
915
                        Set_BusA_To[2:0] = 3'b111;
916
                      end
917
 
918
                    default :;
919
                  endcase // case(MCycle)
920
                end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
921
 
922
              8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110  :
923
                begin
924
                  // ADD A,n
925
                  // ADC A,n
926
                  // SUB A,n
927
                  // SBC A,n
928
                  // AND A,n
929
                  // OR A,n
930
                  // XOR A,n
931
                  // CP A,n
932
                  MCycles = 3'b010;
933
                  if (MCycle == 3'b010 )
934
                    begin
935
                      Inc_PC = 1'b1;
936
                      Read_To_Reg = 1'b1;
937
                      Save_ALU = 1'b1;
938
                      Set_BusB_To[2:0] = SSS;
939
                      Set_BusA_To[2:0] = 3'b111;
940
                    end
941
                end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
942
 
943
              8'b00000100,8'b00001100,8'b00010100,8'b00011100,8'b00100100,8'b00101100,8'b00111100  :
944
                begin
945
                  // INC r
946
                  Set_BusB_To = 4'b1010;
947
                  Set_BusA_To[2:0] = DDD;
948
                  Read_To_Reg = 1'b1;
949
                  Save_ALU = 1'b1;
950
                  PreserveC = 1'b1;
951
                  ALU_Op = 4'b0000;
952
                end
953
 
954
              8'b00110100  :
955
                begin
956
                  // INC (HL)
957
                  MCycles = 3'b011;
958
                  case (MCycle)
959
                    1  :
960
                      Set_Addr_To = aXY;
961
                    2  :
962
                      begin
963
                        TStates = 3'b100;
964
                        Set_Addr_To = aXY;
965
                        Read_To_Reg = 1'b1;
966
                        Save_ALU = 1'b1;
967
                        PreserveC = 1'b1;
968
                        ALU_Op = 4'b0000;
969
                        Set_BusB_To = 4'b1010;
970
                        Set_BusA_To[2:0] = DDD;
971
                      end // case: 2
972
 
973
                    3  :
974
                      Write = 1'b1;
975
                    default :;
976
                  endcase // case(MCycle)
977
                end // case: 8'b00110100
978
 
979
              8'b00000101,8'b00001101,8'b00010101,8'b00011101,8'b00100101,8'b00101101,8'b00111101  :
980
                begin
981
                  // DEC r
982
                  Set_BusB_To = 4'b1010;
983
                  Set_BusA_To[2:0] = DDD;
984
                  Read_To_Reg = 1'b1;
985
                  Save_ALU = 1'b1;
986
                  PreserveC = 1'b1;
987
                  ALU_Op = 4'b0010;
988
                end
989
 
990
              8'b00110101  :
991
                begin
992
                  // DEC (HL)
993
                  MCycles = 3'b011;
994
                  case (MCycle)
995
                    1  :
996
                      Set_Addr_To = aXY;
997
                    2  :
998
                      begin
999
                        TStates = 3'b100;
1000
                        Set_Addr_To = aXY;
1001
                        ALU_Op = 4'b0010;
1002
                        Read_To_Reg = 1'b1;
1003
                        Save_ALU = 1'b1;
1004
                        PreserveC = 1'b1;
1005
                        Set_BusB_To = 4'b1010;
1006
                        Set_BusA_To[2:0] = DDD;
1007
                      end // case: 2
1008
 
1009
                    3  :
1010
                      Write = 1'b1;
1011
                    default :;
1012
                  endcase // case(MCycle)
1013
                end // case: 8'b00110101              
1014
 
1015
// GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
1016
                8'b00100111  :
1017
                  begin
1018
                    // DAA
1019
                    Set_BusA_To[2:0] = 3'b111;
1020
                    Read_To_Reg = 1'b1;
1021
                    ALU_Op = 4'b1100;
1022
                    Save_ALU = 1'b1;
1023
                  end
1024
 
1025
                8'b00101111  :
1026
                  // CPL
1027
                  I_CPL = 1'b1;
1028
 
1029
                8'b00111111  :
1030
                  // CCF
1031
                  I_CCF = 1'b1;
1032
 
1033
                8'b00110111  :
1034
                  // SCF
1035
                  I_SCF = 1'b1;
1036
 
1037
                8'b00000000  :
1038
                  begin
1039
                    if (NMICycle == 1'b1 )
1040
                      begin
1041
                        // NMI
1042
                        MCycles = 3'b011;
1043
                        case (MCycle)
1044
                          1  :
1045
                            begin
1046
                              TStates = 3'b101;
1047
                              IncDec_16 = 4'b1111;
1048
                              Set_Addr_To = aSP;
1049
                              Set_BusB_To = 4'b1101;
1050
                            end
1051
 
1052
                          2  :
1053
                            begin
1054
                              TStates = 3'b100;
1055
                              Write = 1'b1;
1056
                              IncDec_16 = 4'b1111;
1057
                              Set_Addr_To = aSP;
1058
                              Set_BusB_To = 4'b1100;
1059
                            end
1060
 
1061
                          3  :
1062
                            begin
1063
                              TStates = 3'b100;
1064
                              Write = 1'b1;
1065
                            end
1066
 
1067
                          default :;
1068
                        endcase // case(MCycle)
1069
 
1070
                      end
1071
                    else if (IntCycle == 1'b1 )
1072
                      begin
1073
                        // INT (IM 2)
1074
                        MCycles = 3'b101;
1075
                        case (MCycle)
1076
                          1  :
1077
                            begin
1078
                              LDZ = 1'b1;
1079
                              TStates = 3'b101;
1080
                              IncDec_16 = 4'b1111;
1081
                              Set_Addr_To = aSP;
1082
                              Set_BusB_To = 4'b1101;
1083
                            end
1084
 
1085
                          2  :
1086
                            begin
1087
                              TStates = 3'b100;
1088
                              Write = 1'b1;
1089
                              IncDec_16 = 4'b1111;
1090
                              Set_Addr_To = aSP;
1091
                              Set_BusB_To = 4'b1100;
1092
                            end
1093
 
1094
                          3  :
1095
                            begin
1096
                              TStates = 3'b100;
1097
                              Write = 1'b1;
1098
                            end
1099
 
1100
                          4  :
1101
                            begin
1102
                              Inc_PC = 1'b1;
1103
                              LDZ = 1'b1;
1104
                            end
1105
 
1106
                          5  :
1107
                            Jump = 1'b1;
1108
                          default :;
1109
                        endcase
1110
                      end
1111
                  end // case: 8'b00000000
1112
 
1113
              8'b01110110  :
1114
                // HALT
1115
                Halt = 1'b1;
1116
 
1117
              8'b11110011  :
1118
                // DI
1119
                SetDI = 1'b1;
1120
 
1121
              8'b11111011  :
1122
                // EI
1123
                SetEI = 1'b1;
1124
 
1125
              // 16 BIT ARITHMETIC GROUP
1126
              8'b00001001,8'b00011001,8'b00101001,8'b00111001  :
1127
                begin
1128
                  // ADD HL,ss
1129
                  MCycles = 3'b011;
1130
                  case (MCycle)
1131
                    2  :
1132
                      begin
1133
                        NoRead = 1'b1;
1134
                        ALU_Op = 4'b0000;
1135
                        Read_To_Reg = 1'b1;
1136
                        Save_ALU = 1'b1;
1137
                        Set_BusA_To[2:0] = 3'b101;
1138
                        case (IR[5:4])
1139
                          0,1,2  :
1140
                            begin
1141
                              Set_BusB_To[2:1] = IR[5:4];
1142
                              Set_BusB_To[0] = 1'b1;
1143
                            end
1144
 
1145
                          default :
1146
                            Set_BusB_To = 4'b1000;
1147
                        endcase // case(IR[5:4])
1148
 
1149
                        TStates = 3'b100;
1150
                        Arith16 = 1'b1;
1151
                      end // case: 2
1152
 
1153
                    3  :
1154
                      begin
1155
                        NoRead = 1'b1;
1156
                        Read_To_Reg = 1'b1;
1157
                        Save_ALU = 1'b1;
1158
                        ALU_Op = 4'b0001;
1159
                        Set_BusA_To[2:0] = 3'b100;
1160
                        case (IR[5:4])
1161
                          0,1,2  :
1162
                            Set_BusB_To[2:1] = IR[5:4];
1163
                          default :
1164
                            Set_BusB_To = 4'b1001;
1165
                        endcase
1166
                        Arith16 = 1'b1;
1167
                      end // case: 3
1168
 
1169
                    default :;
1170
                  endcase // case(MCycle)
1171
                end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001              
1172
 
1173
              8'b00000011,8'b00010011,8'b00100011,8'b00110011  :
1174
                begin
1175
                  // INC ss
1176
                  TStates = 3'b110;
1177
                  IncDec_16[3:2] = 2'b01;
1178
                  IncDec_16[1:0] = DPAIR;
1179
                end
1180
 
1181
              8'b00001011,8'b00011011,8'b00101011,8'b00111011  :
1182
                begin
1183
                  // DEC ss
1184
                  TStates = 3'b110;
1185
                  IncDec_16[3:2] = 2'b11;
1186
                  IncDec_16[1:0] = DPAIR;
1187
                end
1188
 
1189
// ROTATE AND SHIFT GROUP
1190
              8'b00000111,
1191
                  // RLCA
1192
                  8'b00010111,
1193
                  // RLA
1194
                  8'b00001111,
1195
                  // RRCA
1196
                  8'b00011111 :
1197
                          // RRA
1198
                begin
1199
                  Set_BusA_To[2:0] = 3'b111;
1200
                  ALU_Op = 4'b1000;
1201
                  Read_To_Reg = 1'b1;
1202
                  Save_ALU = 1'b1;
1203
                end // case: 8'b00000111,...
1204
 
1205
 
1206
// JUMP GROUP
1207
              8'b11000011  :
1208
                begin
1209
                  // JP nn
1210
                  MCycles = 3'b011;
1211
                  case (MCycle)
1212
                    2  :
1213
                      begin
1214
                        Inc_PC = 1'b1;
1215
                        LDZ = 1'b1;
1216
                      end
1217
 
1218
                    3  :
1219
                      begin
1220
                        Inc_PC = 1'b1;
1221
                        Jump = 1'b1;
1222
                      end
1223
 
1224
                    default :;
1225
                  endcase // case(MCycle)
1226
                end // case: 8'b11000011
1227
 
1228
              8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010  :
1229
                begin
1230
                  if (IR[5] == 1'b1 && Mode == 3 )
1231
                    begin
1232
                      case (IRB[4:3])
1233
                        2'b00  :
1234
                          begin
1235
                            // LD ($FF00+C),A
1236
                            MCycles = 3'b010;
1237
                            case (MCycle)
1238
                              1  :
1239
                                begin
1240
                                  Set_Addr_To = aBC;
1241
                                  Set_BusB_To   = 4'b0111;
1242
                                end
1243
                              2  :
1244
                                begin
1245
                                  Write = 1'b1;
1246
                                  IORQ = 1'b1;
1247
                                end
1248
 
1249
                              default :;
1250
                            endcase // case(MCycle)
1251
                          end // case: 2'b00
1252
 
1253
                        2'b01  :
1254
                          begin
1255
                            // LD (nn),A
1256
                            MCycles = 3'b100;
1257
                            case (MCycle)
1258
                              2  :
1259
                                begin
1260
                                  Inc_PC = 1'b1;
1261
                                  LDZ = 1'b1;
1262
                                end
1263
 
1264
                              3  :
1265
                                begin
1266
                                  Set_Addr_To = aZI;
1267
                                  Inc_PC = 1'b1;
1268
                                  Set_BusB_To = 4'b0111;
1269
                                end
1270
 
1271
                              4  :
1272
                                Write = 1'b1;
1273
                              default :;
1274
                            endcase // case(MCycle)
1275
                          end // case: default :...
1276
 
1277
                        2'b10  :
1278
                          begin
1279
                            // LD A,($FF00+C)
1280
                            MCycles = 3'b010;
1281
                            case (MCycle)
1282
                              1  :
1283
                                Set_Addr_To = aBC;
1284
                              2  :
1285
                                begin
1286
                                  Read_To_Acc = 1'b1;
1287
                                  IORQ = 1'b1;
1288
                                end
1289
                              default :;
1290
                            endcase // case(MCycle)
1291
                          end // case: 2'b10
1292
 
1293
                        2'b11  :
1294
                          begin
1295
                            // LD A,(nn)
1296
                            MCycles = 3'b100;
1297
                            case (MCycle)
1298
                              2  :
1299
                                begin
1300
                                  Inc_PC = 1'b1;
1301
                                  LDZ = 1'b1;
1302
                                end
1303
                              3  :
1304
                                begin
1305
                                  Set_Addr_To = aZI;
1306
                                  Inc_PC = 1'b1;
1307
                                end
1308
                              4  :
1309
                                Read_To_Acc = 1'b1;
1310
                              default :;
1311
                            endcase // case(MCycle)
1312
                          end
1313
                      endcase
1314
                    end
1315
                  else
1316
                    begin
1317
                      // JP cc,nn
1318
                      MCycles = 3'b011;
1319
                      case (MCycle)
1320
                        2  :
1321
                          begin
1322
                            Inc_PC = 1'b1;
1323
                            LDZ = 1'b1;
1324
                          end
1325
                        3  :
1326
                          begin
1327
                            Inc_PC = 1'b1;
1328
                            if (is_cc_true(F, IR[5:3]) )
1329
                              begin
1330
                                Jump = 1'b1;
1331
                              end
1332
                          end
1333
 
1334
                        default :;
1335
                      endcase
1336
                    end // else: !if(DPAIR == 2'b11 )
1337
                end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010
1338
 
1339
              8'b00011000  :
1340
                begin
1341
                  if (Mode != 2 )
1342
                    begin
1343
                      // JR e
1344
                      MCycles = 3'b011;
1345
                      case (MCycle)
1346
                        2  :
1347
                          Inc_PC = 1'b1;
1348
                        3  :
1349
                          begin
1350
                            NoRead = 1'b1;
1351
                            JumpE = 1'b1;
1352
                            TStates = 3'b101;
1353
                          end
1354
                        default :;
1355
                      endcase
1356
                    end // if (Mode != 2 )
1357
                end // case: 8'b00011000
1358
 
1359
              8'b00111000  :
1360
                begin
1361
                  if (Mode != 2 )
1362
                    begin
1363
                      // JR C,e
1364
                      MCycles = 3'b011;
1365
                      case (MCycle)
1366
                        2  :
1367
                          begin
1368
                            Inc_PC = 1'b1;
1369
                            if (F[Flag_C] == 1'b0 )
1370
                              begin
1371
                                MCycles = 3'b010;
1372
                              end
1373
                          end
1374
 
1375
                        3  :
1376
                          begin
1377
                            NoRead = 1'b1;
1378
                            JumpE = 1'b1;
1379
                            TStates = 3'b101;
1380
                          end
1381
                        default :;
1382
                      endcase
1383
                    end // if (Mode != 2 )
1384
                end // case: 8'b00111000
1385
 
1386
              8'b00110000  :
1387
                begin
1388
                  if (Mode != 2 )
1389
                    begin
1390
                      // JR NC,e
1391
                      MCycles = 3'b011;
1392
                      case (MCycle)
1393
                        2  :
1394
                          begin
1395
                            Inc_PC = 1'b1;
1396
                            if (F[Flag_C] == 1'b1 )
1397
                              begin
1398
                                MCycles = 3'b010;
1399
                              end
1400
                          end
1401
 
1402
                        3  :
1403
                          begin
1404
                            NoRead = 1'b1;
1405
                            JumpE = 1'b1;
1406
                            TStates = 3'b101;
1407
                          end
1408
                        default :;
1409
                      endcase
1410
                    end // if (Mode != 2 )
1411
                end // case: 8'b00110000
1412
 
1413
              8'b00101000  :
1414
                begin
1415
                  if (Mode != 2 )
1416
                    begin
1417
                      // JR Z,e
1418
                      MCycles = 3'b011;
1419
                      case (MCycle)
1420
                        2  :
1421
                          begin
1422
                            Inc_PC = 1'b1;
1423
                            if (F[Flag_Z] == 1'b0 )
1424
                              begin
1425
                                MCycles = 3'b010;
1426
                              end
1427
                          end
1428
 
1429
                        3  :
1430
                          begin
1431
                            NoRead = 1'b1;
1432
                            JumpE = 1'b1;
1433
                            TStates = 3'b101;
1434
                          end
1435
 
1436
                        default :;
1437
                      endcase
1438
                    end // if (Mode != 2 )
1439
                end // case: 8'b00101000
1440
 
1441
              8'b00100000  :
1442
                begin
1443
                  if (Mode != 2 )
1444
                    begin
1445
                      // JR NZ,e
1446
                      MCycles = 3'b011;
1447
                      case (MCycle)
1448
                        2  :
1449
                          begin
1450
                            Inc_PC = 1'b1;
1451
                            if (F[Flag_Z] == 1'b1 )
1452
                              begin
1453
                                MCycles = 3'b010;
1454
                              end
1455
                          end
1456
                        3  :
1457
                          begin
1458
                            NoRead = 1'b1;
1459
                            JumpE = 1'b1;
1460
                            TStates = 3'b101;
1461
                          end
1462
                        default :;
1463
                      endcase
1464
                    end // if (Mode != 2 )
1465
                end // case: 8'b00100000
1466
 
1467
              8'b11101001  :
1468
                // JP (HL)
1469
                JumpXY = 1'b1;
1470
 
1471
              8'b00010000  :
1472
                begin
1473
                  if (Mode == 3 )
1474
                    begin
1475
                      I_DJNZ = 1'b1;
1476
                    end
1477
                  else if (Mode < 2 )
1478
                    begin
1479
                      // DJNZ,e
1480
                      MCycles = 3'b011;
1481
                      case (MCycle)
1482
                        1  :
1483
                          begin
1484
                            TStates = 3'b101;
1485
                            I_DJNZ = 1'b1;
1486
                            Set_BusB_To = 4'b1010;
1487
                            Set_BusA_To[2:0] = 3'b000;
1488
                            Read_To_Reg = 1'b1;
1489
                            Save_ALU = 1'b1;
1490
                            ALU_Op = 4'b0010;
1491
                          end
1492
                        2  :
1493
                          begin
1494
                            I_DJNZ = 1'b1;
1495
                            Inc_PC = 1'b1;
1496
                          end
1497
                        3  :
1498
                          begin
1499
                            NoRead = 1'b1;
1500
                            JumpE = 1'b1;
1501
                            TStates = 3'b101;
1502
                          end
1503
                        default :;
1504
                      endcase
1505
                    end // if (Mode < 2 )
1506
                end // case: 8'b00010000
1507
 
1508
 
1509
// CALL AND RETURN GROUP
1510
              8'b11001101  :
1511
                begin
1512
                  // CALL nn
1513
                  MCycles = 3'b101;
1514
                  case (MCycle)
1515
                    2  :
1516
                      begin
1517
                        Inc_PC = 1'b1;
1518
                        LDZ = 1'b1;
1519
                      end
1520
                    3  :
1521
                      begin
1522
                        IncDec_16 = 4'b1111;
1523
                        Inc_PC = 1'b1;
1524
                        TStates = 3'b100;
1525
                        Set_Addr_To = aSP;
1526
                        LDW = 1'b1;
1527
                        Set_BusB_To = 4'b1101;
1528
                      end
1529
                    4  :
1530
                      begin
1531
                        Write = 1'b1;
1532
                        IncDec_16 = 4'b1111;
1533
                        Set_Addr_To = aSP;
1534
                        Set_BusB_To = 4'b1100;
1535
                      end
1536
                    5  :
1537
                      begin
1538
                        Write = 1'b1;
1539
                        Call = 1'b1;
1540
                      end
1541
                    default :;
1542
                  endcase // case(MCycle)
1543
                end // case: 8'b11001101
1544
 
1545
              8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100  :
1546
                begin
1547
                  if (IR[5] == 1'b0 || Mode != 3 )
1548
                    begin
1549
                      // CALL cc,nn
1550
                      MCycles = 3'b101;
1551
                      case (MCycle)
1552
                        2  :
1553
                          begin
1554
                            Inc_PC = 1'b1;
1555
                            LDZ = 1'b1;
1556
                          end
1557
                        3  :
1558
                          begin
1559
                            Inc_PC = 1'b1;
1560
                            LDW = 1'b1;
1561
                            if (is_cc_true(F, IR[5:3]) )
1562
                              begin
1563
                                IncDec_16 = 4'b1111;
1564
                                Set_Addr_To = aSP;
1565
                                TStates = 3'b100;
1566
                                Set_BusB_To = 4'b1101;
1567
                              end
1568
                            else
1569
                              begin
1570
                                MCycles = 3'b011;
1571
                              end // else: !if(is_cc_true(F, IR[5:3]) )
1572
                          end // case: 3
1573
 
1574
                        4  :
1575
                          begin
1576
                            Write = 1'b1;
1577
                            IncDec_16 = 4'b1111;
1578
                            Set_Addr_To = aSP;
1579
                            Set_BusB_To = 4'b1100;
1580
                          end
1581
 
1582
                        5  :
1583
                          begin
1584
                            Write = 1'b1;
1585
                            Call = 1'b1;
1586
                          end
1587
 
1588
                        default :;
1589
                      endcase
1590
                    end // if (IR[5] == 1'b0 || Mode != 3 )
1591
                end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100
1592
 
1593
              8'b11001001  :
1594
                begin
1595
                  // RET
1596
                  MCycles = 3'b011;
1597
                  case (MCycle)
1598
                    1  :
1599
                      begin
1600
                        TStates = 3'b101;
1601
                        Set_Addr_To = aSP;
1602
                      end
1603
 
1604
                    2  :
1605
                      begin
1606
                        IncDec_16 = 4'b0111;
1607
                        Set_Addr_To = aSP;
1608
                        LDZ = 1'b1;
1609
                      end
1610
 
1611
                    3  :
1612
                      begin
1613
                        Jump = 1'b1;
1614
                        IncDec_16 = 4'b0111;
1615
                      end
1616
 
1617
                    default :;
1618
                  endcase // case(MCycle)
1619
                end // case: 8'b11001001
1620
 
1621
              8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000  :
1622
                begin
1623
                  if (IR[5] == 1'b1 && Mode == 3 )
1624
                    begin
1625
                      case (IRB[4:3])
1626
                        2'b00  :
1627
                          begin
1628
                            // LD ($FF00+nn),A
1629
                            MCycles = 3'b011;
1630
                            case (MCycle)
1631
                              2  :
1632
                                begin
1633
                                  Inc_PC = 1'b1;
1634
                                  Set_Addr_To = aIOA;
1635
                                  Set_BusB_To   = 4'b0111;
1636
                                end
1637
 
1638
                              3  :
1639
                                Write = 1'b1;
1640
                              default :;
1641
                            endcase // case(MCycle)
1642
                          end // case: 2'b00
1643
 
1644
                        2'b01  :
1645
                          begin
1646
                            // ADD SP,n
1647
                            MCycles = 3'b011;
1648
                            case (MCycle)
1649
                              2  :
1650
                                begin
1651
                                  ALU_Op = 4'b0000;
1652
                                  Inc_PC = 1'b1;
1653
                                  Read_To_Reg = 1'b1;
1654
                                  Save_ALU = 1'b1;
1655
                                  Set_BusA_To = 4'b1000;
1656
                                  Set_BusB_To = 4'b0110;
1657
                                end
1658
 
1659
                              3  :
1660
                                begin
1661
                                  NoRead = 1'b1;
1662
                                  Read_To_Reg = 1'b1;
1663
                                  Save_ALU = 1'b1;
1664
                                  ALU_Op = 4'b0001;
1665
                                  Set_BusA_To = 4'b1001;
1666
                                  Set_BusB_To = 4'b1110;        // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
1667
                                end
1668
 
1669
                              default :;
1670
                            endcase // case(MCycle)
1671
                          end // case: 2'b01
1672
 
1673
                        2'b10  :
1674
                          begin
1675
                            // LD A,($FF00+nn)
1676
                            MCycles = 3'b011;
1677
                            case (MCycle)
1678
                              2  :
1679
                                begin
1680
                                  Inc_PC = 1'b1;
1681
                                  Set_Addr_To = aIOA;
1682
                                end
1683
 
1684
                              3  :
1685
                                Read_To_Acc = 1'b1;
1686
                              default :;
1687
                            endcase // case(MCycle)
1688
                          end // case: 2'b10
1689
 
1690
                        2'b11  :
1691
                          begin
1692
                            // LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
1693
                            MCycles = 3'b101;
1694
                            case (MCycle)
1695
                              2  :
1696
                                begin
1697
                                  Inc_PC = 1'b1;
1698
                                  LDZ = 1'b1;
1699
                                end
1700
 
1701
                              3  :
1702
                                begin
1703
                                  Set_Addr_To = aZI;
1704
                                  Inc_PC = 1'b1;
1705
                                  LDW = 1'b1;
1706
                                end
1707
 
1708
                              4  :
1709
                                begin
1710
                                  Set_BusA_To[2:0] = 3'b101; // L
1711
                                  Read_To_Reg = 1'b1;
1712
                                  Inc_WZ = 1'b1;
1713
                                  Set_Addr_To = aZI;
1714
                                end
1715
 
1716
                              5  :
1717
                                begin
1718
                                  Set_BusA_To[2:0] = 3'b100; // H
1719
                                  Read_To_Reg = 1'b1;
1720
                                end
1721
 
1722
                              default :;
1723
                            endcase // case(MCycle)
1724
                          end // case: 2'b11
1725
 
1726
                      endcase // case(IRB[4:3])
1727
 
1728
                    end
1729
                  else
1730
                    begin
1731
                      // RET cc
1732
                      MCycles = 3'b011;
1733
                      case (MCycle)
1734
                        1  :
1735
                          begin
1736
                            if (is_cc_true(F, IR[5:3]) )
1737
                              begin
1738
                                Set_Addr_To = aSP;
1739
                              end
1740
                            else
1741
                              begin
1742
                                MCycles = 3'b001;
1743
                              end
1744
                            TStates = 3'b101;
1745
                          end // case: 1
1746
 
1747
                        2  :
1748
                          begin
1749
                            IncDec_16 = 4'b0111;
1750
                            Set_Addr_To = aSP;
1751
                            LDZ = 1'b1;
1752
                          end
1753
                        3  :
1754
                          begin
1755
                            Jump = 1'b1;
1756
                            IncDec_16 = 4'b0111;
1757
                          end
1758
                        default :;
1759
                      endcase
1760
                    end // else: !if(IR[5] == 1'b1 && Mode == 3 )
1761
                end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000
1762
 
1763
              8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111  :
1764
                begin
1765
                  // RST p
1766
                  MCycles = 3'b011;
1767
                  case (MCycle)
1768
                    1  :
1769
                      begin
1770
                        TStates = 3'b101;
1771
                        IncDec_16 = 4'b1111;
1772
                        Set_Addr_To = aSP;
1773
                        Set_BusB_To = 4'b1101;
1774
                      end
1775
 
1776
                    2  :
1777
                      begin
1778
                        Write = 1'b1;
1779
                        IncDec_16 = 4'b1111;
1780
                        Set_Addr_To = aSP;
1781
                        Set_BusB_To = 4'b1100;
1782
                      end
1783
 
1784
                    3  :
1785
                      begin
1786
                        Write = 1'b1;
1787
                        RstP = 1'b1;
1788
                      end
1789
 
1790
                    default :;
1791
                  endcase // case(MCycle)
1792
                end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111
1793
 
1794
// INPUT AND OUTPUT GROUP
1795
              8'b11011011  :
1796
                begin
1797
                  if (Mode != 3 )
1798
                    begin
1799
                      // IN A,(n)
1800
                      MCycles = 3'b011;
1801
                      case (MCycle)
1802
                        2  :
1803
                          begin
1804
                            Inc_PC = 1'b1;
1805
                            Set_Addr_To = aIOA;
1806
                          end
1807
 
1808
                        3  :
1809
                          begin
1810
                            Read_To_Acc = 1'b1;
1811
                            IORQ = 1'b1;
1812
                          end
1813
 
1814
                        default :;
1815
                      endcase
1816
                    end // if (Mode != 3 )
1817
                end // case: 8'b11011011
1818
 
1819
              8'b11010011  :
1820
                begin
1821
                  if (Mode != 3 )
1822
                    begin
1823
                      // OUT (n),A
1824
                      MCycles = 3'b011;
1825
                      case (MCycle)
1826
                        2  :
1827
                          begin
1828
                            Inc_PC = 1'b1;
1829
                            Set_Addr_To = aIOA;
1830
                            Set_BusB_To = 4'b0111;
1831
                          end
1832
 
1833
                        3  :
1834
                          begin
1835
                            Write = 1'b1;
1836
                            IORQ = 1'b1;
1837
                          end
1838
 
1839
                        default :;
1840
                      endcase
1841
                    end // if (Mode != 3 )
1842
                end // case: 8'b11010011
1843
 
1844
 
1845
//----------------------------------------------------------------------------
1846
//----------------------------------------------------------------------------
1847
// MULTIBYTE INSTRUCTIONS
1848
//----------------------------------------------------------------------------
1849
//----------------------------------------------------------------------------
1850
 
1851
              8'b11001011  :
1852
                begin
1853
                  if (Mode != 2 )
1854
                    begin
1855
                      Prefix = 2'b01;
1856
                    end
1857
                end
1858
 
1859
              8'b11101101  :
1860
                begin
1861
                  if (Mode < 2 )
1862
                    begin
1863
                      Prefix = 2'b10;
1864
                    end
1865
                end
1866
 
1867
              8'b11011101,8'b11111101  :
1868
                begin
1869
                  if (Mode < 2 )
1870
                    begin
1871
                      Prefix = 2'b11;
1872
                    end
1873
                end
1874
 
1875
            endcase // case(IRB)
1876
          end // case: 2'b00
1877
 
1878
 
1879
        2'b01  :
1880
          begin
1881
 
1882
 
1883
            //----------------------------------------------------------------------------
1884
            //
1885
            //  CB prefixed instructions
1886
            //
1887
            //----------------------------------------------------------------------------
1888
 
1889
            Set_BusA_To[2:0] = IR[2:0];
1890
            Set_BusB_To[2:0] = IR[2:0];
1891
 
1892
            case (IRB)
1893
              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
1894
              8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
1895
              8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
1896
              8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
1897
              8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
1898
              8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111,
1899
              8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111,
1900
              8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 :
1901
                begin
1902
                  // RLC r
1903
                  // RL r
1904
                  // RRC r
1905
                  // RR r
1906
                  // SLA r
1907
                  // SRA r
1908
                  // SRL r
1909
                  // SLL r (Undocumented) / SWAP r
1910
                  if (MCycle == 3'b001 ) begin
1911
                    ALU_Op = 4'b1000;
1912
                    Read_To_Reg = 1'b1;
1913
                    Save_ALU = 1'b1;
1914
                  end
1915
                end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
1916
 
1917
              8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110  :
1918
                begin
1919
                  // RLC (HL)
1920
                  // RL (HL)
1921
                  // RRC (HL)
1922
                  // RR (HL)
1923
                  // SRA (HL)
1924
                  // SRL (HL)
1925
                  // SLA (HL)
1926
                  // SLL (HL) (Undocumented) / SWAP (HL)
1927
                  MCycles = 3'b011;
1928
                  case (MCycle)
1929
                    1 , 7  :
1930
                      Set_Addr_To = aXY;
1931
                    2  :
1932
                      begin
1933
                        ALU_Op = 4'b1000;
1934
                        Read_To_Reg = 1'b1;
1935
                        Save_ALU = 1'b1;
1936
                        Set_Addr_To = aXY;
1937
                        TStates = 3'b100;
1938
                      end
1939
 
1940
                    3  :
1941
                      Write = 1'b1;
1942
                    default :;
1943
                  endcase // case(MCycle)
1944
                end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
1945
 
1946
              8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
1947
                  8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
1948
                  8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
1949
                  8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
1950
                  8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
1951
                  8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
1952
                  8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
1953
                  8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
1954
                    begin
1955
                      // BIT b,r
1956
                      if (MCycle == 3'b001 )
1957
                        begin
1958
                          Set_BusB_To[2:0] = IR[2:0];
1959
                          ALU_Op = 4'b1001;
1960
                        end
1961
                    end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
1962
 
1963
              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110  :
1964
                begin
1965
                  // BIT b,(HL)
1966
                  MCycles = 3'b010;
1967
                  case (MCycle)
1968
                    1 , 7  :
1969
                      Set_Addr_To = aXY;
1970
                    2  :
1971
                      begin
1972
                        ALU_Op = 4'b1001;
1973
                        TStates = 3'b100;
1974
                      end
1975
 
1976
                    default :;
1977
                  endcase // case(MCycle)
1978
                end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110
1979
 
1980
              8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,
1981
                  8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111,
1982
                  8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111,
1983
                  8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111,
1984
                  8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111,
1985
                  8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
1986
                  8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
1987
                  8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
1988
                    begin
1989
                      // SET b,r
1990
                      if (MCycle == 3'b001 )
1991
                        begin
1992
                          ALU_Op = 4'b1010;
1993
                          Read_To_Reg = 1'b1;
1994
                          Save_ALU = 1'b1;
1995
                        end
1996
                    end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,...
1997
 
1998
              8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110  :
1999
                begin
2000
                  // SET b,(HL)
2001
                  MCycles = 3'b011;
2002
                  case (MCycle)
2003
                    1 , 7  :
2004
                      Set_Addr_To = aXY;
2005
                    2  :
2006
                      begin
2007
                        ALU_Op = 4'b1010;
2008
                        Read_To_Reg = 1'b1;
2009
                        Save_ALU = 1'b1;
2010
                        Set_Addr_To = aXY;
2011
                        TStates = 3'b100;
2012
                      end
2013
                    3  :
2014
                      Write = 1'b1;
2015
                    default :;
2016
                  endcase // case(MCycle)
2017
                end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
2018
 
2019
              8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
2020
                  8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
2021
                  8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
2022
                  8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
2023
                  8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
2024
                  8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
2025
                  8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
2026
                  8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
2027
                    begin
2028
                      // RES b,r
2029
                      if (MCycle == 3'b001 )
2030
                        begin
2031
                          ALU_Op = 4'b1011;
2032
                          Read_To_Reg = 1'b1;
2033
                          Save_ALU = 1'b1;
2034
                        end
2035
                    end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
2036
 
2037
              8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110  :
2038
                begin
2039
                  // RES b,(HL)
2040
                  MCycles = 3'b011;
2041
                  case (MCycle)
2042
                    1 , 7  :
2043
                      Set_Addr_To = aXY;
2044
                    2  :
2045
                      begin
2046
                        ALU_Op = 4'b1011;
2047
                        Read_To_Reg = 1'b1;
2048
                        Save_ALU = 1'b1;
2049
                        Set_Addr_To = aXY;
2050
                        TStates = 3'b100;
2051
                      end
2052
 
2053
                    3  :
2054
                      Write = 1'b1;
2055
                    default :;
2056
                  endcase // case(MCycle)
2057
                end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
2058
 
2059
            endcase // case(IRB)
2060
          end // case: 2'b01
2061
 
2062
 
2063
        default :
2064
          begin : default_ed_block
2065
 
2066
            //----------------------------------------------------------------------------
2067
            //
2068
            //  ED prefixed instructions
2069
            //
2070
            //----------------------------------------------------------------------------
2071
 
2072
            case (IRB)
2073
              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
2074
                ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
2075
                  ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111
2076
                    ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111
2077
                      ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111
2078
                        ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111
2079
                          ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111
2080
                            ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111
2081
 
2082
 
2083
                                  ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111
2084
                                    ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111
2085
                                      ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111
2086
                                        ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111
2087
                                          ,                                            8'b10100100,8'b10100101,8'b10100110,8'b10100111
2088
                                            ,                                            8'b10101100,8'b10101101,8'b10101110,8'b10101111
2089
                                              ,                                            8'b10110100,8'b10110101,8'b10110110,8'b10110111
2090
                                                ,                                            8'b10111100,8'b10111101,8'b10111110,8'b10111111
2091
                                                  ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111
2092
                                                    ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111
2093
                                                      ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111
2094
                                                        ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111
2095
                                                          ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111
2096
                                                            ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111
2097
                                                              ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111
2098
                                                                ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 :
2099
                                ; // NOP, undocumented
2100
 
2101
                  8'b01111110,8'b01111111  :
2102
                    // NOP, undocumented
2103
                ;
2104
                  // 8 BIT LOAD GROUP
2105
                  8'b01010111  :
2106
                    begin
2107
                      // LD A,I
2108
                      Special_LD = 3'b100;
2109
                      TStates = 3'b101;
2110
                    end
2111
 
2112
                  8'b01011111  :
2113
                    begin
2114
                      // LD A,R
2115
                      Special_LD = 3'b101;
2116
                      TStates = 3'b101;
2117
                    end
2118
 
2119
                  8'b01000111  :
2120
                    begin
2121
                      // LD I,A
2122
                      Special_LD = 3'b110;
2123
                      TStates = 3'b101;
2124
                    end
2125
 
2126
                  8'b01001111  :
2127
                    begin
2128
                      // LD R,A
2129
                      Special_LD = 3'b111;
2130
                      TStates = 3'b101;
2131
                    end
2132
 
2133
                  // 16 BIT LOAD GROUP
2134
                  8'b01001011,8'b01011011,8'b01101011,8'b01111011  :
2135
                    begin
2136
                      // LD dd,(nn)
2137
                      MCycles = 3'b101;
2138
                      case (MCycle)
2139
                        2  :
2140
                          begin
2141
                            Inc_PC = 1'b1;
2142
                            LDZ = 1'b1;
2143
                          end
2144
 
2145
                        3  :
2146
                          begin
2147
                            Set_Addr_To = aZI;
2148
                            Inc_PC = 1'b1;
2149
                            LDW = 1'b1;
2150
                          end
2151
 
2152
                        4  :
2153
                          begin
2154
                            Read_To_Reg = 1'b1;
2155
                            if (IR[5:4] == 2'b11 )
2156
                              begin
2157
                                Set_BusA_To = 4'b1000;
2158
                              end
2159
                            else
2160
                              begin
2161
                                Set_BusA_To[2:1] = IR[5:4];
2162
                                Set_BusA_To[0] = 1'b1;
2163
                              end
2164
                            Inc_WZ = 1'b1;
2165
                            Set_Addr_To = aZI;
2166
                          end // case: 4
2167
 
2168
                        5  :
2169
                          begin
2170
                            Read_To_Reg = 1'b1;
2171
                            if (IR[5:4] == 2'b11 )
2172
                              begin
2173
                                Set_BusA_To = 4'b1001;
2174
                              end
2175
                            else
2176
                              begin
2177
                                Set_BusA_To[2:1] = IR[5:4];
2178
                                Set_BusA_To[0] = 1'b0;
2179
                              end
2180
                          end // case: 5
2181
 
2182
                        default :;
2183
                      endcase // case(MCycle)
2184
                    end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011
2185
 
2186
 
2187
                  8'b01000011,8'b01010011,8'b01100011,8'b01110011  :
2188
                    begin
2189
                      // LD (nn),dd
2190
                      MCycles = 3'b101;
2191
                      case (MCycle)
2192
                        2  :
2193
                          begin
2194
                            Inc_PC = 1'b1;
2195
                            LDZ = 1'b1;
2196
                          end
2197
 
2198
                        3  :
2199
                          begin
2200
                            Set_Addr_To = aZI;
2201
                            Inc_PC = 1'b1;
2202
                            LDW = 1'b1;
2203
                            if (IR[5:4] == 2'b11 )
2204
                              begin
2205
                                Set_BusB_To = 4'b1000;
2206
                              end
2207
                            else
2208
                              begin
2209
                                Set_BusB_To[2:1] = IR[5:4];
2210
                                Set_BusB_To[0] = 1'b1;
2211
                                Set_BusB_To[3] = 1'b0;
2212
                              end
2213
                          end // case: 3
2214
 
2215
                        4  :
2216
                          begin
2217
                            Inc_WZ = 1'b1;
2218
                            Set_Addr_To = aZI;
2219
                            Write = 1'b1;
2220
                            if (IR[5:4] == 2'b11 )
2221
                              begin
2222
                                Set_BusB_To = 4'b1001;
2223
                              end
2224
                            else
2225
                              begin
2226
                                Set_BusB_To[2:1] = IR[5:4];
2227
                                Set_BusB_To[0] = 1'b0;
2228
                                Set_BusB_To[3] = 1'b0;
2229
                              end
2230
                          end // case: 4
2231
 
2232
                        5  :
2233
                          begin
2234
                            Write = 1'b1;
2235
                          end
2236
 
2237
                        default :;
2238
                      endcase // case(MCycle)
2239
                    end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011
2240
 
2241
                  8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000  :
2242
                    begin
2243
                      // LDI, LDD, LDIR, LDDR
2244
                      MCycles = 3'b100;
2245
                      case (MCycle)
2246
                        1  :
2247
                          begin
2248
                            Set_Addr_To = aXY;
2249
                            IncDec_16 = 4'b1100; // BC
2250
                          end
2251
 
2252
                        2  :
2253
                          begin
2254
                            Set_BusB_To = 4'b0110;
2255
                            Set_BusA_To[2:0] = 3'b111;
2256
                            ALU_Op = 4'b0000;
2257
                            Set_Addr_To = aDE;
2258
                            if (IR[3] == 1'b0 )
2259
                              begin
2260
                                IncDec_16 = 4'b0110; // IX
2261
                              end
2262
                            else
2263
                              begin
2264
                                IncDec_16 = 4'b1110;
2265
                              end
2266
                          end // case: 2
2267
 
2268
                        3  :
2269
                          begin
2270
                            I_BT = 1'b1;
2271
                            TStates = 3'b101;
2272
                            Write = 1'b1;
2273
                            if (IR[3] == 1'b0 )
2274
                              begin
2275
                                IncDec_16 = 4'b0101; // DE
2276
                              end
2277
                            else
2278
                              begin
2279
                                IncDec_16 = 4'b1101;
2280
                              end
2281
                          end // case: 3
2282
 
2283
                        4  :
2284
                          begin
2285
                            NoRead = 1'b1;
2286
                            TStates = 3'b101;
2287
                          end
2288
 
2289
                        default :;
2290
                      endcase // case(MCycle)
2291
                    end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000
2292
 
2293
                  8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001  :
2294
                    begin
2295
                      // CPI, CPD, CPIR, CPDR
2296
                      MCycles = 3'b100;
2297
                      case (MCycle)
2298
                        1  :
2299
                          begin
2300
                            Set_Addr_To = aXY;
2301
                            IncDec_16 = 4'b1100; // BC
2302
                          end
2303
 
2304
                        2  :
2305
                          begin
2306
                            Set_BusB_To = 4'b0110;
2307
                            Set_BusA_To[2:0] = 3'b111;
2308
                            ALU_Op = 4'b0111;
2309
                            Save_ALU = 1'b1;
2310
                            PreserveC = 1'b1;
2311
                            if (IR[3] == 1'b0 )
2312
                              begin
2313
                                IncDec_16 = 4'b0110;
2314
                              end
2315
                            else
2316
                              begin
2317
                                IncDec_16 = 4'b1110;
2318
                              end
2319
                          end // case: 2
2320
 
2321
                        3  :
2322
                          begin
2323
                            NoRead = 1'b1;
2324
                            I_BC = 1'b1;
2325
                            TStates = 3'b101;
2326
                          end
2327
 
2328
                        4  :
2329
                          begin
2330
                            NoRead = 1'b1;
2331
                            TStates = 3'b101;
2332
                          end
2333
 
2334
                        default :;
2335
                      endcase // case(MCycle)
2336
                    end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001
2337
 
2338
                  8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100  :
2339
                    begin
2340
                      // NEG
2341
                      ALU_Op = 4'b0010;
2342
                      Set_BusB_To = 4'b0111;
2343
                      Set_BusA_To = 4'b1010;
2344
                      Read_To_Acc = 1'b1;
2345
                      Save_ALU = 1'b1;
2346
                    end
2347
 
2348
                  8'b01000110,8'b01001110,8'b01100110,8'b01101110  :
2349
                    begin
2350
                      // IM 0
2351
                      IMode = 2'b00;
2352
                    end
2353
 
2354
                  8'b01010110,8'b01110110  :
2355
                    // IM 1
2356
                    IMode = 2'b01;
2357
 
2358
                  8'b01011110,8'b01110111  :
2359
                    // IM 2
2360
                    IMode = 2'b10;
2361
 
2362
                  // 16 bit arithmetic
2363
                  8'b01001010,8'b01011010,8'b01101010,8'b01111010  :
2364
                    begin
2365
                      // ADC HL,ss
2366
                      MCycles = 3'b011;
2367
                      case (MCycle)
2368
                        2  :
2369
                          begin
2370
                            NoRead = 1'b1;
2371
                            ALU_Op = 4'b0001;
2372
                            Read_To_Reg = 1'b1;
2373
                            Save_ALU = 1'b1;
2374
                            Set_BusA_To[2:0] = 3'b101;
2375
                            case (IR[5:4])
2376
                              0,1,2  :
2377
                                begin
2378
                                  Set_BusB_To[2:1] = IR[5:4];
2379
                                  Set_BusB_To[0] = 1'b1;
2380
                                end
2381
                              default :
2382
                                Set_BusB_To = 4'b1000;
2383
                            endcase
2384
                            TStates = 3'b100;
2385
                          end // case: 2
2386
 
2387
                        3  :
2388
                          begin
2389
                            NoRead = 1'b1;
2390
                            Read_To_Reg = 1'b1;
2391
                            Save_ALU = 1'b1;
2392
                            ALU_Op = 4'b0001;
2393
                            Set_BusA_To[2:0] = 3'b100;
2394
                            case (IR[5:4])
2395
                              0,1,2  :
2396
                                begin
2397
                                  Set_BusB_To[2:1] = IR[5:4];
2398
                                  Set_BusB_To[0] = 1'b0;
2399
                                end
2400
                              default :
2401
                                Set_BusB_To = 4'b1001;
2402
                            endcase // case(IR[5:4])
2403
                          end // case: 3
2404
 
2405
                        default :;
2406
                      endcase // case(MCycle)
2407
                    end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010
2408
 
2409
                  8'b01000010,8'b01010010,8'b01100010,8'b01110010  :
2410
                    begin
2411
                      // SBC HL,ss
2412
                      MCycles = 3'b011;
2413
                      case (MCycle)
2414
                        2  :
2415
                          begin
2416
                            NoRead = 1'b1;
2417
                            ALU_Op = 4'b0011;
2418
                            Read_To_Reg = 1'b1;
2419
                            Save_ALU = 1'b1;
2420
                            Set_BusA_To[2:0] = 3'b101;
2421
                            case (IR[5:4])
2422
                              0,1,2  :
2423
                                begin
2424
                                  Set_BusB_To[2:1] = IR[5:4];
2425
                                  Set_BusB_To[0] = 1'b1;
2426
                                end
2427
                              default :
2428
                                Set_BusB_To = 4'b1000;
2429
                            endcase
2430
                            TStates = 3'b100;
2431
                          end // case: 2
2432
 
2433
                        3  :
2434
                          begin
2435
                            NoRead = 1'b1;
2436
                            ALU_Op = 4'b0011;
2437
                            Read_To_Reg = 1'b1;
2438
                            Save_ALU = 1'b1;
2439
                            Set_BusA_To[2:0] = 3'b100;
2440
                            case (IR[5:4])
2441
                              0,1,2  :
2442
                                Set_BusB_To[2:1] = IR[5:4];
2443
                              default :
2444
                                Set_BusB_To = 4'b1001;
2445
                            endcase
2446
                          end // case: 3
2447
 
2448
                        default :;
2449
 
2450
                      endcase // case(MCycle)
2451
                    end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010
2452
 
2453
                  8'b01101111  :
2454
                    begin
2455
                      // RLD
2456
                      MCycles = 3'b100;
2457
                      case (MCycle)
2458
                        2  :
2459
                          begin
2460
                            NoRead = 1'b1;
2461
                            Set_Addr_To = aXY;
2462
                          end
2463
 
2464
                        3  :
2465
                          begin
2466
                            Read_To_Reg = 1'b1;
2467
                            Set_BusB_To[2:0] = 3'b110;
2468
                            Set_BusA_To[2:0] = 3'b111;
2469
                            ALU_Op = 4'b1101;
2470
                            TStates = 3'b100;
2471
                            Set_Addr_To = aXY;
2472
                            Save_ALU = 1'b1;
2473
                          end
2474
 
2475
                        4  :
2476
                          begin
2477
                            I_RLD = 1'b1;
2478
                            Write = 1'b1;
2479
                          end
2480
 
2481
                        default :;
2482
                      endcase // case(MCycle)
2483
                    end // case: 8'b01101111
2484
 
2485
                  8'b01100111  :
2486
                    begin
2487
                      // RRD
2488
                      MCycles = 3'b100;
2489
                      case (MCycle)
2490
                        2  :
2491
                          Set_Addr_To = aXY;
2492
                        3  :
2493
                          begin
2494
                            Read_To_Reg = 1'b1;
2495
                            Set_BusB_To[2:0] = 3'b110;
2496
                            Set_BusA_To[2:0] = 3'b111;
2497
                            ALU_Op = 4'b1110;
2498
                            TStates = 3'b100;
2499
                            Set_Addr_To = aXY;
2500
                            Save_ALU = 1'b1;
2501
                          end
2502
 
2503
                        4  :
2504
                          begin
2505
                            I_RRD = 1'b1;
2506
                            Write = 1'b1;
2507
                          end
2508
 
2509
                        default :;
2510
                      endcase // case(MCycle)
2511
                    end // case: 8'b01100111
2512
 
2513
                  8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101  :
2514
                    begin
2515
                      // RETI, RETN
2516
                      MCycles = 3'b011;
2517
                      case (MCycle)
2518
                        1  :
2519
                          Set_Addr_To = aSP;
2520
 
2521
                        2  :
2522
                          begin
2523
                            IncDec_16 = 4'b0111;
2524
                            Set_Addr_To = aSP;
2525
                            LDZ = 1'b1;
2526
                          end
2527
 
2528
                        3  :
2529
                          begin
2530
                            Jump = 1'b1;
2531
                            IncDec_16 = 4'b0111;
2532
                            I_RETN = 1'b1;
2533
                          end
2534
 
2535
                        default :;
2536
                      endcase // case(MCycle)
2537
                    end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101
2538
 
2539
                  8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000  :
2540
                    begin
2541
                      // IN r,(C)
2542
                      MCycles = 3'b010;
2543
                      case (MCycle)
2544
                        1  :
2545
                          Set_Addr_To = aBC;
2546
 
2547
                        2  :
2548
                          begin
2549
                            IORQ = 1'b1;
2550
                            if (IR[5:3] != 3'b110 )
2551
                              begin
2552
                                Read_To_Reg = 1'b1;
2553
                                Set_BusA_To[2:0] = IR[5:3];
2554
                              end
2555
                            I_INRC = 1'b1;
2556
                          end
2557
 
2558
                        default :;
2559
                      endcase // case(MCycle)
2560
                    end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000
2561
 
2562
                  8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001  :
2563
                    begin
2564
                      // OUT (C),r
2565
                      // OUT (C),0
2566
                      MCycles = 3'b010;
2567
                      case (MCycle)
2568
                        1  :
2569
                          begin
2570
                            Set_Addr_To = aBC;
2571
                            Set_BusB_To[2:0]     = IR[5:3];
2572
                            if (IR[5:3] == 3'b110 )
2573
                              begin
2574
                                Set_BusB_To[3] = 1'b1;
2575
                              end
2576
                          end
2577
 
2578
                        2  :
2579
                          begin
2580
                            Write = 1'b1;
2581
                            IORQ = 1'b1;
2582
                          end
2583
 
2584
                        default :;
2585
                      endcase // case(MCycle)
2586
                    end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001
2587
 
2588
                  8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010  :
2589
                    begin
2590
                      // INI, IND, INIR, INDR
2591
                      MCycles = 3'b100;
2592
                      case (MCycle)
2593
                        1  :
2594
                          begin
2595
                            Set_Addr_To = aBC;
2596
                            Set_BusB_To = 4'b1010;
2597
                            Set_BusA_To = 4'b0000;
2598
                            Read_To_Reg = 1'b1;
2599
                            Save_ALU = 1'b1;
2600
                            ALU_Op = 4'b0010;
2601
                          end
2602
 
2603
                        2  :
2604
                          begin
2605
                            IORQ = 1'b1;
2606
                            Set_BusB_To = 4'b0110;
2607
                            Set_Addr_To = aXY;
2608
                          end
2609
 
2610
                        3  :
2611
                          begin
2612
                            if (IR[3] == 1'b0 )
2613
                              begin
2614
                                IncDec_16 = 4'b0010;
2615
                              end
2616
                            else
2617
                              begin
2618
                                IncDec_16 = 4'b1010;
2619
                              end
2620
                            TStates = 3'b100;
2621
                            Write = 1'b1;
2622
                            I_BTR = 1'b1;
2623
                          end // case: 3
2624
 
2625
                        4  :
2626
                          begin
2627
                            NoRead = 1'b1;
2628
                            TStates = 3'b101;
2629
                          end
2630
 
2631
                        default :;
2632
                      endcase // case(MCycle)
2633
                    end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010
2634
 
2635
                  8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011  :
2636
                    begin
2637
                      // OUTI, OUTD, OTIR, OTDR
2638
                      MCycles = 3'b100;
2639
                      case (MCycle)
2640
                        1  :
2641
                          begin
2642
                            TStates = 3'b101;
2643
                            Set_Addr_To = aXY;
2644
                            Set_BusB_To = 4'b1010;
2645
                            Set_BusA_To = 4'b0000;
2646
                            Read_To_Reg = 1'b1;
2647
                            Save_ALU = 1'b1;
2648
                            ALU_Op = 4'b0010;
2649
                          end
2650
 
2651
                        2  :
2652
                          begin
2653
                            Set_BusB_To = 4'b0110;
2654
                            Set_Addr_To = aBC;
2655
                          end
2656
 
2657
                        3  :
2658
                          begin
2659
                            if (IR[3] == 1'b0 )
2660
                              begin
2661
                                IncDec_16 = 4'b0010;
2662
                              end
2663
                            else
2664
                              begin
2665
                                IncDec_16 = 4'b1010;
2666
                              end
2667
                            IORQ = 1'b1;
2668
                            Write = 1'b1;
2669
                            I_BTR = 1'b1;
2670
                          end // case: 3
2671
 
2672
                        4  :
2673
                          begin
2674
                            NoRead = 1'b1;
2675
                            TStates = 3'b101;
2676
                          end
2677
 
2678
                        default :;
2679
                      endcase // case(MCycle)
2680
                    end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
2681
 
2682
                endcase // case(IRB)                  
2683
          end // block: default_ed_block        
2684
      endcase // case(ISet)
2685
 
2686
      if (Mode == 1 )
2687
        begin
2688
          if (MCycle == 3'b001 )
2689
            begin
2690
              //TStates = 3'b100;
2691
            end
2692
          else
2693
            begin
2694
              TStates = 3'b011;
2695
            end
2696
        end
2697
 
2698
      if (Mode == 3 )
2699
        begin
2700
          if (MCycle == 3'b001 )
2701
            begin
2702
              //TStates = 3'b100;
2703
            end
2704
          else
2705
            begin
2706
              TStates = 3'b100;
2707
            end
2708
        end
2709
 
2710
      if (Mode < 2 )
2711
        begin
2712
          if (MCycle == 3'b110 )
2713
            begin
2714
              Inc_PC = 1'b1;
2715
              if (Mode == 1 )
2716
                begin
2717
                  Set_Addr_To = aXY;
2718
                  TStates = 3'b100;
2719
                  Set_BusB_To[2:0] = SSS;
2720
                  Set_BusB_To[3] = 1'b0;
2721
                end
2722
              if (IRB == 8'b00110110 || IRB == 8'b11001011 )
2723
                begin
2724
                  Set_Addr_To = aNone;
2725
                end
2726
            end
2727
          if (MCycle == 3'b111 )
2728
            begin
2729
              if (Mode == 0 )
2730
                begin
2731
                  TStates = 3'b101;
2732
                end
2733
              if (ISet != 2'b01 )
2734
                begin
2735
                  Set_Addr_To = aXY;
2736
                end
2737
              Set_BusB_To[2:0] = SSS;
2738
              Set_BusB_To[3] = 1'b0;
2739
              if (IRB == 8'b00110110 || ISet == 2'b01 )
2740
                begin
2741
                  // LD (HL),n
2742
                  Inc_PC = 1'b1;
2743
                end
2744
              else
2745
                begin
2746
                  NoRead = 1'b1;
2747
                end
2748
            end
2749
        end // if (Mode < 2 )      
2750
 
2751
    end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
2752
 
2753
// synopsys dc_script_begin
2754
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.1 2004-05-16 17:39:57 ghutchis Exp $" -type string -quiet
2755
// synopsys dc_script_end
2756
endmodule // T80_MCode
2757
 
2758
 
2759
 

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