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      Trace: <span class="bcsep">»</span> <a href="http://192.168.1.1/dokuwiki/doku.php?id=start" class="breadcrumbs" title="start">start</a> <span class="bcsep">»</span> <span class="curid"><a href="http://192.168.1.1/dokuwiki/doku.php?id=rgen.py" class="breadcrumbs" title="rgen.py">rgen.py</a></span>          </div>
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  <div class="page">
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    <!-- wikipage start -->
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    <div class="toc">
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<div class="tocheader toctoggle" id="toc__header"><img alt="-" src="rgen_doc_files/arrow_up.gif" id="toc__hide"><img style="display: none;" alt="+" src="rgen_doc_files/arrow_down.gif" id="toc__show">Table of Contents</div>
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<div id="toc__inside">
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<ul class="toc">
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<li class="level1"><div class="li"><span class="li"><a href="#rgen_register_file_and_decoder_generator" class="toc">rgen Register File and Decoder Generator</a></span></div></li>
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<li class="level1"><div class="li"><span class="li"><a href="#register_file_generator" class="toc">Register File Generator</a></span></div>
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<ul class="toc">
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<li class="level2"><div class="li"><span class="li"><a href="#tag_definitions" class="toc">Tag Definitions</a></span></div>
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<ul class="toc">
68 
<li class="level3"><div class="li"><span class="li"><a href="#config" class="toc">config</a></span></div></li>
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<li class="level3"><div class="li"><span class="li"><a href="#status" class="toc">status</a></span></div></li>
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<li class="level3"><div class="li"><span class="li"><a href="#count" class="toc">count</a></span></div></li>
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<li class="level3"><div class="li"><span class="li"><a href="#int_msk" class="toc">int_msk</a></span></div></li>
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<li class="level3"><div class="li"><span class="li"><a href="#soft_set" class="toc">soft_set</a></span></div></li>
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<li class="level3"><div class="li"><span class="li"><a href="#write_stb" class="toc">write_stb</a></span></div></li>
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<li class="level3"><div class="li"><span class="li"><a href="#read_stb" class="toc">read_stb</a></span></div></li>
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<li class="level3"><div class="li"><span class="li"><a href="#ext_load" class="toc">ext_load</a></span></div></li>
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<li class="level3"><div class="li"><span class="li"><a href="#user" class="toc">user</a></span></div></li>
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</ul>
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</li>
79 
</ul>
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</li>
81 
<li class="level1"><div class="li"><span class="li"><a href="#decoder_generator" class="toc">Decoder Generator</a></span></div></li></ul>
82 
</div>
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</div>
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87 
<h1><a name="rgen_register_file_and_decoder_generator" id="rgen_register_file_and_decoder_generator">rgen Register File and Decoder Generator</a></h1>
88 
<div class="level1">
89 
 
90 
<p> rgen is a Python script for generating a hierarchical set of
91 
register files and address decoders. It supports a variety of register
92 
types and multiple levels of address decoding hieararchy.
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</p>
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</div>
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<h1><a name="register_file_generator" id="register_file_generator">Register File Generator</a></h1>
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<div class="level1">
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</div>
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<div class="secedit"><form class="button" method="post" action="/dokuwiki/doku.php"><div class="no"><input name="do" value="edit" type="hidden"><input name="lines" value="249-286" type="hidden"><input name="rev" value="1298592735" type="hidden"><input name="id" value="rgen.py" type="hidden"><input value="Edit" class="button" title="Register File Generator" type="submit"></div></form></div>
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<h2><a name="tag_definitions" id="tag_definitions">Tag Definitions</a></h2>
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<div class="level2">
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<table class="inline">
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        <tbody><tr>
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                <th>tag name</th><th>attributes</th><th>description</th>
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        </tr>
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        <tr>
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                <td>tv_registers</td><td>name,addr_sz,data_sz,base_addr,registered_read</td><td>top-level tag for a register file</td>
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        </tr>
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        <tr>
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                <td>register</td><td>name,type,width,default</td><td>tag for a single logical register</td>
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        </tr>
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        <tr>
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                <td>field</td><td>name,width,default</td><td>tag for a bit field within a single register</td>
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        </tr>
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</tbody></table>
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<table class="inline">
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        <tbody><tr>
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                <th>register type</th><th>Access</th><th>description</th>
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        </tr>
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        <tr>
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                <td><a href="#config" title="rgen.py ↵" class="wikilink1">config</a></td><td>RW</td><td>General read-write configuration register</td>
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        </tr>
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        <tr>
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                <td><a href="#status" title="rgen.py ↵" class="wikilink1">status</a></td><td>RO</td><td>Read-only status register</td>
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        </tr>
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        <tr>
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                <td><a href="#count" title="rgen.py ↵" class="wikilink1">count</a></td><td>RW</td><td>Incrementing statistics register</td>
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        </tr>
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        <tr>
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                <td><a href="#int_msk" title="rgen.py ↵" class="wikilink1">int_msk</a></td><td>Special</td><td>Interrupt status &amp; mask registers</td>
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        </tr>
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        <tr>
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                <td><a href="#soft_set" title="rgen.py ↵" class="wikilink1">soft_set</a></td><td>RW</td><td>Software set, hardware clear register</td>
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        </tr>
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        <tr>
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                <td><a href="#write_stb" title="rgen.py ↵" class="wikilink1">write_stb</a></td><td>RW</td><td>Configuration register with additional strobe output</td>
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        </tr>
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        <tr>
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                <td><a href="#read_stb" title="rgen.py ↵" class="wikilink1">read_stb</a></td><td>RW</td><td>Configuration register with additional strobe outout</td>
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        </tr>
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        <tr>
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                <td><a href="#ext_load" title="rgen.py ↵" class="wikilink1">ext_load</a></td><td>RW</td><td>External-load register</td>
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        </tr>
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        <tr>
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                <td><a href="#user" title="rgen.py ↵" class="wikilink1">user</a></td><td>Special</td><td>User-defined pass-through register</td>
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        </tr>
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</tbody></table>
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</div>
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<h3><a name="config" id="config">config</a></h3>
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<div class="level3">
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<table class="inline">
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        <tbody><tr>
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                <th>port name</th><th>direction</th><th>size</th><th>description</th>
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        </tr>
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        <tr>
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                <td>NAME</td><td>output</td><td>WIDTH</td><td>Read-only value of config bits</td>
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        </tr>
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</tbody></table>
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<p>
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 Basic configuration register, read/write by the configuration side, register bits available read-only from the hardware side.
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</p>
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</div>
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<h3><a name="status" id="status">status</a></h3>
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<div class="level3">
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<table class="inline">
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        <tbody><tr>
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                <th>port name</th><th>direction</th><th>size</th><th>description</th>
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        </tr>
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        <tr>
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                <td>NAME</td><td>input</td><td>WIDTH</td><td>status input bits</td>
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        </tr>
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</tbody></table>
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<p>
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 Status register, read-only by the config side, status bits are combinatorial input from the hardware side.
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</p>
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</div>
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<h3><a name="count" id="count">count</a></h3>
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<div class="level3">
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<table class="inline">
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        <tbody><tr>
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                <th>port name</th><th>direction</th><th>size</th><th>description</th>
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        </tr>
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        <tr>
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                <td>NAME</td><td>output</td><td>WIDTH</td><td>current count value</td>
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        </tr>
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        <tr>
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                <td>NAME_inc</td><td>input</td><td>1</td><td>When high, increment count by 1</td>
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        </tr>
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</tbody></table>
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<p> Basic statistics register. Read/write by config side, count value
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available read-only from hardware side. Increment value provided for
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hardware side.
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</p>
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</div>
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<h3><a name="int_msk" id="int_msk">int_msk</a></h3>
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<div class="level3">
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<table class="inline">
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        <tbody><tr>
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                <th>port name</th><th>direction</th><th>size</th><th>description</th>
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        </tr>
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        <tr>
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                <td>NAME_set</td><td>input</td><td>WIDTH</td><td>set interrupt</td>
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        </tr>
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</tbody></table>
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<p> The int_msk register type provides a pair of interrupt registers.
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The first register is the interrupt status register, and the second is
221 
the interrupt mask register. The interrupt status register can be set
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by hardware and cleared by software by writing a ‘1’ to the bit which
223 
should be cleared. Software cannot set any bits in the interrupt
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register, and writing ‘0’ to a bit has no effect (leave unchanged).
225 
</p>
226 
 
227 
<p>The paired mask register has the same number of bits as the status
228 
register, but each bit set in the mask register disables interrupt
229 
generation for the corresponding status bit. Note that even if
230 
interrupt generation is disabled, the status bit will still be set. The
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mask register is Read/Write by software.
232 
</p>
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<p>The default attribute for this register type sets the default value
235 
of the mask register; the default value of the status register is
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always zero.
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</p>
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</div>
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<h3><a name="soft_set" id="soft_set">soft_set</a></h3>
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<div class="level3">
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<table class="inline">
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        <tbody><tr>
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                <th>port name</th><th>direction</th><th>size</th><th>description</th>
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        </tr>
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        <tr>
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                <td>NAME</td><td>output</td><td>WIDTH</td><td>Read-only value of config bits</td>
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        </tr>
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        <tr>
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                <td>NAME_clr</td><td>input</td><td>WIDTH</td><td>Read-only value of config bits</td>
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        </tr>
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</tbody></table>
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</div>
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<h3><a name="write_stb" id="write_stb">write_stb</a></h3>
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<div class="level3">
259 
<table class="inline">
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        <tbody><tr>
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                <th>port name</th><th>direction</th><th>size</th><th>description</th>
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        </tr>
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        <tr>
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                <td>NAME</td><td>output</td><td>WIDTH</td><td>Read-only value of config bits</td>
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        </tr>
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        <tr>
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                <td>NAME_wr_stb</td><td>output</td><td>1</td><td>Pulses on write to this register</td>
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        </tr>
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</tbody></table>
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271 
</div>
272 
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<h3><a name="read_stb" id="read_stb">read_stb</a></h3>
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<div class="level3">
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<table class="inline">
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        <tbody><tr>
277 
                <th>port name</th><th>direction</th><th>size</th><th>description</th>
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        </tr>
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        <tr>
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                <td>NAME</td><td>output</td><td>WIDTH</td><td>Read-only value of config bits</td>
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        </tr>
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        <tr>
283 
                <td>NAME_wr_stb</td><td>output</td><td>1</td><td>Pulses on read to this register</td>
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        </tr>
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</tbody></table>
286 
 
287 
</div>
288 
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289 
<h3><a name="ext_load" id="ext_load">ext_load</a></h3>
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<div class="level3">
291 
<table class="inline">
292 
        <tbody><tr>
293 
                <th>port name</th><th>direction</th><th>size</th><th>description</th>
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        </tr>
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        <tr>
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                <td>NAME_out</td><td>output</td><td>WIDTH</td><td>Data from config interface</td>
297 
        </tr>
298 
        <tr>
299 
                <td>NAME_in</td><td>input</td><td>WIDTH</td><td>Sample data in to config interface</td>
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        </tr>
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        <tr>
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                <td>NAME_wr_stb</td><td>output</td><td>1</td><td>Pulsed on final write operation</td>
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        </tr>
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        <tr>
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                <td>NAME_rd_stb</td><td>output</td><td>1</td><td>Pulsed on initial read operation</td>
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        </tr>
307 
</tbody></table>
308 
 
309 
<p> An external-load register is used to sample and cache values which
310 
may be changing over time. It is intended to be used for values which
311 
are wider than the configuration interface (otherwise, a <a href="#status" title="rgen.py ↵" class="wikilink1">status</a> or <a href="#write_stb" title="rgen.py ↵" class="wikilink1">write_stb</a>
312 
register would be more appropriate). The width of an ext_load register
313 
can be wider than the data_sz width of the module, and rgen will split
314 
the logical register into multiple physical registers.
315 
</p>
316 
 
317 
<p>
318 
Current limitations: ext_load registers must be an even multiple of data_size otherwise syntax errors will result.
319 
</p>
320 
 
321 
</div>
322 
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<h3><a name="user" id="user">user</a></h3>
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<div class="level3">
325 
<table class="inline">
326 
        <tbody><tr>
327 
                <th>port name</th><th>direction</th><th>size</th><th>description</th>
328 
        </tr>
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        <tr>
330 
                <td>NAME_wr_data</td><td>output</td><td>WIDTH</td><td>Data from config on write</td>
331 
        </tr>
332 
        <tr>
333 
                <td>NAME_wr_stb</td><td>output</td><td>1</td><td>Asserted during write operation</td>
334 
        </tr>
335 
        <tr>
336 
                <td>NAME_wr_ack</td><td>input</td><td>1</td><td>Assert by HW side to acknowledge write</td>
337 
        </tr>
338 
        <tr>
339 
                <td>NAME_rd_data</td><td>input</td><td>WIDTH</td><td>Data to config on read</td>
340 
        </tr>
341 
        <tr>
342 
                <td>NAME_rd_stb</td><td>output</td><td>1</td><td>Asserted during read operation</td>
343 
        </tr>
344 
        <tr>
345 
                <td>NAME_rd_ack</td><td>input</td><td>1</td><td>Assert by HW side to acknowledge read</td>
346 
        </tr>
347 
</tbody></table>
348 
 
349 
<p> Register with user-defined behavior. Used to implement registers
350 
with read-side effects, or where config interface must arbitrate with
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the HW datapath for access to a resource. Provides full handshake for
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each of read and write operations.
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</p>
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<h1><a name="decoder_generator" id="decoder_generator">Decoder Generator</a></h1>
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<div class="level1">
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<p>
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 Decoders are created using a different set of tags from the register file generator.
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<table class="inline">
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        <tbody><tr>
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                <th>tag name</th><th>attributes</th><th>description</th>
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        </tr>
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        <tr>
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                <td>it_decoder</td><td>name,addr_sz,data_sz</td><td>top-level tag for an address decoder</td>
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        </tr>
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        <tr>
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                <td>range</td><td>prefix,base,bits</td><td>tag for an address decode range</td>
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