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[/] [tv80/] [trunk/] [env/] [env_io.v] - Blame information for rev 115

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1 2 ghutchis 
 
2 
module env_io (/*AUTOARG*/
3 89 ghutchis 
  // Inouts
4 
  DI,
5 2 ghutchis 
  // Inputs
6 89 ghutchis 
  clk, iorq_n, rd_n, wr_n, addr, D_OUT
7 2 ghutchis 
  );
8 
 
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  input clk;
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  input iorq_n;
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  input rd_n;
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  input wr_n;
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  input [7:0] addr;
14 89 ghutchis 
  input [7:0] D_OUT;
15 2 ghutchis 
  inout [7:0] DI;
16 
 
17 
  reg [7:0]    io_data;
18 
 
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  reg [7:0]    str_buf [0:255];
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  reg          io_cs;
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  integer      buf_ptr, i;
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  reg [7:0]    timeout_ctl;
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  reg [15:0]   cur_timeout;
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  reg [15:0]   max_timeout;
26 
 
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  reg [7:0]    int_countdown;
28 89 ghutchis 
  reg [7:0]    nmi_countdown;
29 37 ghutchis 
  reg [7:0]    checksum;
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  reg [7:0]    ior_value;  // increment-on-read value
31 89 ghutchis 
  reg [7:0]    nmi_trigger; // trigger nmi when IR = this value
32 2 ghutchis 
 
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  assign       DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
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  initial
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    begin
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      io_cs = 0;
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      buf_ptr = 0;
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      cur_timeout = 0;
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      max_timeout = 10000;
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      timeout_ctl = 1;
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      int_countdown = 0;
43 89 ghutchis 
      nmi_countdown = 0;
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      nmi_trigger = 0;
45 2 ghutchis 
    end
46 37 ghutchis 
 
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  always @*
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    begin
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      if (!iorq_n & !rd_n)
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        begin
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          io_cs = (addr[7:5] == 3'b100);
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          case (addr)
54 53 ghutchis 
            8'h82 : io_data = timeout_ctl;
55 37 ghutchis 
            8'h83 : io_data = max_timeout[7:0];
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            8'h84 : io_data = max_timeout[15:8];
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            8'h90 : io_data = int_countdown;
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            8'h91 : io_data = checksum;
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            8'h93 : io_data = ior_value;
61 41 ghutchis 
            8'h94 : io_data = {$random};
62 89 ghutchis 
            8'h95 : io_data = nmi_countdown[7:0];
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            8'hA0 : io_data = nmi_trigger;
64 37 ghutchis 
            default : io_data = 8'hzz;
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          endcase // case(addr)
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        end // if (!iorq_n & !rd_n)
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    end // always @ *
68 75 ghutchis 
 
69 
  wire wr_stb;
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  reg last_iowrite;
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  assign wr_stb = (!iorq_n & !wr_n);
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74 2 ghutchis 
  always @(posedge clk)
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    begin
76 75 ghutchis 
      last_iowrite <= #1 wr_stb;
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      if (!wr_stb & last_iowrite)
78 2 ghutchis 
        case (addr)
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          8'h80 :
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            begin
81 89 ghutchis 
              case (D_OUT)
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                1 :
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                  begin
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                    tb_top.test_pass;
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                  end
86 2 ghutchis 
 
87 89 ghutchis 
                2 :
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                  begin
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                    tb_top.test_fail;
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                  end
91 2 ghutchis 
 
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                3 : tb_top.dumpon;
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                4 : tb_top.dumpoff;
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                default :
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                  begin
98 89 ghutchis 
                    $display ("%t: ERROR   : Unknown I/O command %x", $time, D_OUT);
99 2 ghutchis 
                  end
100 89 ghutchis 
              endcase // case(D_OUT)
101 2 ghutchis 
            end // case: :...
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          8'h81 :
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            begin
105 89 ghutchis 
              str_buf[buf_ptr] = D_OUT;
106 2 ghutchis 
              buf_ptr = buf_ptr + 1;
107 
 
108 89 ghutchis 
              //$display ("%t: DEBUG   : Detected write of character %x", $time, D_OUT);
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              if (D_OUT == 8'h0A)
110 2 ghutchis 
                begin
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                  $write ("%t: PROGRAM : ", $time);
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                  for (i=0; i<buf_ptr; i=i+1)
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                    $write ("%s", str_buf[i]);
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                  buf_ptr = 0;
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                end
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            end // case: 8'h81
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          8'h82 :
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            begin
122 89 ghutchis 
              timeout_ctl = D_OUT;
123 2 ghutchis 
            end
124 
 
125 89 ghutchis 
          8'h83 : max_timeout[7:0] = D_OUT;
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          8'h84 : max_timeout[15:8] = D_OUT;
127 2 ghutchis 
 
128 89 ghutchis 
          8'h90 : int_countdown = D_OUT;
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          8'h91 : checksum = D_OUT;
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          8'h92 : checksum = checksum + D_OUT;
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          8'h93 : ior_value = D_OUT;
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          8'h95 : nmi_countdown[7:0] = D_OUT;
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          8'hA0 : nmi_trigger = D_OUT;
134 2 ghutchis 
        endcase // case(addr)
135 
    end // always @ (posedge clk)
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137 
  always @(posedge clk)
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    begin
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      if (timeout_ctl[1])
140 
        cur_timeout = 0;
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      else if (timeout_ctl[0])
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        cur_timeout = cur_timeout + 1;
143 
 
144 
      if (cur_timeout >= max_timeout)
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        begin
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          $display ("%t: ERROR   : Reached timeout %d cycles", $time, max_timeout);
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          tb_top.test_fail;
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        end
149 
    end // always @ (posedge clk)
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151 
  always @(posedge clk)
152 
    begin
153 89 ghutchis 
      if (int_countdown == 0)
154 
        begin
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          tb_top.int_n  <= #1 1'b1;
156 
        end
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      else if (int_countdown == 1)
158 2 ghutchis 
        begin
159 
          tb_top.int_n  <= #1 1'b0;
160 89 ghutchis 
          //int_countdown = 0;
161 2 ghutchis 
        end
162 
      else if (int_countdown > 1)
163 31 ghutchis 
        begin
164 
          int_countdown = int_countdown - 1;
165 
          tb_top.int_n  <= #1 1'b1;
166 
        end
167 89 ghutchis 
 
168 
      // when nmi countdown reaches 1, an NMI will be issued.
169 
      // to clear the interrupt, write nmi_countdown to 0.
170 
      if ((nmi_countdown == 0) && (nmi_trigger == 0))
171 
        begin
172 
          tb_top.nmi_n  <= #1 1'b1;
173 
        end
174 
      else if (nmi_countdown == 1)
175 
        begin
176 
          tb_top.nmi_n  <= #1 1'b0;
177 
        end
178 
      else if (nmi_countdown > 1)
179 
        begin
180 
          nmi_countdown = nmi_countdown - 1;
181 
          tb_top.nmi_n  <= #1 1'b1;
182 
        end
183 
 
184 
      // when IR equals the target instruction, an NMI will be
185 
      // issued.  To clear the interrupt, write nmi_trigger to
186 
      // zero.
187 
      if (nmi_trigger != 0)
188 
        begin
189 
          if (nmi_trigger === tb_top.tv80s_inst.i_tv80_core.IR[7:0])
190 
            begin
191 
              tb_top.nmi_n <= #80 0;
192 
              tb_top.nmi_n <= #160 1;
193 
            end
194 
        end
195 
      else if (nmi_countdown == 0)
196 
        tb_top.nmi_n <= #1 1;
197 2 ghutchis 
    end
198 
 
199 
endmodule // env_io

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