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[/] [tv80/] [trunk/] [env/] [env_io.v] - Blame information for rev 84

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module env_io (/*AUTOARG*/
  // Outputs
  DI,
  // Inputs
  clk, iorq_n, rd_n, wr_n, addr, DO
  );
 
  input clk;
  input iorq_n;
  input rd_n;
  input wr_n;
  input [7:0] addr;
  input [7:0] DO;
  inout [7:0] DI;
 
  reg [7:0]    io_data;
 
  reg [7:0]    str_buf [0:255];
  reg          io_cs;
  integer      buf_ptr, i;
 
  reg [7:0]    timeout_ctl;
  reg [15:0]   cur_timeout;
  reg [15:0]   max_timeout;
 
  reg [7:0]    int_countdown;
  reg [7:0]    checksum;
  reg [7:0]    ior_value;  // increment-on-read value
 
  assign       DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
 
  initial
    begin
      io_cs = 0;
      buf_ptr = 0;
      cur_timeout = 0;
      max_timeout = 10000;
      timeout_ctl = 1;
      int_countdown = 0;
    end
 
  always @*
    begin
      if (!iorq_n & !rd_n)
        begin
          io_cs = (addr[7:5] == 3'b100);
 
          case (addr)
            8'h82 : io_data = timeout_ctl;
            8'h83 : io_data = max_timeout[7:0];
            8'h84 : io_data = max_timeout[15:8];
 
            8'h90 : io_data = int_countdown;
            8'h91 : io_data = checksum;
            8'h93 : io_data = ior_value;
            8'h94 : io_data = {$random};
            default : io_data = 8'hzz;
          endcase // case(addr)
        end // if (!iorq_n & !rd_n)
    end // always @ *
 
  wire wr_stb;
  reg last_iowrite;
 
  assign wr_stb = (!iorq_n & !wr_n);
 
  always @(posedge clk)
    begin
      last_iowrite <= #1 wr_stb;
      if (!wr_stb & last_iowrite)
        case (addr)
          8'h80 :
            begin
              case (DO)
                1 : tb_top.test_pass;
 
                2 : tb_top.test_fail;
 
                3 : tb_top.dumpon;
 
                4 : tb_top.dumpoff;
 
                default :
                  begin
                    $display ("%t: ERROR   : Unknown I/O command %x", $time, DO);
                  end
              endcase // case(DO)
            end // case: :...
 
          8'h81 :
            begin
              str_buf[buf_ptr] = DO;
              buf_ptr = buf_ptr + 1;
 
              //$display ("%t: DEBUG   : Detected write of character %x", $time, DO);
              if (DO == 8'h0A)
                begin
                  $write ("%t: PROGRAM : ", $time);
 
                  for (i=0; i<buf_ptr; i=i+1)
                    $write ("%s", str_buf[i]);
 
                  buf_ptr = 0;
                end
            end // case: 8'h81
 
          8'h82 :
            begin
              timeout_ctl = DO;
            end
 
          8'h83 : max_timeout[7:0] = DO;
          8'h84 : max_timeout[15:8] = DO;
 
          8'h90 : int_countdown = DO;
          8'h91 : checksum = DO;
          8'h92 : checksum = checksum + DO;
          8'h93 : ior_value = DO;
        endcase // case(addr)
    end // always @ (posedge clk)
 
  always @(posedge clk)
    begin
      if (timeout_ctl[1])
        cur_timeout = 0;
      else if (timeout_ctl[0])
        cur_timeout = cur_timeout + 1;
 
      if (cur_timeout >= max_timeout)
        begin
          $display ("%t: ERROR   : Reached timeout %d cycles", $time, max_timeout);
          tb_top.test_fail;
        end
    end // always @ (posedge clk)
 
  always @(posedge clk)
    begin
      if (int_countdown == 1)
        begin
          tb_top.int_n  <= #1 1'b0;
          int_countdown = 0;
        end
      else if (int_countdown > 1)
        begin
          int_countdown = int_countdown - 1;
          tb_top.int_n  <= #1 1'b1;
        end
    end
 
endmodule // env_io

Line No.	Rev	Author	Line
1	2	ghutchis
2			`module env_io (/AUTOARG/`
3			`// Outputs`
4			`DI,`
5			`// Inputs`
6			`clk, iorq_n, rd_n, wr_n, addr, DO`
7			`);`
8
9			`input clk;`
10			`input iorq_n;`
11			`input rd_n;`
12			`input wr_n;`
13			`input [7:0] addr;`
14			`input [7:0] DO;`
15			`inout [7:0] DI;`
16
17			`reg [7:0] io_data;`
18
19			`reg [7:0] str_buf [0:255];`
20			`reg io_cs;`
21			`integer buf_ptr, i;`
22
23			`reg [7:0] timeout_ctl;`
24			`reg [15:0] cur_timeout;`
25			`reg [15:0] max_timeout;`
26
27			`reg [7:0] int_countdown;`
28	37	ghutchis	`reg [7:0] checksum;`
29			`reg [7:0] ior_value; // increment-on-read value`
30	2	ghutchis
31			`assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};`
32
33			`initial`
34			`begin`
35			`io_cs = 0;`
36			`buf_ptr = 0;`
37			`cur_timeout = 0;`
38			`max_timeout = 10000;`
39			`timeout_ctl = 1;`
40			`int_countdown = 0;`
41			`end`
42	37	ghutchis
43			`always @*`
44			`begin`
45			`if (!iorq_n & !rd_n)`
46			`begin`
47			`io_cs = (addr[7:5] == 3'b100);`
48
49			`case (addr)`
50	53	ghutchis	`8'h82 : io_data = timeout_ctl;`
51	37	ghutchis	`8'h83 : io_data = max_timeout[7:0];`
52			`8'h84 : io_data = max_timeout[15:8];`
53
54			`8'h90 : io_data = int_countdown;`
55			`8'h91 : io_data = checksum;`
56			`8'h93 : io_data = ior_value;`
57	41	ghutchis	`8'h94 : io_data = {$random};`
58	37	ghutchis	`default : io_data = 8'hzz;`
59			`endcase // case(addr)`
60			`end // if (!iorq_n & !rd_n)`
61			`end // always @ *`
62	75	ghutchis
63			`wire wr_stb;`
64			`reg last_iowrite;`
65
66			`assign wr_stb = (!iorq_n & !wr_n);`
67
68	2	ghutchis	`always @(posedge clk)`
69			`begin`
70	75	ghutchis	`last_iowrite <= #1 wr_stb;`
71			`if (!wr_stb & last_iowrite)`
72	2	ghutchis	`case (addr)`
73			`8'h80 :`
74			`begin`
75			`case (DO)`
76			`1 : tb_top.test_pass;`
77
78			`2 : tb_top.test_fail;`
79
80			`3 : tb_top.dumpon;`
81
82			`4 : tb_top.dumpoff;`
83
84			`default :`
85			`begin`
86			`$display ("%t: ERROR : Unknown I/O command %x", $time, DO);`
87			`end`
88			`endcase // case(DO)`
89			`end // case: :...`
90
91			`8'h81 :`
92			`begin`
93			`str_buf[buf_ptr] = DO;`
94			`buf_ptr = buf_ptr + 1;`
95
96			`//$display ("%t: DEBUG : Detected write of character %x", $time, DO);`
97			`if (DO == 8'h0A)`
98			`begin`
99			`$write ("%t: PROGRAM : ", $time);`
100
101			`for (i=0; i<buf_ptr; i=i+1)`
102			`$write ("%s", str_buf[i]);`
103
104			`buf_ptr = 0;`
105			`end`
106			`end // case: 8'h81`
107
108			`8'h82 :`
109			`begin`
110			`timeout_ctl = DO;`
111			`end`
112
113			`8'h83 : max_timeout[7:0] = DO;`
114			`8'h84 : max_timeout[15:8] = DO;`
115
116			`8'h90 : int_countdown = DO;`
117	37	ghutchis	`8'h91 : checksum = DO;`
118			`8'h92 : checksum = checksum + DO;`
119			`8'h93 : ior_value = DO;`
120	2	ghutchis	`endcase // case(addr)`
121			`end // always @ (posedge clk)`
122
123			`always @(posedge clk)`
124			`begin`
125			`if (timeout_ctl[1])`
126			`cur_timeout = 0;`
127			`else if (timeout_ctl[0])`
128			`cur_timeout = cur_timeout + 1;`
129
130			`if (cur_timeout >= max_timeout)`
131			`begin`
132			`$display ("%t: ERROR : Reached timeout %d cycles", $time, max_timeout);`
133			`tb_top.test_fail;`
134			`end`
135			`end // always @ (posedge clk)`
136
137			`always @(posedge clk)`
138			`begin`
139			`if (int_countdown == 1)`
140			`begin`
141			`tb_top.int_n <= #1 1'b0;`
142			`int_countdown = 0;`
143			`end`
144			`else if (int_countdown > 1)`
145	31	ghutchis	`begin`
146			`int_countdown = int_countdown - 1;`
147			`tb_top.int_n <= #1 1'b1;`
148			`end`
149	2	ghutchis	`end`
150
151			`endmodule // env_io`

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[/] [tv80/] [trunk/] [env/] [env_io.v] - Blame information for rev 84