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1 2 ghutchis
//
2
// TV80 8-Bit Microprocessor Core
3
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
4
//
5
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
6
//
7
// Permission is hereby granted, free of charge, to any person obtaining a 
8
// copy of this software and associated documentation files (the "Software"), 
9
// to deal in the Software without restriction, including without limitation 
10
// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
11
// and/or sell copies of the Software, and to permit persons to whom the 
12
// Software is furnished to do so, subject to the following conditions:
13
//
14
// The above copyright notice and this permission notice shall be included 
15
// in all copies or substantial portions of the Software.
16
//
17
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
18
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
19
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
20
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
21
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
22
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
23
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24
 
25
module tv80_core (/*AUTOARG*/
26
  // Outputs
27
  m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, do, mc, ts,
28
  intcycle_n, IntE, stop,
29
  // Inputs
30
  reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
31
  );
32
  // Beginning of automatic inputs (from unused autoinst inputs)
33
  // End of automatics
34
 
35 60 ghutchis
  parameter Mode = 1;   // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
36
  parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
37 2 ghutchis
  parameter Flag_C = 0;
38
  parameter Flag_N = 1;
39
  parameter Flag_P = 2;
40
  parameter Flag_X = 3;
41
  parameter Flag_H = 4;
42
  parameter Flag_Y = 5;
43
  parameter Flag_Z = 6;
44
  parameter Flag_S = 7;
45
 
46 60 ghutchis
  input     reset_n;
47
  input     clk;
48
  input     cen;
49
  input     wait_n;
50
  input     int_n;
51
  input     nmi_n;
52
  input     busrq_n;
53
  output    m1_n;
54
  output    iorq;
55
  output    no_read;
56
  output    write;
57
  output    rfsh_n;
58
  output    halt_n;
59
  output    busak_n;
60 2 ghutchis
  output [15:0] A;
61 60 ghutchis
  input [7:0]   dinst;
62
  input [7:0]   di;
63
  output [7:0]  do;
64
  output [6:0]  mc;
65
  output [6:0]  ts;
66
  output        intcycle_n;
67
  output        IntE;
68
  output        stop;
69 2 ghutchis
 
70 60 ghutchis
  reg    m1_n;
71 87 ghutchis
  reg    iorq;
72
`ifdef TV80_REFRESH
73
  reg    rfsh_n;
74
`endif
75 60 ghutchis
  reg    halt_n;
76
  reg    busak_n;
77 2 ghutchis
  reg [15:0] A;
78 60 ghutchis
  reg [7:0]  do;
79
  reg [6:0]  mc;
80
  reg [6:0]  ts;
81
  reg   intcycle_n;
82
  reg   IntE;
83
  reg   stop;
84 2 ghutchis
 
85 60 ghutchis
  parameter     aNone    = 3'b111;
86
  parameter     aBC      = 3'b000;
87
  parameter     aDE      = 3'b001;
88
  parameter     aXY      = 3'b010;
89
  parameter     aIOA     = 3'b100;
90
  parameter     aSP      = 3'b101;
91
  parameter     aZI      = 3'b110;
92 2 ghutchis
 
93
  // Registers
94
  reg [7:0]     ACC, F;
95
  reg [7:0]     Ap, Fp;
96
  reg [7:0]     I;
97 87 ghutchis
`ifdef TV80_REFRESH
98 2 ghutchis
  reg [7:0]     R;
99 87 ghutchis
`endif
100 2 ghutchis
  reg [15:0]    SP, PC;
101
  reg [7:0]     RegDIH;
102
  reg [7:0]     RegDIL;
103
  wire [15:0]   RegBusA;
104
  wire [15:0]   RegBusB;
105
  wire [15:0]   RegBusC;
106
  reg [2:0]     RegAddrA_r;
107
  reg [2:0]     RegAddrA;
108
  reg [2:0]     RegAddrB_r;
109
  reg [2:0]     RegAddrB;
110
  reg [2:0]     RegAddrC;
111
  reg           RegWEH;
112
  reg           RegWEL;
113
  reg           Alternate;
114
 
115
  // Help Registers
116 60 ghutchis
  reg [15:0]    TmpAddr;        // Temporary address register
117
  reg [7:0]     IR;             // Instruction register
118
  reg [1:0]     ISet;           // Instruction set selector
119 2 ghutchis
  reg [15:0]    RegBusA_r;
120
 
121
  reg [15:0]    ID16;
122
  reg [7:0]     Save_Mux;
123
 
124 21 ghutchis
  reg [6:0]     tstate;
125
  reg [6:0]     mcycle;
126
  reg           last_mcycle, last_tstate;
127 2 ghutchis
  reg           IntE_FF1;
128
  reg           IntE_FF2;
129
  reg           Halt_FF;
130
  reg           BusReq_s;
131
  reg           BusAck;
132
  reg           ClkEn;
133
  reg           NMI_s;
134
  reg           INT_s;
135
  reg [1:0]     IStatus;
136
 
137
  reg [7:0]     DI_Reg;
138
  reg           T_Res;
139
  reg [1:0]     XY_State;
140
  reg [2:0]     Pre_XY_F_M;
141
  reg           NextIs_XY_Fetch;
142
  reg           XY_Ind;
143
  reg           No_BTR;
144
  reg           BTR_r;
145
  reg           Auto_Wait;
146
  reg           Auto_Wait_t1;
147
  reg           Auto_Wait_t2;
148
  reg           IncDecZ;
149
 
150
  // ALU signals
151
  reg [7:0]     BusB;
152
  reg [7:0]     BusA;
153
  wire [7:0]    ALU_Q;
154
  wire [7:0]    F_Out;
155
 
156
  // Registered micro code outputs
157
  reg [4:0]     Read_To_Reg_r;
158
  reg           Arith16_r;
159
  reg           Z16_r;
160
  reg [3:0]     ALU_Op_r;
161
  reg           Save_ALU_r;
162
  reg           PreserveC_r;
163
  reg [2:0]     mcycles;
164
 
165
  // Micro code outputs
166
  wire [2:0]    mcycles_d;
167
  wire [2:0]    tstates;
168
  reg           IntCycle;
169
  reg           NMICycle;
170
  wire          Inc_PC;
171
  wire          Inc_WZ;
172
  wire [3:0]    IncDec_16;
173
  wire [1:0]    Prefix;
174
  wire          Read_To_Acc;
175
  wire          Read_To_Reg;
176
  wire [3:0]     Set_BusB_To;
177
  wire [3:0]     Set_BusA_To;
178
  wire [3:0]     ALU_Op;
179
  wire           Save_ALU;
180
  wire           PreserveC;
181
  wire           Arith16;
182
  wire [2:0]     Set_Addr_To;
183
  wire           Jump;
184
  wire           JumpE;
185
  wire           JumpXY;
186
  wire           Call;
187
  wire           RstP;
188
  wire           LDZ;
189
  wire           LDW;
190
  wire           LDSPHL;
191
  wire           iorq_i;
192
  wire [2:0]     Special_LD;
193
  wire           ExchangeDH;
194
  wire           ExchangeRp;
195
  wire           ExchangeAF;
196
  wire           ExchangeRS;
197
  wire           I_DJNZ;
198
  wire           I_CPL;
199
  wire           I_CCF;
200
  wire           I_SCF;
201
  wire           I_RETN;
202
  wire           I_BT;
203
  wire           I_BC;
204
  wire           I_BTR;
205
  wire           I_RLD;
206
  wire           I_RRD;
207
  wire           I_INRC;
208
  wire           SetDI;
209
  wire           SetEI;
210
  wire [1:0]     IMode;
211
  wire           Halt;
212
 
213
  reg [15:0]     PC16;
214
  reg [15:0]     PC16_B;
215
  reg [15:0]     SP16, SP16_A, SP16_B;
216
  reg [15:0]     ID16_B;
217
  reg            Oldnmi_n;
218
 
219
  tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode
220
    (
221
     .IR                   (IR),
222
     .ISet                 (ISet),
223
     .MCycle               (mcycle),
224
     .F                    (F),
225
     .NMICycle             (NMICycle),
226
     .IntCycle             (IntCycle),
227
     .MCycles              (mcycles_d),
228
     .TStates              (tstates),
229
     .Prefix               (Prefix),
230
     .Inc_PC               (Inc_PC),
231
     .Inc_WZ               (Inc_WZ),
232
     .IncDec_16            (IncDec_16),
233
     .Read_To_Acc          (Read_To_Acc),
234
     .Read_To_Reg          (Read_To_Reg),
235
     .Set_BusB_To          (Set_BusB_To),
236
     .Set_BusA_To          (Set_BusA_To),
237
     .ALU_Op               (ALU_Op),
238
     .Save_ALU             (Save_ALU),
239
     .PreserveC            (PreserveC),
240
     .Arith16              (Arith16),
241
     .Set_Addr_To          (Set_Addr_To),
242
     .IORQ                 (iorq_i),
243
     .Jump                 (Jump),
244
     .JumpE                (JumpE),
245
     .JumpXY               (JumpXY),
246
     .Call                 (Call),
247
     .RstP                 (RstP),
248
     .LDZ                  (LDZ),
249
     .LDW                  (LDW),
250
     .LDSPHL               (LDSPHL),
251
     .Special_LD           (Special_LD),
252
     .ExchangeDH           (ExchangeDH),
253
     .ExchangeRp           (ExchangeRp),
254
     .ExchangeAF           (ExchangeAF),
255
     .ExchangeRS           (ExchangeRS),
256
     .I_DJNZ               (I_DJNZ),
257
     .I_CPL                (I_CPL),
258
     .I_CCF                (I_CCF),
259
     .I_SCF                (I_SCF),
260
     .I_RETN               (I_RETN),
261
     .I_BT                 (I_BT),
262
     .I_BC                 (I_BC),
263
     .I_BTR                (I_BTR),
264
     .I_RLD                (I_RLD),
265
     .I_RRD                (I_RRD),
266
     .I_INRC               (I_INRC),
267
     .SetDI                (SetDI),
268
     .SetEI                (SetEI),
269
     .IMode                (IMode),
270
     .Halt                 (Halt),
271
     .NoRead               (no_read),
272
     .Write                (write)
273
     );
274
 
275
  tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu
276
    (
277
     .Arith16              (Arith16_r),
278
     .Z16                  (Z16_r),
279
     .ALU_Op               (ALU_Op_r),
280
     .IR                   (IR[5:0]),
281
     .ISet                 (ISet),
282
     .BusA                 (BusA),
283
     .BusB                 (BusB),
284
     .F_In                 (F),
285
     .Q                    (ALU_Q),
286
     .F_Out                (F_Out)
287
     );
288
 
289 21 ghutchis
  function [6:0] number_to_bitvec;
290
    input [2:0] num;
291
    begin
292
      case (num)
293
        1 : number_to_bitvec = 7'b0000001;
294
        2 : number_to_bitvec = 7'b0000010;
295
        3 : number_to_bitvec = 7'b0000100;
296
        4 : number_to_bitvec = 7'b0001000;
297
        5 : number_to_bitvec = 7'b0010000;
298
        6 : number_to_bitvec = 7'b0100000;
299
        7 : number_to_bitvec = 7'b1000000;
300
        default : number_to_bitvec = 7'bx;
301
      endcase // case(num)
302
    end
303
  endfunction // number_to_bitvec
304
 
305
  always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
306
    begin
307
      case (mcycles)
308
        1 : last_mcycle = mcycle[0];
309
        2 : last_mcycle = mcycle[1];
310
        3 : last_mcycle = mcycle[2];
311
        4 : last_mcycle = mcycle[3];
312
        5 : last_mcycle = mcycle[4];
313
        6 : last_mcycle = mcycle[5];
314
        7 : last_mcycle = mcycle[6];
315
        default : last_mcycle = 1'bx;
316
      endcase // case(mcycles)
317
 
318
      case (tstates)
319
 
320
        1 : last_tstate = tstate[1];
321
        2 : last_tstate = tstate[2];
322
        3 : last_tstate = tstate[3];
323
        4 : last_tstate = tstate[4];
324
        5 : last_tstate = tstate[5];
325
        6 : last_tstate = tstate[6];
326
        default : last_tstate = 1'bx;
327
      endcase
328
    end // always @ (...
329
 
330
 
331 2 ghutchis
  always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg
332 21 ghutchis
           or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind
333
           or XY_State or cen or last_tstate or mcycle)
334 2 ghutchis
    begin
335
      ClkEn = cen && ~ BusAck;
336
 
337 21 ghutchis
      if (last_tstate)
338 2 ghutchis
        T_Res = 1'b1;
339
      else T_Res = 1'b0;
340
 
341
      if (XY_State != 2'b00 && XY_Ind == 1'b0 &&
342 60 ghutchis
          ((Set_Addr_To == aXY) ||
343
           (mcycle[0] && IR == 8'b11001011) ||
344
           (mcycle[0] && IR == 8'b00110110)))
345 2 ghutchis
        NextIs_XY_Fetch = 1'b1;
346
      else
347
        NextIs_XY_Fetch = 1'b0;
348
 
349
      if (ExchangeRp)
350
        Save_Mux = BusB;
351
      else if (!Save_ALU_r)
352
        Save_Mux = DI_Reg;
353
      else
354
        Save_Mux = ALU_Q;
355
    end // always @ *
356
 
357
  always @ (posedge clk)
358
    begin
359
      if (reset_n == 1'b0 )
360
        begin
361 60 ghutchis
          PC <= #1 0;  // Program Counter
362
          A <= #1 0;
363
          TmpAddr <= #1 0;
364
          IR <= #1 8'b00000000;
365
          ISet <= #1 2'b00;
366
          XY_State <= #1 2'b00;
367
          IStatus <= #1 2'b00;
368
          mcycles <= #1 3'b000;
369
          do <= #1 8'b00000000;
370 2 ghutchis
 
371 60 ghutchis
          ACC <= #1 8'hFF;
372
          F <= #1 8'hFF;
373
          Ap <= #1 8'hFF;
374
          Fp <= #1 8'hFF;
375
          I <= #1 0;
376
          `ifdef TV80_REFRESH
377
          R <= #1 0;
378
          `endif
379
          SP <= #1 16'hFFFF;
380
          Alternate <= #1 1'b0;
381 2 ghutchis
 
382 60 ghutchis
          Read_To_Reg_r <= #1 5'b00000;
383
          Arith16_r <= #1 1'b0;
384
          BTR_r <= #1 1'b0;
385
          Z16_r <= #1 1'b0;
386
          ALU_Op_r <= #1 4'b0000;
387
          Save_ALU_r <= #1 1'b0;
388
          PreserveC_r <= #1 1'b0;
389
          XY_Ind <= #1 1'b0;
390
        end
391 2 ghutchis
      else
392
        begin
393
 
394 60 ghutchis
          if (ClkEn == 1'b1 )
395 2 ghutchis
            begin
396
 
397 60 ghutchis
              ALU_Op_r <= #1 4'b0000;
398
              Save_ALU_r <= #1 1'b0;
399
              Read_To_Reg_r <= #1 5'b00000;
400 2 ghutchis
 
401 60 ghutchis
              mcycles <= #1 mcycles_d;
402 2 ghutchis
 
403 60 ghutchis
              if (IMode != 2'b11 )
404 2 ghutchis
                begin
405 60 ghutchis
                  IStatus <= #1 IMode;
406
                end
407 2 ghutchis
 
408 60 ghutchis
              Arith16_r <= #1 Arith16;
409
              PreserveC_r <= #1 PreserveC;
410
              if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] )
411 2 ghutchis
                begin
412 60 ghutchis
                  Z16_r <= #1 1'b1;
413
                end
414 2 ghutchis
              else
415
                begin
416 60 ghutchis
                  Z16_r <= #1 1'b0;
417
                end
418 2 ghutchis
 
419 60 ghutchis
              if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] ))
420 2 ghutchis
                begin
421 60 ghutchis
                  // mcycle == 1 && tstate == 1, 2, || 3
422
                  if (tstate[2] && wait_n == 1'b1 )
423 2 ghutchis
                    begin
424 60 ghutchis
                      `ifdef TV80_REFRESH
425
                      if (Mode < 2 )
426 2 ghutchis
                        begin
427 60 ghutchis
                          A[7:0] <= #1 R;
428
                          A[15:8] <= #1 I;
429
                          R[6:0] <= #1 R[6:0] + 1;
430
                        end
431
                      `endif
432
                      if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) )
433 2 ghutchis
                        begin
434 60 ghutchis
                          PC <= #1 PC16;
435
                        end
436 2 ghutchis
 
437 60 ghutchis
                      if (IntCycle == 1'b1 && IStatus == 2'b01 )
438 2 ghutchis
                        begin
439 60 ghutchis
                          IR <= #1 8'b11111111;
440
                        end
441 2 ghutchis
                      else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 )
442
                        begin
443 60 ghutchis
                          IR <= #1 8'b00000000;
444
                        end
445 2 ghutchis
                      else
446
                        begin
447 60 ghutchis
                          IR <= #1 dinst;
448
                        end
449 2 ghutchis
 
450 60 ghutchis
                      ISet <= #1 2'b00;
451
                      if (Prefix != 2'b00 )
452 2 ghutchis
                        begin
453 60 ghutchis
                          if (Prefix == 2'b11 )
454 2 ghutchis
                            begin
455 60 ghutchis
                              if (IR[5] == 1'b1 )
456 2 ghutchis
                                begin
457 60 ghutchis
                                  XY_State <= #1 2'b10;
458
                                end
459 2 ghutchis
                              else
460
                                begin
461 60 ghutchis
                                  XY_State <= #1 2'b01;
462
                                end
463
                            end
464 2 ghutchis
                          else
465
                            begin
466 60 ghutchis
                              if (Prefix == 2'b10 )
467 2 ghutchis
                                begin
468 60 ghutchis
                                  XY_State <= #1 2'b00;
469
                                  XY_Ind <= #1 1'b0;
470
                                end
471
                              ISet <= #1 Prefix;
472
                            end
473
                        end
474 2 ghutchis
                      else
475
                        begin
476 60 ghutchis
                          XY_State <= #1 2'b00;
477
                          XY_Ind <= #1 1'b0;
478
                        end
479
                    end // if (tstate == 2 && wait_n == 1'b1 )
480 2 ghutchis
 
481
 
482 60 ghutchis
                end
483 2 ghutchis
              else
484
                begin
485 60 ghutchis
                  // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3)
486 2 ghutchis
 
487 60 ghutchis
                  if (mcycle[5] )
488 2 ghutchis
                    begin
489 60 ghutchis
                      XY_Ind <= #1 1'b1;
490
                      if (Prefix == 2'b01 )
491 2 ghutchis
                        begin
492 60 ghutchis
                          ISet <= #1 2'b01;
493
                        end
494
                    end
495 2 ghutchis
 
496 60 ghutchis
                  if (T_Res == 1'b1 )
497 2 ghutchis
                    begin
498 60 ghutchis
                      BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR;
499
                      if (Jump == 1'b1 )
500 2 ghutchis
                        begin
501 60 ghutchis
                          A[15:8] <= #1 DI_Reg;
502
                          A[7:0] <= #1 TmpAddr[7:0];
503
                          PC[15:8] <= #1 DI_Reg;
504
                          PC[7:0] <= #1 TmpAddr[7:0];
505
                        end
506 2 ghutchis
                      else if (JumpXY == 1'b1 )
507
                        begin
508 60 ghutchis
                          A <= #1 RegBusC;
509
                          PC <= #1 RegBusC;
510
                        end else if (Call == 1'b1 || RstP == 1'b1 )
511 2 ghutchis
                          begin
512 60 ghutchis
                            A <= #1 TmpAddr;
513
                            PC <= #1 TmpAddr;
514
                          end
515 21 ghutchis
                        else if (last_mcycle && NMICycle == 1'b1 )
516 2 ghutchis
                          begin
517 60 ghutchis
                            A <= #1 16'b0000000001100110;
518
                            PC <= #1 16'b0000000001100110;
519
                          end
520 21 ghutchis
                        else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
521 2 ghutchis
                          begin
522 60 ghutchis
                            A[15:8] <= #1 I;
523
                            A[7:0] <= #1 TmpAddr[7:0];
524
                            PC[15:8] <= #1 I;
525
                            PC[7:0] <= #1 TmpAddr[7:0];
526
                          end
527 2 ghutchis
                        else
528
                          begin
529 60 ghutchis
                            case (Set_Addr_To)
530
                              aXY :
531 2 ghutchis
                                begin
532 60 ghutchis
                                  if (XY_State == 2'b00 )
533 2 ghutchis
                                    begin
534 60 ghutchis
                                      A <= #1 RegBusC;
535
                                    end
536 2 ghutchis
                                  else
537
                                    begin
538 60 ghutchis
                                      if (NextIs_XY_Fetch == 1'b1 )
539 2 ghutchis
                                        begin
540 60 ghutchis
                                          A <= #1 PC;
541
                                        end
542 2 ghutchis
                                      else
543
                                        begin
544 60 ghutchis
                                          A <= #1 TmpAddr;
545
                                        end
546
                                    end // else: !if(XY_State == 2'b00 )
547 2 ghutchis
                                end // case: aXY
548
 
549 60 ghutchis
                              aIOA :
550 2 ghutchis
                                begin
551 60 ghutchis
                                  if (Mode == 3 )
552 2 ghutchis
                                    begin
553 60 ghutchis
                                      // Memory map I/O on GBZ80
554
                                      A[15:8] <= #1 8'hFF;
555
                                    end
556 2 ghutchis
                                  else if (Mode == 2 )
557
                                    begin
558 60 ghutchis
                                      // Duplicate I/O address on 8080
559
                                      A[15:8] <= #1 DI_Reg;
560
                                    end
561 2 ghutchis
                                  else
562
                                    begin
563 60 ghutchis
                                      A[15:8] <= #1 ACC;
564
                                    end
565
                                  A[7:0] <= #1 DI_Reg;
566 2 ghutchis
                                end // case: aIOA
567
 
568
 
569 60 ghutchis
                              aSP :
570 2 ghutchis
                                begin
571 60 ghutchis
                                  A <= #1 SP;
572 2 ghutchis
                                end
573
 
574 60 ghutchis
                              aBC :
575 2 ghutchis
                                begin
576 60 ghutchis
                                  if (Mode == 3 && iorq_i == 1'b1 )
577 2 ghutchis
                                    begin
578 60 ghutchis
                                      // Memory map I/O on GBZ80
579
                                      A[15:8] <= #1 8'hFF;
580
                                      A[7:0] <= #1 RegBusC[7:0];
581
                                    end
582 2 ghutchis
                                  else
583
                                    begin
584 60 ghutchis
                                      A <= #1 RegBusC;
585
                                    end
586 2 ghutchis
                                end // case: aBC
587
 
588 60 ghutchis
                              aDE :
589 2 ghutchis
                                begin
590 60 ghutchis
                                  A <= #1 RegBusC;
591 2 ghutchis
                                end
592
 
593 60 ghutchis
                              aZI :
594 2 ghutchis
                                begin
595 60 ghutchis
                                  if (Inc_WZ == 1'b1 )
596 2 ghutchis
                                    begin
597 60 ghutchis
                                      A <= #1 TmpAddr + 1;
598
                                    end
599 2 ghutchis
                                  else
600
                                    begin
601 60 ghutchis
                                      A[15:8] <= #1 DI_Reg;
602
                                      A[7:0] <= #1 TmpAddr[7:0];
603
                                    end
604 2 ghutchis
                                end // case: aZI
605
 
606 60 ghutchis
                              default   :
607 2 ghutchis
                                begin
608 60 ghutchis
                                  A <= #1 PC;
609 2 ghutchis
                                end
610 60 ghutchis
                            endcase // case(Set_Addr_To)
611 2 ghutchis
 
612 60 ghutchis
                          end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
613 2 ghutchis
 
614
 
615 60 ghutchis
                      Save_ALU_r <= #1 Save_ALU;
616
                      ALU_Op_r <= #1 ALU_Op;
617 2 ghutchis
 
618 60 ghutchis
                      if (I_CPL == 1'b1 )
619 2 ghutchis
                        begin
620 60 ghutchis
                          // CPL
621
                          ACC <= #1 ~ ACC;
622
                          F[Flag_Y] <= #1 ~ ACC[5];
623
                          F[Flag_H] <= #1 1'b1;
624
                          F[Flag_X] <= #1 ~ ACC[3];
625
                          F[Flag_N] <= #1 1'b1;
626
                        end
627
                      if (I_CCF == 1'b1 )
628 2 ghutchis
                        begin
629 60 ghutchis
                          // CCF
630
                          F[Flag_C] <= #1 ~ F[Flag_C];
631
                          F[Flag_Y] <= #1 ACC[5];
632
                          F[Flag_H] <= #1 F[Flag_C];
633
                          F[Flag_X] <= #1 ACC[3];
634
                          F[Flag_N] <= #1 1'b0;
635
                        end
636
                      if (I_SCF == 1'b1 )
637 2 ghutchis
                        begin
638 60 ghutchis
                          // SCF
639
                          F[Flag_C] <= #1 1'b1;
640
                          F[Flag_Y] <= #1 ACC[5];
641
                          F[Flag_H] <= #1 1'b0;
642
                          F[Flag_X] <= #1 ACC[3];
643
                          F[Flag_N] <= #1 1'b0;
644
                        end
645
                    end // if (T_Res == 1'b1 )
646 2 ghutchis
 
647
 
648 60 ghutchis
                  if (tstate[2] && wait_n == 1'b1 )
649 2 ghutchis
                    begin
650 60 ghutchis
                      if (ISet == 2'b01 && mcycle[6] )
651 2 ghutchis
                        begin
652 60 ghutchis
                          IR <= #1 dinst;
653
                        end
654
                      if (JumpE == 1'b1 )
655 2 ghutchis
                        begin
656
                          PC <= #1 PC16;
657 60 ghutchis
                        end
658 2 ghutchis
                      else if (Inc_PC == 1'b1 )
659
                        begin
660 60 ghutchis
                          //PC <= #1 PC + 1;
661 2 ghutchis
                          PC <= #1 PC16;
662 60 ghutchis
                        end
663
                      if (BTR_r == 1'b1 )
664 2 ghutchis
                        begin
665 60 ghutchis
                          //PC <= #1 PC - 2;
666 2 ghutchis
                          PC <= #1 PC16;
667 60 ghutchis
                        end
668
                      if (RstP == 1'b1 )
669 2 ghutchis
                        begin
670
                          TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 };
671 60 ghutchis
                          //TmpAddr <= #1 (others =>1'b0);
672
                          //TmpAddr[5:3] <= #1 IR[5:3];
673
                        end
674
                    end
675
                  if (tstate[3] && mcycle[5] )
676 2 ghutchis
                    begin
677
                      TmpAddr <= #1 SP16;
678 60 ghutchis
                    end
679 2 ghutchis
 
680 60 ghutchis
                  if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) )
681 2 ghutchis
                    begin
682 60 ghutchis
                      if (IncDec_16[2:0] == 3'b111 )
683 2 ghutchis
                        begin
684
                          SP <= #1 SP16;
685 60 ghutchis
                        end
686
                    end
687 2 ghutchis
 
688 60 ghutchis
                  if (LDSPHL == 1'b1 )
689 2 ghutchis
                    begin
690 60 ghutchis
                      SP <= #1 RegBusC;
691
                    end
692
                  if (ExchangeAF == 1'b1 )
693 2 ghutchis
                    begin
694 60 ghutchis
                      Ap <= #1 ACC;
695
                      ACC <= #1 Ap;
696
                      Fp <= #1 F;
697
                      F <= #1 Fp;
698
                    end
699
                  if (ExchangeRS == 1'b1 )
700 2 ghutchis
                    begin
701 60 ghutchis
                      Alternate <= #1 ~ Alternate;
702
                    end
703
                end // else: !if(mcycle  == 3'b001 && tstate(2) == 1'b0 )
704 2 ghutchis
 
705
 
706 60 ghutchis
              if (tstate[3] )
707 2 ghutchis
                begin
708 60 ghutchis
                  if (LDZ == 1'b1 )
709 2 ghutchis
                    begin
710 60 ghutchis
                      TmpAddr[7:0] <= #1 DI_Reg;
711
                    end
712
                  if (LDW == 1'b1 )
713 2 ghutchis
                    begin
714 60 ghutchis
                      TmpAddr[15:8] <= #1 DI_Reg;
715
                    end
716 2 ghutchis
 
717 60 ghutchis
                  if (Special_LD[2] == 1'b1 )
718 2 ghutchis
                    begin
719 60 ghutchis
                      case (Special_LD[1:0])
720
                        2'b00 :
721 2 ghutchis
                          begin
722 60 ghutchis
                            ACC <= #1 I;
723
                            F[Flag_P] <= #1 IntE_FF2;
724 2 ghutchis
                          end
725
 
726 60 ghutchis
                        2'b01 :
727 2 ghutchis
                          begin
728 87 ghutchis
                            `ifdef TV80_REFRESH
729 60 ghutchis
                            ACC <= #1 R;
730 87 ghutchis
                            `else
731
                            ACC <= #1 0;
732
                            `endif
733 60 ghutchis
                            F[Flag_P] <= #1 IntE_FF2;
734 2 ghutchis
                          end
735
 
736 60 ghutchis
                        2'b10 :
737
                          I <= #1 ACC;
738
 
739
                        `ifdef TV80_REFRESH
740
                        default :
741
                          R <= #1 ACC;
742
                        `else
743
                        default : ;
744
                        `endif
745
                      endcase
746
                    end
747
                end // if (tstate == 3 )
748 2 ghutchis
 
749
 
750 60 ghutchis
              if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
751 2 ghutchis
                begin
752 60 ghutchis
                  if (Mode == 3 )
753 2 ghutchis
                    begin
754 60 ghutchis
                      F[6] <= #1 F_Out[6];
755
                      F[5] <= #1 F_Out[5];
756
                      F[7] <= #1 F_Out[7];
757
                      if (PreserveC_r == 1'b0 )
758 2 ghutchis
                        begin
759 60 ghutchis
                          F[4] <= #1 F_Out[4];
760
                        end
761
                    end
762 2 ghutchis
                  else
763
                    begin
764 60 ghutchis
                      F[7:1] <= #1 F_Out[7:1];
765
                      if (PreserveC_r == 1'b0 )
766 2 ghutchis
                        begin
767 60 ghutchis
                          F[Flag_C] <= #1 F_Out[0];
768
                        end
769
                    end
770
                end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
771 2 ghutchis
 
772 60 ghutchis
              if (T_Res == 1'b1 && I_INRC == 1'b1 )
773 2 ghutchis
                begin
774 60 ghutchis
                  F[Flag_H] <= #1 1'b0;
775
                  F[Flag_N] <= #1 1'b0;
776
                  if (DI_Reg[7:0] == 8'b00000000 )
777 2 ghutchis
                    begin
778 60 ghutchis
                      F[Flag_Z] <= #1 1'b1;
779
                    end
780 2 ghutchis
                  else
781
                    begin
782 60 ghutchis
                      F[Flag_Z] <= #1 1'b0;
783
                    end
784
                  F[Flag_S] <= #1 DI_Reg[7];
785
                  F[Flag_P] <= #1 ~ (^DI_Reg[7:0]);
786
                end // if (T_Res == 1'b1 && I_INRC == 1'b1 )
787 2 ghutchis
 
788
 
789 60 ghutchis
              if (tstate[1] && Auto_Wait_t1 == 1'b0 )
790 2 ghutchis
                begin
791 60 ghutchis
                  do <= #1 BusB;
792
                  if (I_RLD == 1'b1 )
793 2 ghutchis
                    begin
794 60 ghutchis
                      do[3:0] <= #1 BusA[3:0];
795
                      do[7:4] <= #1 BusB[3:0];
796
                    end
797
                  if (I_RRD == 1'b1 )
798 2 ghutchis
                    begin
799 60 ghutchis
                      do[3:0] <= #1 BusB[7:4];
800
                      do[7:4] <= #1 BusA[3:0];
801
                    end
802
                end
803 2 ghutchis
 
804 60 ghutchis
              if (T_Res == 1'b1 )
805 2 ghutchis
                begin
806 60 ghutchis
                  Read_To_Reg_r[3:0] <= #1 Set_BusA_To;
807
                  Read_To_Reg_r[4] <= #1 Read_To_Reg;
808
                  if (Read_To_Acc == 1'b1 )
809 2 ghutchis
                    begin
810 60 ghutchis
                      Read_To_Reg_r[3:0] <= #1 4'b0111;
811
                      Read_To_Reg_r[4] <= #1 1'b1;
812
                    end
813
                end
814 2 ghutchis
 
815 60 ghutchis
              if (tstate[1] && I_BT == 1'b1 )
816 2 ghutchis
                begin
817 60 ghutchis
                  F[Flag_X] <= #1 ALU_Q[3];
818
                  F[Flag_Y] <= #1 ALU_Q[1];
819
                  F[Flag_H] <= #1 1'b0;
820
                  F[Flag_N] <= #1 1'b0;
821
                end
822
              if (I_BC == 1'b1 || I_BT == 1'b1 )
823 2 ghutchis
                begin
824 60 ghutchis
                  F[Flag_P] <= #1 IncDecZ;
825
                end
826 2 ghutchis
 
827 60 ghutchis
              if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
828
                  (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) )
829 2 ghutchis
                begin
830 60 ghutchis
                  case (Read_To_Reg_r)
831
                    5'b10111 :
832
                      ACC <= #1 Save_Mux;
833
                    5'b10110 :
834
                      do <= #1 Save_Mux;
835
                    5'b11000 :
836
                      SP[7:0] <= #1 Save_Mux;
837
                    5'b11001 :
838
                      SP[15:8] <= #1 Save_Mux;
839
                    5'b11011 :
840
                      F <= #1 Save_Mux;
841
                  endcase
842
                end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...              
843
            end // if (ClkEn == 1'b1 )         
844
        end // else: !if(reset_n == 1'b0 )
845 2 ghutchis
    end
846
 
847
 
848
  //-------------------------------------------------------------------------
849
  //
850
  // BC('), DE('), HL('), IX && IY
851
  //
852
  //-------------------------------------------------------------------------
853
  always @ (posedge clk)
854
    begin
855
      if (ClkEn == 1'b1 )
856
        begin
857 60 ghutchis
          // Bus A / Write
858
          RegAddrA_r <= #1  { Alternate, Set_BusA_To[2:1] };
859
          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 )
860 2 ghutchis
            begin
861 60 ghutchis
              RegAddrA_r <= #1 { XY_State[1],  2'b11 };
862
            end
863 2 ghutchis
 
864 60 ghutchis
          // Bus B
865
          RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] };
866
          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 )
867 2 ghutchis
            begin
868 60 ghutchis
              RegAddrB_r <= #1 { XY_State[1],  2'b11 };
869
            end
870 2 ghutchis
 
871 60 ghutchis
          // Address from register
872
          RegAddrC <= #1 { Alternate,  Set_Addr_To[1:0] };
873
          // Jump (HL), LD SP,HL
874
          if ((JumpXY == 1'b1 || LDSPHL == 1'b1) )
875 2 ghutchis
            begin
876 60 ghutchis
              RegAddrC <= #1 { Alternate, 2'b10 };
877
            end
878
          if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) )
879 2 ghutchis
            begin
880 60 ghutchis
              RegAddrC <= #1 { XY_State[1],  2'b11 };
881
            end
882 2 ghutchis
 
883 60 ghutchis
          if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 )
884 2 ghutchis
            begin
885 60 ghutchis
              IncDecZ <= #1 F_Out[Flag_Z];
886
            end
887
          if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 )
888 2 ghutchis
            begin
889 60 ghutchis
              if (ID16 == 0 )
890 2 ghutchis
                begin
891 60 ghutchis
                  IncDecZ <= #1 1'b0;
892
                end
893 2 ghutchis
              else
894
                begin
895 60 ghutchis
                  IncDecZ <= #1 1'b1;
896
                end
897
            end
898 2 ghutchis
 
899 60 ghutchis
          RegBusA_r <= #1 RegBusA;
900
        end
901 2 ghutchis
 
902
    end // always @ (posedge clk)
903
 
904
 
905
  always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16
906 21 ghutchis
           or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate)
907 2 ghutchis
    begin
908 21 ghutchis
      if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00)
909 2 ghutchis
        RegAddrA = { Alternate, IncDec_16[1:0] };
910 21 ghutchis
      else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10)
911 2 ghutchis
        RegAddrA = { XY_State[1], 2'b11 };
912 21 ghutchis
      else if (ExchangeDH == 1'b1 && tstate[3])
913 2 ghutchis
        RegAddrA = { Alternate, 2'b10 };
914 21 ghutchis
      else if (ExchangeDH == 1'b1 && tstate[4])
915 60 ghutchis
        RegAddrA = { Alternate, 2'b01 };
916 2 ghutchis
      else
917
        RegAddrA = RegAddrA_r;
918
 
919 21 ghutchis
      if (ExchangeDH == 1'b1 && tstate[3])
920 2 ghutchis
        RegAddrB = { Alternate, 2'b01 };
921
      else
922
        RegAddrB = RegAddrB_r;
923
    end // always @ *
924
 
925
 
926
  always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH
927 21 ghutchis
           or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
928
           or tstate or wait_n)
929 2 ghutchis
    begin
930
      RegWEH = 1'b0;
931
      RegWEL = 1'b0;
932 21 ghutchis
      if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
933 60 ghutchis
          (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) )
934 2 ghutchis
        begin
935 60 ghutchis
          case (Read_To_Reg_r)
936
            5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
937 2 ghutchis
              begin
938 60 ghutchis
                RegWEH = ~ Read_To_Reg_r[0];
939
                RegWEL = Read_To_Reg_r[0];
940 2 ghutchis
              end
941
          endcase // case(Read_To_Reg_r)
942
 
943 60 ghutchis
        end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
944 2 ghutchis
 
945
 
946 21 ghutchis
      if (ExchangeDH == 1'b1 && (tstate[3] || tstate[4]) )
947 2 ghutchis
        begin
948 60 ghutchis
          RegWEH = 1'b1;
949
          RegWEL = 1'b1;
950
        end
951 2 ghutchis
 
952 21 ghutchis
      if (IncDec_16[2] == 1'b1 && ((tstate[2] && wait_n == 1'b1 && mcycle != 3'b001) || (tstate[3] && mcycle[0])) )
953 2 ghutchis
        begin
954 60 ghutchis
          case (IncDec_16[1:0])
955
            2'b00 , 2'b01 , 2'b10 :
956 2 ghutchis
              begin
957 60 ghutchis
                RegWEH = 1'b1;
958
                RegWEL = 1'b1;
959 2 ghutchis
              end
960 60 ghutchis
          endcase
961
        end
962 2 ghutchis
    end // always @ *
963
 
964
 
965
  always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r
966 21 ghutchis
           or RegBusB or Save_Mux or mcycle or tstate)
967 2 ghutchis
    begin
968
      RegDIH = Save_Mux;
969
      RegDIL = Save_Mux;
970
 
971 21 ghutchis
      if (ExchangeDH == 1'b1 && tstate[3] )
972 2 ghutchis
        begin
973 60 ghutchis
          RegDIH = RegBusB[15:8];
974
          RegDIL = RegBusB[7:0];
975
        end
976 21 ghutchis
      else if (ExchangeDH == 1'b1 && tstate[4] )
977 2 ghutchis
        begin
978 60 ghutchis
          RegDIH = RegBusA_r[15:8];
979
          RegDIL = RegBusA_r[7:0];
980
        end
981 21 ghutchis
      else if (IncDec_16[2] == 1'b1 && ((tstate[2] && mcycle != 3'b001) || (tstate[3] && mcycle[0])) )
982 2 ghutchis
        begin
983 60 ghutchis
          RegDIH = ID16[15:8];
984
          RegDIL = ID16[7:0];
985
        end
986 2 ghutchis
    end
987
 
988
  tv80_reg i_reg
989
    (
990
     .clk                  (clk),
991
     .CEN                  (ClkEn),
992
     .WEH                  (RegWEH),
993
     .WEL                  (RegWEL),
994
     .AddrA                (RegAddrA),
995
     .AddrB                (RegAddrB),
996
     .AddrC                (RegAddrC),
997
     .DIH                  (RegDIH),
998
     .DIL                  (RegDIL),
999
     .DOAH                 (RegBusA[15:8]),
1000
     .DOAL                 (RegBusA[7:0]),
1001
     .DOBH                 (RegBusB[15:8]),
1002
     .DOBL                 (RegBusB[7:0]),
1003
     .DOCH                 (RegBusC[15:8]),
1004
     .DOCL                 (RegBusC[7:0])
1005
     );
1006
 
1007
  //-------------------------------------------------------------------------
1008
  //
1009
  // Buses
1010
  //
1011
  //-------------------------------------------------------------------------
1012
 
1013
  always @ (posedge clk)
1014
    begin
1015
      if (ClkEn == 1'b1 )
1016
        begin
1017 60 ghutchis
          case (Set_BusB_To)
1018
            4'b0111 :
1019
              BusB <= #1 ACC;
1020
            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
1021 2 ghutchis
              begin
1022 60 ghutchis
                if (Set_BusB_To[0] == 1'b1 )
1023 2 ghutchis
                  begin
1024 60 ghutchis
                    BusB <= #1 RegBusB[7:0];
1025
                  end
1026 2 ghutchis
                else
1027
                  begin
1028 60 ghutchis
                    BusB <= #1 RegBusB[15:8];
1029
                  end
1030 2 ghutchis
              end
1031 60 ghutchis
            4'b0110 :
1032
              BusB <= #1 DI_Reg;
1033
            4'b1000 :
1034
              BusB <= #1 SP[7:0];
1035
            4'b1001 :
1036
              BusB <= #1 SP[15:8];
1037
            4'b1010 :
1038
              BusB <= #1 8'b00000001;
1039
            4'b1011 :
1040
              BusB <= #1 F;
1041
            4'b1100 :
1042
              BusB <= #1 PC[7:0];
1043
            4'b1101 :
1044
              BusB <= #1 PC[15:8];
1045
            4'b1110 :
1046
              BusB <= #1 8'b00000000;
1047
            default :
1048 87 ghutchis
              BusB <= #1 8'h0;
1049 60 ghutchis
          endcase
1050 2 ghutchis
 
1051 60 ghutchis
          case (Set_BusA_To)
1052
            4'b0111 :
1053
              BusA <= #1 ACC;
1054
            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
1055 2 ghutchis
              begin
1056 60 ghutchis
                if (Set_BusA_To[0] == 1'b1 )
1057 2 ghutchis
                  begin
1058 60 ghutchis
                    BusA <= #1 RegBusA[7:0];
1059
                  end
1060 2 ghutchis
                else
1061
                  begin
1062 60 ghutchis
                    BusA <= #1 RegBusA[15:8];
1063
                  end
1064 2 ghutchis
              end
1065 60 ghutchis
            4'b0110 :
1066
              BusA <= #1 DI_Reg;
1067
            4'b1000 :
1068
              BusA <= #1 SP[7:0];
1069
            4'b1001 :
1070
              BusA <= #1 SP[15:8];
1071
            4'b1010 :
1072
              BusA <= #1 8'b00000000;
1073
            default :
1074 87 ghutchis
              BusA <= #1  8'h0;
1075 60 ghutchis
          endcase
1076
        end
1077 2 ghutchis
    end
1078
 
1079
  //-------------------------------------------------------------------------
1080
  //
1081
  // Generate external control signals
1082
  //
1083
  //-------------------------------------------------------------------------
1084 60 ghutchis
`ifdef TV80_REFRESH
1085 2 ghutchis
  always @ (posedge clk)
1086
    begin
1087
      if (reset_n == 1'b0 )
1088
        begin
1089 60 ghutchis
          rfsh_n <= #1 1'b1;
1090
        end
1091 2 ghutchis
      else
1092
        begin
1093 60 ghutchis
          if (cen == 1'b1 )
1094 2 ghutchis
            begin
1095 60 ghutchis
              if (mcycle[0] && ((tstate[2]  && wait_n == 1'b1) || tstate[3]) )
1096 2 ghutchis
                begin
1097 60 ghutchis
                  rfsh_n <= #1 1'b0;
1098
                end
1099 2 ghutchis
              else
1100
                begin
1101 60 ghutchis
                  rfsh_n <= #1 1'b1;
1102
                end
1103
            end
1104
        end
1105 87 ghutchis
    end // always @ (posedge clk or negedge reset_n)
1106
`else // !`ifdef TV80_REFRESH
1107
  assign rfsh_n = 1'b1;
1108 60 ghutchis
`endif
1109 2 ghutchis
 
1110
  always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle
1111 21 ghutchis
           or IntE_FF1 or di or iorq_i or mcycle or tstate)
1112 2 ghutchis
    begin
1113
      mc = mcycle;
1114
      ts = tstate;
1115
      DI_Reg = di;
1116
      halt_n = ~ Halt_FF;
1117
      busak_n = ~ BusAck;
1118
      intcycle_n = ~ IntCycle;
1119
      IntE = IntE_FF1;
1120
      iorq = iorq_i;
1121
      stop = I_DJNZ;
1122
    end
1123
 
1124
  //-----------------------------------------------------------------------
1125
  //
1126
  // Syncronise inputs
1127
  //
1128
  //-----------------------------------------------------------------------
1129
 
1130
  always @ (posedge clk)
1131
    begin : sync_inputs
1132
 
1133
      if (reset_n == 1'b0 )
1134
        begin
1135 60 ghutchis
          BusReq_s <= #1 1'b0;
1136
          INT_s <= #1 1'b0;
1137
          NMI_s <= #1 1'b0;
1138
          Oldnmi_n <= #1 1'b0;
1139
        end
1140 2 ghutchis
      else
1141
        begin
1142 60 ghutchis
          if (cen == 1'b1 )
1143 2 ghutchis
            begin
1144 60 ghutchis
              BusReq_s <= #1 ~ busrq_n;
1145
              INT_s <= #1 ~ int_n;
1146
              if (NMICycle == 1'b1 )
1147 2 ghutchis
                begin
1148 60 ghutchis
                  NMI_s <= #1 1'b0;
1149
                end
1150 2 ghutchis
              else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 )
1151
                begin
1152 60 ghutchis
                  NMI_s <= #1 1'b1;
1153
                end
1154
              Oldnmi_n <= #1 nmi_n;
1155
            end
1156
        end
1157 2 ghutchis
    end
1158
 
1159
  //-----------------------------------------------------------------------
1160
  //
1161
  // Main state machine
1162
  //
1163
  //-----------------------------------------------------------------------
1164
 
1165
  always @ (posedge clk)
1166
    begin
1167
      if (reset_n == 1'b0 )
1168
        begin
1169 60 ghutchis
          mcycle <= #1 7'b0000001;
1170
          tstate <= #1 7'b0000001;
1171
          Pre_XY_F_M <= #1 3'b000;
1172
          Halt_FF <= #1 1'b0;
1173
          BusAck <= #1 1'b0;
1174
          NMICycle <= #1 1'b0;
1175
          IntCycle <= #1 1'b0;
1176
          IntE_FF1 <= #1 1'b0;
1177
          IntE_FF2 <= #1 1'b0;
1178
          No_BTR <= #1 1'b0;
1179
          Auto_Wait_t1 <= #1 1'b0;
1180
          Auto_Wait_t2 <= #1 1'b0;
1181
          m1_n <= #1 1'b1;
1182
        end
1183 2 ghutchis
      else
1184
        begin
1185 60 ghutchis
          if (cen == 1'b1 )
1186 2 ghutchis
            begin
1187 60 ghutchis
              if (T_Res == 1'b1 )
1188 2 ghutchis
                begin
1189 60 ghutchis
                  Auto_Wait_t1 <= #1 1'b0;
1190
                end
1191 2 ghutchis
              else
1192
                begin
1193 60 ghutchis
                  Auto_Wait_t1 <= #1 Auto_Wait || iorq_i;
1194
                end
1195
              Auto_Wait_t2 <= #1 Auto_Wait_t1;
1196
              No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) ||
1197
                        (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) ||
1198
                        (I_BTR && (~ IR[4] || F[Flag_Z]));
1199
              if (tstate[2] )
1200 2 ghutchis
                begin
1201 60 ghutchis
                  if (SetEI == 1'b1 )
1202 2 ghutchis
                    begin
1203 60 ghutchis
                      IntE_FF1 <= #1 1'b1;
1204
                      IntE_FF2 <= #1 1'b1;
1205
                    end
1206
                  if (I_RETN == 1'b1 )
1207 2 ghutchis
                    begin
1208 60 ghutchis
                      IntE_FF1 <= #1 IntE_FF2;
1209
                    end
1210
                end
1211
              if (tstate[3] )
1212 2 ghutchis
                begin
1213 60 ghutchis
                  if (SetDI == 1'b1 )
1214 2 ghutchis
                    begin
1215 60 ghutchis
                      IntE_FF1 <= #1 1'b0;
1216
                      IntE_FF2 <= #1 1'b0;
1217
                    end
1218
                end
1219
              if (IntCycle == 1'b1 || NMICycle == 1'b1 )
1220 2 ghutchis
                begin
1221 60 ghutchis
                  Halt_FF <= #1 1'b0;
1222
                end
1223
              if (mcycle[0] && tstate[2] && wait_n == 1'b1 )
1224 2 ghutchis
                begin
1225 60 ghutchis
                  m1_n <= #1 1'b1;
1226
                end
1227
              if (BusReq_s == 1'b1 && BusAck == 1'b1 )
1228 2 ghutchis
                begin
1229
                end
1230
              else
1231
                begin
1232 60 ghutchis
                  BusAck <= #1 1'b0;
1233
                  if (tstate[2] && wait_n == 1'b0 )
1234 2 ghutchis
                    begin
1235 60 ghutchis
                    end
1236 2 ghutchis
                  else if (T_Res == 1'b1 )
1237
                    begin
1238 60 ghutchis
                      if (Halt == 1'b1 )
1239 2 ghutchis
                        begin
1240 60 ghutchis
                          Halt_FF <= #1 1'b1;
1241
                        end
1242
                      if (BusReq_s == 1'b1 )
1243 2 ghutchis
                        begin
1244 60 ghutchis
                          BusAck <= #1 1'b1;
1245
                        end
1246 2 ghutchis
                      else
1247
                        begin
1248 60 ghutchis
                          tstate <= #1 7'b0000010;
1249
                          if (NextIs_XY_Fetch == 1'b1 )
1250 2 ghutchis
                            begin
1251 60 ghutchis
                              mcycle <= #1 7'b0100000;
1252
                              Pre_XY_F_M <= #1 mcycle;
1253
                              if (IR == 8'b00110110 && Mode == 0 )
1254 2 ghutchis
                                begin
1255 60 ghutchis
                                  Pre_XY_F_M <= #1 3'b010;
1256
                                end
1257
                            end
1258 21 ghutchis
                          else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) )
1259 2 ghutchis
                            begin
1260 60 ghutchis
                              mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1);
1261
                            end
1262 21 ghutchis
                          else if ((last_mcycle) ||
1263 60 ghutchis
                                   No_BTR == 1'b1 ||
1264
                                   (mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) )
1265 2 ghutchis
                            begin
1266 60 ghutchis
                              m1_n <= #1 1'b0;
1267
                              mcycle <= #1 7'b0000001;
1268
                              IntCycle <= #1 1'b0;
1269
                              NMICycle <= #1 1'b0;
1270
                              if (NMI_s == 1'b1 && Prefix == 2'b00 )
1271 2 ghutchis
                                begin
1272 60 ghutchis
                                  NMICycle <= #1 1'b1;
1273
                                  IntE_FF1 <= #1 1'b0;
1274
                                end
1275 2 ghutchis
                              else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 )
1276
                                begin
1277 60 ghutchis
                                  IntCycle <= #1 1'b1;
1278
                                  IntE_FF1 <= #1 1'b0;
1279
                                  IntE_FF2 <= #1 1'b0;
1280
                                end
1281
                            end
1282 2 ghutchis
                          else
1283
                            begin
1284 60 ghutchis
                              mcycle <= #1 { mcycle[5:0], mcycle[6] };
1285
                            end
1286
                        end
1287
                    end
1288 2 ghutchis
                  else
1289
                    begin   // verilog has no "nor" operator
1290 60 ghutchis
                      if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) &&
1291
                           ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) )
1292 2 ghutchis
                        begin
1293 60 ghutchis
                          tstate <= #1 { tstate[5:0], tstate[6] };
1294
                        end
1295
                    end
1296
                end
1297
              if (tstate[0])
1298 2 ghutchis
                begin
1299 60 ghutchis
                  m1_n <= #1 1'b0;
1300
                end
1301
            end
1302
        end
1303 2 ghutchis
    end
1304
 
1305
  always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
1306 21 ghutchis
           or RegBusA or RegBusC or SP or tstate)
1307 2 ghutchis
    begin
1308
      if (JumpE == 1'b1 )
1309
        begin
1310
          PC16_B = { {8{DI_Reg[7]}}, DI_Reg };
1311 60 ghutchis
        end
1312 2 ghutchis
      else if (BTR_r == 1'b1 )
1313
        begin
1314
          PC16_B = -2;
1315 60 ghutchis
        end
1316 2 ghutchis
      else
1317
        begin
1318
          PC16_B = 1;
1319 60 ghutchis
        end
1320 2 ghutchis
 
1321 21 ghutchis
      if (tstate[3])
1322 2 ghutchis
        begin
1323
          SP16_A = RegBusC;
1324
          SP16_B = { {8{DI_Reg[7]}}, DI_Reg };
1325
        end
1326
      else
1327
        begin
1328
          // suspect that ID16 and SP16 could be shared
1329
          SP16_A = SP;
1330
 
1331
          if (IncDec_16[3] == 1'b1)
1332
            SP16_B = -1;
1333
          else
1334
            SP16_B = 1;
1335
        end
1336
 
1337
      if (IncDec_16[3])
1338
        ID16_B = -1;
1339
      else
1340
        ID16_B = 1;
1341
 
1342
      ID16 = RegBusA + ID16_B;
1343
      PC16 = PC + PC16_B;
1344
      SP16 = SP16_A + SP16_B;
1345
    end // always @ *
1346
 
1347
 
1348
  always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle)
1349
    begin
1350
      Auto_Wait = 1'b0;
1351
      if (IntCycle == 1'b1 || NMICycle == 1'b1 )
1352
        begin
1353 60 ghutchis
          if (mcycle[0] )
1354 2 ghutchis
            begin
1355 60 ghutchis
              Auto_Wait = 1'b1;
1356
            end
1357
        end
1358 2 ghutchis
    end // always @ *
1359
 
1360
// synopsys dc_script_begin
1361 60 ghutchis
// set_attribute current_design "revision" "$Id: tv80_core.v,v 1.5 2005-01-26 18:55:47 ghutchis Exp $" -type string -quiet
1362 2 ghutchis
// synopsys dc_script_end
1363
endmodule // T80
1364
 

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