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[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_mcode.v] - Blame information for rev 90

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1 2 ghutchis
//
2
// TV80 8-Bit Microprocessor Core
3
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
4
//
5 83 hharte
// Copyright (c) 2004,2007 Guy Hutchison (ghutchis@opencores.org)
6 2 ghutchis
//
7
// Permission is hereby granted, free of charge, to any person obtaining a 
8
// copy of this software and associated documentation files (the "Software"), 
9
// to deal in the Software without restriction, including without limitation 
10
// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
11
// and/or sell copies of the Software, and to permit persons to whom the 
12
// Software is furnished to do so, subject to the following conditions:
13
//
14
// The above copyright notice and this permission notice shall be included 
15
// in all copies or substantial portions of the Software.
16
//
17
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
18
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
19
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
20
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
21
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
22
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
23
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24
 
25 24 ghutchis
module tv80_mcode
26
  (/*AUTOARG*/
27 80 ghutchis
  // Outputs
28
  MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,
29
  Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,
30
  Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,
31
  LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,
32
  ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR,
33
  I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write,
34
  // Inputs
35
  IR, ISet, MCycle, F, NMICycle, IntCycle
36
  );
37 2 ghutchis
 
38 24 ghutchis
  parameter             Mode   = 0;
39
  parameter             Flag_C = 0;
40
  parameter             Flag_N = 1;
41
  parameter             Flag_P = 2;
42
  parameter             Flag_X = 3;
43
  parameter             Flag_H = 4;
44
  parameter             Flag_Y = 5;
45
  parameter             Flag_Z = 6;
46
  parameter             Flag_S = 7;
47 2 ghutchis
 
48
  input [7:0]           IR;
49 24 ghutchis
  input [1:0]           ISet                    ;
50
  input [6:0]           MCycle                  ;
51
  input [7:0]           F                       ;
52
  input                 NMICycle                ;
53
  input                 IntCycle                ;
54
  output [2:0]          MCycles                 ;
55
  output [2:0]          TStates                 ;
56
  output [1:0]          Prefix                  ; // None,BC,ED,DD/FD
57
  output                Inc_PC                  ;
58
  output                Inc_WZ                  ;
59
  output [3:0]          IncDec_16               ; // BC,DE,HL,SP   0 is inc
60
  output                Read_To_Reg             ;
61
  output                Read_To_Acc             ;
62
  output [3:0]          Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
63
  output [3:0]          Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
64
  output [3:0]          ALU_Op                  ;
65
  output                Save_ALU                ;
66
  output                PreserveC               ;
67
  output                Arith16                 ;
68
  output [2:0]          Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
69
  output                IORQ                    ;
70
  output                Jump                    ;
71
  output                JumpE                   ;
72
  output                JumpXY                  ;
73
  output                Call                    ;
74
  output                RstP                    ;
75
  output                LDZ                     ;
76
  output                LDW                     ;
77
  output                LDSPHL                  ;
78
  output [2:0]          Special_LD              ; // A,I;A,R;I,A;R,A;None
79
  output                ExchangeDH              ;
80
  output                ExchangeRp              ;
81
  output                ExchangeAF              ;
82
  output                ExchangeRS              ;
83
  output                I_DJNZ                  ;
84
  output                I_CPL                   ;
85
  output                I_CCF                   ;
86
  output                I_SCF                   ;
87
  output                I_RETN                  ;
88
  output                I_BT                    ;
89
  output                I_BC                    ;
90
  output                I_BTR                   ;
91
  output                I_RLD                   ;
92
  output                I_RRD                   ;
93
  output                I_INRC                  ;
94
  output                SetDI                   ;
95
  output                SetEI                   ;
96
  output [1:0]          IMode                   ;
97
  output                Halt                    ;
98
  output                NoRead                  ;
99
  output                Write   ;
100 2 ghutchis
 
101
  // regs
102 24 ghutchis
  reg [2:0]             MCycles                 ;
103
  reg [2:0]             TStates                 ;
104
  reg [1:0]             Prefix                  ; // None,BC,ED,DD/FD
105
  reg                   Inc_PC                  ;
106
  reg                   Inc_WZ                  ;
107
  reg [3:0]             IncDec_16               ; // BC,DE,HL,SP   0 is inc
108
  reg                   Read_To_Reg             ;
109
  reg                   Read_To_Acc             ;
110
  reg [3:0]             Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
111
  reg [3:0]             Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
112
  reg [3:0]             ALU_Op                  ;
113
  reg                   Save_ALU                ;
114
  reg                   PreserveC               ;
115
  reg                   Arith16                 ;
116
  reg [2:0]             Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
117
  reg                   IORQ                    ;
118
  reg                   Jump                    ;
119
  reg                   JumpE                   ;
120
  reg                   JumpXY                  ;
121
  reg                   Call                    ;
122
  reg                   RstP                    ;
123
  reg                   LDZ                     ;
124
  reg                   LDW                     ;
125
  reg                   LDSPHL                  ;
126
  reg [2:0]             Special_LD              ; // A,I;A,R;I,A;R,A;None
127
  reg                   ExchangeDH              ;
128
  reg                   ExchangeRp              ;
129
  reg                   ExchangeAF              ;
130
  reg                   ExchangeRS              ;
131
  reg                   I_DJNZ                  ;
132
  reg                   I_CPL                   ;
133
  reg                   I_CCF                   ;
134
  reg                   I_SCF                   ;
135
  reg                   I_RETN                  ;
136
  reg                   I_BT                    ;
137
  reg                   I_BC                    ;
138
  reg                   I_BTR                   ;
139
  reg                   I_RLD                   ;
140
  reg                   I_RRD                   ;
141
  reg                   I_INRC                  ;
142
  reg                   SetDI                   ;
143
  reg                   SetEI                   ;
144
  reg [1:0]             IMode                   ;
145
  reg                   Halt                    ;
146
  reg                   NoRead                  ;
147
  reg                   Write   ;
148 2 ghutchis
 
149 24 ghutchis
  parameter             aNone   = 3'b111;
150
  parameter             aBC     = 3'b000;
151
  parameter             aDE     = 3'b001;
152
  parameter             aXY     = 3'b010;
153
  parameter             aIOA    = 3'b100;
154
  parameter             aSP     = 3'b101;
155
  parameter             aZI     = 3'b110;
156
  //    constant aNone  : std_logic_vector[2:0] = 3'b000;
157
  //    constant aXY    : std_logic_vector[2:0] = 3'b001;
158
  //    constant aIOA   : std_logic_vector[2:0] = 3'b010;
159
  //    constant aSP    : std_logic_vector[2:0] = 3'b011;
160
  //    constant aBC    : std_logic_vector[2:0] = 3'b100;
161
  //    constant aDE    : std_logic_vector[2:0] = 3'b101;
162
  //    constant aZI    : std_logic_vector[2:0] = 3'b110;
163 2 ghutchis
 
164
  function is_cc_true;
165 90 ghutchis
    input [7:0] FF;
166 2 ghutchis
    input [2:0] cc;
167
    begin
168
      if (Mode == 3 )
169
        begin
170 24 ghutchis
          case (cc)
171 90 ghutchis
            3'b000  : is_cc_true = FF[7] == 1'b0; // NZ
172
            3'b001  : is_cc_true = FF[7] == 1'b1; // Z
173
            3'b010  : is_cc_true = FF[4] == 1'b0; // NC
174
            3'b011  : is_cc_true = FF[4] == 1'b1; // C
175 24 ghutchis
            3'b100  : is_cc_true = 0;
176
            3'b101  : is_cc_true = 0;
177
            3'b110  : is_cc_true = 0;
178
            3'b111  : is_cc_true = 0;
179
          endcase
180
        end
181 2 ghutchis
      else
182
        begin
183 24 ghutchis
          case (cc)
184 90 ghutchis
            3'b000  : is_cc_true = FF[6] == 1'b0; // NZ
185
            3'b001  : is_cc_true = FF[6] == 1'b1; // Z
186
            3'b010  : is_cc_true = FF[0] == 1'b0; // NC
187
            3'b011  : is_cc_true = FF[0] == 1'b1; // C
188
            3'b100  : is_cc_true = FF[2] == 1'b0; // PO
189
            3'b101  : is_cc_true = FF[2] == 1'b1; // PE
190
            3'b110  : is_cc_true = FF[7] == 1'b0; // P
191
            3'b111  : is_cc_true = FF[7] == 1'b1; // M
192 24 ghutchis
          endcase
193
        end
194 2 ghutchis
    end
195
  endfunction // is_cc_true
196
 
197
 
198
  reg [2:0] DDD;
199
  reg [2:0] SSS;
200
  reg [1:0] DPAIR;
201
 
202
  always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle
203 24 ghutchis
            or NMICycle)
204 2 ghutchis
    begin
205
      DDD = IR[5:3];
206
      SSS = IR[2:0];
207
      DPAIR = IR[5:4];
208
 
209
      MCycles = 3'b001;
210 21 ghutchis
      if (MCycle[0] )
211 2 ghutchis
        begin
212 24 ghutchis
          TStates = 3'b100;
213
        end
214 2 ghutchis
      else
215
        begin
216 24 ghutchis
          TStates = 3'b011;
217
        end
218 2 ghutchis
      Prefix = 2'b00;
219
      Inc_PC = 1'b0;
220
      Inc_WZ = 1'b0;
221
      IncDec_16 = 4'b0000;
222
      Read_To_Acc = 1'b0;
223
      Read_To_Reg = 1'b0;
224
      Set_BusB_To = 4'b0000;
225
      Set_BusA_To = 4'b0000;
226
      ALU_Op = { 1'b0, IR[5:3] };
227
      Save_ALU = 1'b0;
228
      PreserveC = 1'b0;
229
      Arith16 = 1'b0;
230
      IORQ = 1'b0;
231
      Set_Addr_To = aNone;
232
      Jump = 1'b0;
233
      JumpE = 1'b0;
234
      JumpXY = 1'b0;
235
      Call = 1'b0;
236
      RstP = 1'b0;
237
      LDZ = 1'b0;
238
      LDW = 1'b0;
239
      LDSPHL = 1'b0;
240
      Special_LD = 3'b000;
241
      ExchangeDH = 1'b0;
242
      ExchangeRp = 1'b0;
243
      ExchangeAF = 1'b0;
244
      ExchangeRS = 1'b0;
245
      I_DJNZ = 1'b0;
246
      I_CPL = 1'b0;
247
      I_CCF = 1'b0;
248
      I_SCF = 1'b0;
249
      I_RETN = 1'b0;
250
      I_BT = 1'b0;
251
      I_BC = 1'b0;
252
      I_BTR = 1'b0;
253
      I_RLD = 1'b0;
254
      I_RRD = 1'b0;
255
      I_INRC = 1'b0;
256
      SetDI = 1'b0;
257
      SetEI = 1'b0;
258
      IMode = 2'b11;
259
      Halt = 1'b0;
260
      NoRead = 1'b0;
261
      Write = 1'b0;
262
 
263
      case (ISet)
264 24 ghutchis
        2'b00  :
265 2 ghutchis
          begin
266
 
267 24 ghutchis
            //----------------------------------------------------------------------------
268
            //
269
            //  Unprefixed instructions
270
            //
271
            //----------------------------------------------------------------------------
272 2 ghutchis
 
273 90 ghutchis
            casez (IR)
274 24 ghutchis
              // 8 BIT LOAD GROUP
275 90 ghutchis
              8'b01zzzzzz :
276 2 ghutchis
                begin
277 80 ghutchis
                  if (IR[5:0] == 6'b110110)
278 24 ghutchis
                    Halt = 1'b1;
279 80 ghutchis
                  else if (IR[2:0] == 3'b110)
280 24 ghutchis
                    begin
281
                      // LD r,(HL)
282
                      MCycles = 3'b010;
283
                      if (MCycle[0])
284
                        Set_Addr_To = aXY;
285
                      if (MCycle[1])
286
                        begin
287
                          Set_BusA_To[2:0] = DDD;
288
                          Read_To_Reg = 1'b1;
289
                        end
290 80 ghutchis
                    end // if (IR[2:0] == 3'b110)
291
                  else if (IR[5:3] == 3'b110)
292 24 ghutchis
                    begin
293
                      // LD (HL),r
294
                      MCycles = 3'b010;
295
                      if (MCycle[0])
296
                        begin
297
                          Set_Addr_To = aXY;
298
                          Set_BusB_To[2:0] = SSS;
299
                          Set_BusB_To[3] = 1'b0;
300
                        end
301
                      if (MCycle[1])
302
                        Write = 1'b1;
303 80 ghutchis
                    end // if (IR[5:3] == 3'b110)
304 24 ghutchis
                  else
305
                    begin
306
                      Set_BusB_To[2:0] = SSS;
307
                      ExchangeRp = 1'b1;
308
                      Set_BusA_To[2:0] = DDD;
309
                      Read_To_Reg = 1'b1;
310 80 ghutchis
                    end // else: !if(IR[5:3] == 3'b110)
311 90 ghutchis
                end // case: 8'b01zzzzzz                                    
312 24 ghutchis
 
313 90 ghutchis
              8'b00zzz110 :
314 2 ghutchis
                begin
315 80 ghutchis
                  if (IR[5:3] == 3'b110)
316 23 ghutchis
                    begin
317 24 ghutchis
                      // LD (HL),n
318
                      MCycles = 3'b011;
319
                      if (MCycle[1])
320
                        begin
321
                          Inc_PC = 1'b1;
322
                          Set_Addr_To = aXY;
323
                          Set_BusB_To[2:0] = SSS;
324
                          Set_BusB_To[3] = 1'b0;
325
                        end
326
                      if (MCycle[2])
327
                        Write = 1'b1;
328 80 ghutchis
                    end // if (IR[5:3] == 3'b110)
329 24 ghutchis
                  else
330
                    begin
331
                      // LD r,n
332
                      MCycles = 3'b010;
333
                      if (MCycle[1])
334
                        begin
335
                          Inc_PC = 1'b1;
336
                          Set_BusA_To[2:0] = DDD;
337
                          Read_To_Reg = 1'b1;
338
                        end
339 23 ghutchis
                    end
340 24 ghutchis
                end
341 2 ghutchis
 
342 24 ghutchis
              8'b00001010  :
343 2 ghutchis
                begin
344 24 ghutchis
                  // LD A,(BC)
345
                  MCycles = 3'b010;
346 23 ghutchis
                  if (MCycle[0])
347 24 ghutchis
                    Set_Addr_To = aBC;
348
                  if (MCycle[1])
349
                    Read_To_Acc = 1'b1;
350 2 ghutchis
                end // case: 8'b00001010
351
 
352 24 ghutchis
              8'b00011010  :
353 2 ghutchis
                begin
354 24 ghutchis
                  // LD A,(DE)
355
                  MCycles = 3'b010;
356 23 ghutchis
                  if (MCycle[0])
357 24 ghutchis
                    Set_Addr_To = aDE;
358 23 ghutchis
                  if (MCycle[1])
359 24 ghutchis
                    Read_To_Acc = 1'b1;
360 2 ghutchis
                end // case: 8'b00011010
361
 
362 24 ghutchis
              8'b00111010  :
363 2 ghutchis
                begin
364 24 ghutchis
                  if (Mode == 3 )
365 2 ghutchis
                    begin
366 24 ghutchis
                      // LDD A,(HL)
367
                      MCycles = 3'b010;
368 23 ghutchis
                      if (MCycle[0])
369 24 ghutchis
                        Set_Addr_To = aXY;
370 23 ghutchis
                      if (MCycle[1])
371
                        begin
372 24 ghutchis
                          Read_To_Acc = 1'b1;
373
                          IncDec_16 = 4'b1110;
374 23 ghutchis
                        end
375 24 ghutchis
                    end
376 2 ghutchis
                  else
377
                    begin
378 24 ghutchis
                      // LD A,(nn)
379
                      MCycles = 3'b100;
380 23 ghutchis
                      if (MCycle[1])
381
                        begin
382 24 ghutchis
                          Inc_PC = 1'b1;
383
                          LDZ = 1'b1;
384 23 ghutchis
                        end
385
                      if (MCycle[2])
386
                        begin
387 24 ghutchis
                          Set_Addr_To = aZI;
388
                          Inc_PC = 1'b1;
389 23 ghutchis
                        end
390
                      if (MCycle[3])
391
                        begin
392 24 ghutchis
                          Read_To_Acc = 1'b1;
393 23 ghutchis
                        end
394 24 ghutchis
                    end // else: !if(Mode == 3 )
395 2 ghutchis
                end // case: 8'b00111010
396
 
397 24 ghutchis
              8'b00000010  :
398 2 ghutchis
                begin
399 24 ghutchis
                  // LD (BC),A
400
                  MCycles = 3'b010;
401 23 ghutchis
                  if (MCycle[0])
402
                    begin
403 24 ghutchis
                      Set_Addr_To = aBC;
404
                      Set_BusB_To = 4'b0111;
405 23 ghutchis
                    end
406
                  if (MCycle[1])
407
                    begin
408 24 ghutchis
                      Write = 1'b1;
409 23 ghutchis
                    end
410 2 ghutchis
                end // case: 8'b00000010
411
 
412 24 ghutchis
              8'b00010010  :
413 2 ghutchis
                begin
414 24 ghutchis
                  // LD (DE),A
415
                  MCycles = 3'b010;
416
                  case (1'b1) // MCycle
417
                    MCycle[0] :
418 2 ghutchis
                      begin
419 24 ghutchis
                        Set_Addr_To = aDE;
420
                        Set_BusB_To = 4'b0111;
421 2 ghutchis
                      end
422 24 ghutchis
                    MCycle[1] :
423
                      Write = 1'b1;
424
                    default :;
425
                  endcase // case(MCycle)
426 2 ghutchis
                end // case: 8'b00010010
427
 
428 24 ghutchis
              8'b00110010  :
429 2 ghutchis
                begin
430 24 ghutchis
                  if (Mode == 3 )
431 2 ghutchis
                    begin
432 24 ghutchis
                      // LDD (HL),A
433
                      MCycles = 3'b010;
434
                      case (1'b1) // MCycle
435
                        MCycle[0] :
436 2 ghutchis
                          begin
437 24 ghutchis
                            Set_Addr_To = aXY;
438
                            Set_BusB_To = 4'b0111;
439 2 ghutchis
                          end
440 24 ghutchis
                        MCycle[1] :
441 2 ghutchis
                          begin
442 24 ghutchis
                            Write = 1'b1;
443
                            IncDec_16 = 4'b1110;
444 2 ghutchis
                          end
445 24 ghutchis
                        default :;
446
                      endcase // case(MCycle)
447 2 ghutchis
 
448 24 ghutchis
                    end
449 2 ghutchis
                  else
450
                    begin
451 24 ghutchis
                      // LD (nn),A
452
                      MCycles = 3'b100;
453
                      case (1'b1) // MCycle
454
                        MCycle[1] :
455 2 ghutchis
                          begin
456 24 ghutchis
                            Inc_PC = 1'b1;
457
                            LDZ = 1'b1;
458 2 ghutchis
                          end
459 24 ghutchis
                        MCycle[2] :
460 2 ghutchis
                          begin
461 24 ghutchis
                            Set_Addr_To = aZI;
462
                            Inc_PC = 1'b1;
463
                            Set_BusB_To = 4'b0111;
464 2 ghutchis
                          end
465 24 ghutchis
                        MCycle[3] :
466 2 ghutchis
                          begin
467 24 ghutchis
                            Write = 1'b1;
468 2 ghutchis
                          end
469 24 ghutchis
                        default :;
470
                      endcase
471
                    end // else: !if(Mode == 3 )
472 2 ghutchis
                end // case: 8'b00110010
473
 
474
 
475 24 ghutchis
              // 16 BIT LOAD GROUP
476
              8'b00000001,8'b00010001,8'b00100001,8'b00110001  :
477 2 ghutchis
                begin
478 24 ghutchis
                  // LD dd,nn
479
                  MCycles = 3'b011;
480
                  case (1'b1) // MCycle
481
                    MCycle[1] :
482 2 ghutchis
                      begin
483 24 ghutchis
                        Inc_PC = 1'b1;
484
                        Read_To_Reg = 1'b1;
485
                        if (DPAIR == 2'b11 )
486 2 ghutchis
                          begin
487 24 ghutchis
                            Set_BusA_To[3:0] = 4'b1000;
488
                          end
489 2 ghutchis
                        else
490
                          begin
491 24 ghutchis
                            Set_BusA_To[2:1] = DPAIR;
492
                            Set_BusA_To[0] = 1'b1;
493
                          end
494 2 ghutchis
                      end // case: 2
495
 
496 24 ghutchis
                    MCycle[2] :
497 2 ghutchis
                      begin
498 24 ghutchis
                        Inc_PC = 1'b1;
499
                        Read_To_Reg = 1'b1;
500
                        if (DPAIR == 2'b11 )
501 2 ghutchis
                          begin
502 24 ghutchis
                            Set_BusA_To[3:0] = 4'b1001;
503
                          end
504 2 ghutchis
                        else
505
                          begin
506 24 ghutchis
                            Set_BusA_To[2:1] = DPAIR;
507
                            Set_BusA_To[0] = 1'b0;
508
                          end
509 2 ghutchis
                      end // case: 3
510
 
511 24 ghutchis
                    default :;
512
                  endcase // case(MCycle)
513 2 ghutchis
                end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001
514
 
515 24 ghutchis
              8'b00101010  :
516 2 ghutchis
                begin
517 24 ghutchis
                  if (Mode == 3 )
518 2 ghutchis
                    begin
519 24 ghutchis
                      // LDI A,(HL)
520
                      MCycles = 3'b010;
521
                      case (1'b1) // MCycle
522
                        MCycle[0] :
523
                          Set_Addr_To = aXY;
524
                        MCycle[1] :
525 2 ghutchis
                          begin
526 24 ghutchis
                            Read_To_Acc = 1'b1;
527
                            IncDec_16 = 4'b0110;
528 2 ghutchis
                          end
529
 
530 24 ghutchis
                        default :;
531
                      endcase
532
                    end
533 2 ghutchis
                  else
534
                    begin
535 24 ghutchis
                      // LD HL,(nn)
536
                      MCycles = 3'b101;
537
                      case (1'b1) // MCycle
538
                        MCycle[1] :
539 2 ghutchis
                          begin
540 24 ghutchis
                            Inc_PC = 1'b1;
541
                            LDZ = 1'b1;
542 2 ghutchis
                          end
543 24 ghutchis
                        MCycle[2] :
544 2 ghutchis
                          begin
545 24 ghutchis
                            Set_Addr_To = aZI;
546
                            Inc_PC = 1'b1;
547
                            LDW = 1'b1;
548 2 ghutchis
                          end
549 24 ghutchis
                        MCycle[3] :
550 2 ghutchis
                          begin
551 24 ghutchis
                            Set_BusA_To[2:0] = 3'b101; // L
552
                            Read_To_Reg = 1'b1;
553
                            Inc_WZ = 1'b1;
554
                            Set_Addr_To = aZI;
555 2 ghutchis
                          end
556 24 ghutchis
                        MCycle[4] :
557 2 ghutchis
                          begin
558 24 ghutchis
                            Set_BusA_To[2:0] = 3'b100; // H
559
                            Read_To_Reg = 1'b1;
560 2 ghutchis
                          end
561 24 ghutchis
                        default :;
562
                      endcase
563
                    end // else: !if(Mode == 3 )
564 2 ghutchis
                end // case: 8'b00101010
565
 
566 24 ghutchis
              8'b00100010  :
567 2 ghutchis
                begin
568 24 ghutchis
                  if (Mode == 3 )
569 2 ghutchis
                    begin
570 24 ghutchis
                      // LDI (HL),A
571
                      MCycles = 3'b010;
572
                      case (1'b1) // MCycle
573
                        MCycle[0] :
574 2 ghutchis
                          begin
575 24 ghutchis
                            Set_Addr_To = aXY;
576
                            Set_BusB_To = 4'b0111;
577 2 ghutchis
                          end
578 24 ghutchis
                        MCycle[1] :
579 2 ghutchis
                          begin
580 24 ghutchis
                            Write = 1'b1;
581
                            IncDec_16 = 4'b0110;
582 2 ghutchis
                          end
583 24 ghutchis
                        default :;
584
                      endcase
585
                    end
586 2 ghutchis
                  else
587
                    begin
588 24 ghutchis
                      // LD (nn),HL
589
                      MCycles = 3'b101;
590
                      case (1'b1) // MCycle                        
591
                        MCycle[1] :
592 2 ghutchis
                          begin
593 24 ghutchis
                            Inc_PC = 1'b1;
594
                            LDZ = 1'b1;
595 2 ghutchis
                          end
596
 
597 24 ghutchis
                        MCycle[2] :
598 2 ghutchis
                          begin
599 24 ghutchis
                            Set_Addr_To = aZI;
600
                            Inc_PC = 1'b1;
601
                            LDW = 1'b1;
602
                            Set_BusB_To = 4'b0101; // L
603 2 ghutchis
                          end
604
 
605 24 ghutchis
                        MCycle[3] :
606 2 ghutchis
                          begin
607 24 ghutchis
                            Inc_WZ = 1'b1;
608
                            Set_Addr_To = aZI;
609
                            Write = 1'b1;
610
                            Set_BusB_To = 4'b0100; // H
611 2 ghutchis
                          end
612 24 ghutchis
                        MCycle[4] :
613
                          Write = 1'b1;
614
                        default :;
615
                      endcase
616
                    end // else: !if(Mode == 3 )
617 2 ghutchis
                end // case: 8'b00100010
618
 
619 24 ghutchis
              8'b11111001  :
620
                begin
621
                  // LD SP,HL
622
                  TStates = 3'b110;
623
                  LDSPHL = 1'b1;
624
                end
625 2 ghutchis
 
626 90 ghutchis
              8'b11zz0101 :
627 2 ghutchis
                begin
628 24 ghutchis
                  // PUSH qq
629
                  MCycles = 3'b011;
630
                  case (1'b1) // MCycle                    
631
                    MCycle[0] :
632 2 ghutchis
                      begin
633 24 ghutchis
                        TStates = 3'b101;
634
                        IncDec_16 = 4'b1111;
635
                        Set_Addr_To = aSP;
636
                        if (DPAIR == 2'b11 )
637 2 ghutchis
                          begin
638 24 ghutchis
                            Set_BusB_To = 4'b0111;
639
                          end
640 2 ghutchis
                        else
641
                          begin
642 24 ghutchis
                            Set_BusB_To[2:1] = DPAIR;
643
                            Set_BusB_To[0] = 1'b0;
644
                            Set_BusB_To[3] = 1'b0;
645
                          end
646 2 ghutchis
                      end // case: 1
647
 
648 24 ghutchis
                    MCycle[1] :
649 2 ghutchis
                      begin
650 24 ghutchis
                        IncDec_16 = 4'b1111;
651
                        Set_Addr_To = aSP;
652
                        if (DPAIR == 2'b11 )
653 2 ghutchis
                          begin
654 24 ghutchis
                            Set_BusB_To = 4'b1011;
655
                          end
656 2 ghutchis
                        else
657
                          begin
658 24 ghutchis
                            Set_BusB_To[2:1] = DPAIR;
659
                            Set_BusB_To[0] = 1'b1;
660
                            Set_BusB_To[3] = 1'b0;
661
                          end
662
                        Write = 1'b1;
663 2 ghutchis
                      end // case: 2
664
 
665 24 ghutchis
                    MCycle[2] :
666
                      Write = 1'b1;
667
                    default :;
668
                  endcase // case(MCycle)
669 2 ghutchis
                end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
670
 
671 90 ghutchis
              8'b11zz0001 :
672 2 ghutchis
                begin
673 24 ghutchis
                  // POP qq
674
                  MCycles = 3'b011;
675
                  case (1'b1) // MCycle
676
                    MCycle[0] :
677
                      Set_Addr_To = aSP;
678
                    MCycle[1] :
679 2 ghutchis
                      begin
680 24 ghutchis
                        IncDec_16 = 4'b0111;
681
                        Set_Addr_To = aSP;
682
                        Read_To_Reg = 1'b1;
683
                        if (DPAIR == 2'b11 )
684 2 ghutchis
                          begin
685 24 ghutchis
                            Set_BusA_To[3:0] = 4'b1011;
686
                          end
687 2 ghutchis
                        else
688
                          begin
689 24 ghutchis
                            Set_BusA_To[2:1] = DPAIR;
690
                            Set_BusA_To[0] = 1'b1;
691
                          end
692 2 ghutchis
                      end // case: 2
693
 
694 24 ghutchis
                    MCycle[2] :
695 2 ghutchis
                      begin
696 24 ghutchis
                        IncDec_16 = 4'b0111;
697
                        Read_To_Reg = 1'b1;
698
                        if (DPAIR == 2'b11 )
699 2 ghutchis
                          begin
700 24 ghutchis
                            Set_BusA_To[3:0] = 4'b0111;
701
                          end
702 2 ghutchis
                        else
703
                          begin
704 24 ghutchis
                            Set_BusA_To[2:1] = DPAIR;
705
                            Set_BusA_To[0] = 1'b0;
706
                          end
707 2 ghutchis
                      end // case: 3
708
 
709 24 ghutchis
                    default :;
710
                  endcase // case(MCycle)
711 2 ghutchis
                end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001
712
 
713
 
714 24 ghutchis
              // EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
715
              8'b11101011  :
716 2 ghutchis
                begin
717 24 ghutchis
                  if (Mode != 3 )
718 2 ghutchis
                    begin
719 24 ghutchis
                      // EX DE,HL
720
                      ExchangeDH = 1'b1;
721
                    end
722 2 ghutchis
                end
723
 
724 24 ghutchis
              8'b00001000  :
725 2 ghutchis
                begin
726 24 ghutchis
                  if (Mode == 3 )
727 2 ghutchis
                    begin
728 24 ghutchis
                      // LD (nn),SP
729
                      MCycles = 3'b101;
730
                      case (1'b1) // MCycle
731
                        MCycle[1] :
732 2 ghutchis
                          begin
733 24 ghutchis
                            Inc_PC = 1'b1;
734
                            LDZ = 1'b1;
735 2 ghutchis
                          end
736
 
737 24 ghutchis
                        MCycle[2] :
738 2 ghutchis
                          begin
739 24 ghutchis
                            Set_Addr_To = aZI;
740
                            Inc_PC = 1'b1;
741
                            LDW = 1'b1;
742
                            Set_BusB_To = 4'b1000;
743 2 ghutchis
                          end
744
 
745 24 ghutchis
                        MCycle[3] :
746 2 ghutchis
                          begin
747 24 ghutchis
                            Inc_WZ = 1'b1;
748
                            Set_Addr_To = aZI;
749
                            Write = 1'b1;
750
                            Set_BusB_To = 4'b1001;
751 2 ghutchis
                          end
752
 
753 24 ghutchis
                        MCycle[4] :
754
                          Write = 1'b1;
755
                        default :;
756
                      endcase
757
                    end
758 2 ghutchis
                  else if (Mode < 2 )
759
                    begin
760 24 ghutchis
                      // EX AF,AF'
761
                      ExchangeAF = 1'b1;
762
                    end
763 2 ghutchis
                end // case: 8'b00001000
764
 
765 24 ghutchis
              8'b11011001  :
766 2 ghutchis
                begin
767 24 ghutchis
                  if (Mode == 3 )
768 2 ghutchis
                    begin
769 24 ghutchis
                      // RETI
770
                      MCycles = 3'b011;
771
                      case (1'b1) // MCycle
772
                        MCycle[0] :
773
                          Set_Addr_To = aSP;
774
                        MCycle[1] :
775 2 ghutchis
                          begin
776 24 ghutchis
                            IncDec_16 = 4'b0111;
777
                            Set_Addr_To = aSP;
778
                            LDZ = 1'b1;
779 2 ghutchis
                          end
780
 
781 24 ghutchis
                        MCycle[2] :
782 2 ghutchis
                          begin
783 24 ghutchis
                            Jump = 1'b1;
784
                            IncDec_16 = 4'b0111;
785
                            I_RETN = 1'b1;
786
                            SetEI = 1'b1;
787 2 ghutchis
                          end
788 24 ghutchis
                        default :;
789
                      endcase
790
                    end
791 2 ghutchis
                  else if (Mode < 2 )
792
                    begin
793 24 ghutchis
                      // EXX
794
                      ExchangeRS = 1'b1;
795
                    end
796 2 ghutchis
                end // case: 8'b11011001
797
 
798 24 ghutchis
              8'b11100011  :
799 2 ghutchis
                begin
800 24 ghutchis
                  if (Mode != 3 )
801 2 ghutchis
                    begin
802 24 ghutchis
                      // EX (SP),HL
803
                      MCycles = 3'b101;
804
                      case (1'b1) // MCycle
805
                        MCycle[0] :
806
                          Set_Addr_To = aSP;
807
                        MCycle[1] :
808 2 ghutchis
                          begin
809 24 ghutchis
                            Read_To_Reg = 1'b1;
810
                            Set_BusA_To = 4'b0101;
811
                            Set_BusB_To = 4'b0101;
812
                            Set_Addr_To = aSP;
813 2 ghutchis
                          end
814 24 ghutchis
                        MCycle[2] :
815 2 ghutchis
                          begin
816 24 ghutchis
                            IncDec_16 = 4'b0111;
817
                            Set_Addr_To = aSP;
818
                            TStates = 3'b100;
819
                            Write = 1'b1;
820 2 ghutchis
                          end
821 24 ghutchis
                        MCycle[3] :
822 2 ghutchis
                          begin
823 24 ghutchis
                            Read_To_Reg = 1'b1;
824
                            Set_BusA_To = 4'b0100;
825
                            Set_BusB_To = 4'b0100;
826
                            Set_Addr_To = aSP;
827 2 ghutchis
                          end
828 24 ghutchis
                        MCycle[4] :
829 2 ghutchis
                          begin
830 24 ghutchis
                            IncDec_16 = 4'b1111;
831
                            TStates = 3'b101;
832
                            Write = 1'b1;
833 2 ghutchis
                          end
834
 
835 24 ghutchis
                        default :;
836
                      endcase
837
                    end // if (Mode != 3 )
838 2 ghutchis
                end // case: 8'b11100011
839
 
840
 
841 24 ghutchis
              // 8 BIT ARITHMETIC AND LOGICAL GROUP
842 90 ghutchis
              8'b10zzzzzz :
843 2 ghutchis
                begin
844 24 ghutchis
                  if (IR[2:0] == 3'b110)
845
                    begin
846
                      // ADD A,(HL)
847
                      // ADC A,(HL)
848
                      // SUB A,(HL)
849
                      // SBC A,(HL)
850
                      // AND A,(HL)
851
                      // OR A,(HL)
852
                      // XOR A,(HL)
853
                      // CP A,(HL)
854
                      MCycles = 3'b010;
855
                      case (1'b1) // MCycle
856
                        MCycle[0] :
857
                          Set_Addr_To = aXY;
858
                        MCycle[1] :
859
                          begin
860
                            Read_To_Reg = 1'b1;
861
                            Save_ALU = 1'b1;
862
                            Set_BusB_To[2:0] = SSS;
863
                            Set_BusA_To[2:0] = 3'b111;
864
                          end
865
 
866
                        default :;
867
                      endcase // case(MCycle)
868
                    end // if (IR[2:0] == 3'b110)
869
                  else
870
                    begin
871
                      // ADD A,r
872
                      // ADC A,r
873
                      // SUB A,r
874
                      // SBC A,r
875
                      // AND A,r
876
                      // OR A,r
877
                      // XOR A,r
878
                      // CP A,r
879
                      Set_BusB_To[2:0] = SSS;
880
                      Set_BusA_To[2:0] = 3'b111;
881
                      Read_To_Reg = 1'b1;
882
                      Save_ALU = 1'b1;
883
                    end // else: !if(IR[2:0] == 3'b110)                  
884 2 ghutchis
                end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
885
 
886 90 ghutchis
              8'b11zzz110 :
887 2 ghutchis
                begin
888 24 ghutchis
                  // ADD A,n
889
                  // ADC A,n
890
                  // SUB A,n
891
                  // SBC A,n
892
                  // AND A,n
893
                  // OR A,n
894
                  // XOR A,n
895
                  // CP A,n
896
                  MCycles = 3'b010;
897
                  if (MCycle[1] )
898
                    begin
899
                      Inc_PC = 1'b1;
900
                      Read_To_Reg = 1'b1;
901
                      Save_ALU = 1'b1;
902
                      Set_BusB_To[2:0] = SSS;
903
                      Set_BusA_To[2:0] = 3'b111;
904
                    end
905
                end
906 2 ghutchis
 
907 90 ghutchis
              8'b00zzz100 :
908 2 ghutchis
                begin
909 80 ghutchis
                  if (IR[5:3] == 3'b110)
910 2 ghutchis
                    begin
911 24 ghutchis
                      // INC (HL)
912
                      MCycles = 3'b011;
913
                      case (1'b1) // MCycle
914
                        MCycle[0] :
915
                          Set_Addr_To = aXY;
916
                        MCycle[1] :
917
                          begin
918
                            TStates = 3'b100;
919
                            Set_Addr_To = aXY;
920
                            Read_To_Reg = 1'b1;
921
                            Save_ALU = 1'b1;
922
                            PreserveC = 1'b1;
923
                            ALU_Op = 4'b0000;
924
                            Set_BusB_To = 4'b1010;
925
                            Set_BusA_To[2:0] = DDD;
926
                          end // case: 2
927
 
928
                        MCycle[2] :
929
                          Write = 1'b1;
930
                        default :;
931
                      endcase // case(MCycle)
932
                    end // case: 8'b00110100
933
                  else
934
                    begin
935
                      // INC r
936
                      Set_BusB_To = 4'b1010;
937
                      Set_BusA_To[2:0] = DDD;
938
                      Read_To_Reg = 1'b1;
939
                      Save_ALU = 1'b1;
940
                      PreserveC = 1'b1;
941
                      ALU_Op = 4'b0000;
942
                    end
943 2 ghutchis
                end
944
 
945 90 ghutchis
              8'b00zzz101 :
946 2 ghutchis
                begin
947 80 ghutchis
                  if (IR[5:3] == 3'b110)
948 24 ghutchis
                    begin
949
                      // DEC (HL)
950
                      MCycles = 3'b011;
951
                      case (1'b1) // MCycle
952
                        MCycle[0] :
953
                          Set_Addr_To = aXY;
954
                        MCycle[1] :
955
                          begin
956
                            TStates = 3'b100;
957
                            Set_Addr_To = aXY;
958
                            ALU_Op = 4'b0010;
959
                            Read_To_Reg = 1'b1;
960
                            Save_ALU = 1'b1;
961
                            PreserveC = 1'b1;
962
                            Set_BusB_To = 4'b1010;
963
                            Set_BusA_To[2:0] = DDD;
964
                          end // case: 2
965
 
966
                        MCycle[2] :
967
                          Write = 1'b1;
968
                        default :;
969
                      endcase // case(MCycle)
970
                    end
971
                  else
972
                    begin
973
                      // DEC r
974
                      Set_BusB_To = 4'b1010;
975
                      Set_BusA_To[2:0] = DDD;
976
                      Read_To_Reg = 1'b1;
977
                      Save_ALU = 1'b1;
978
                      PreserveC = 1'b1;
979
                      ALU_Op = 4'b0010;
980
                    end
981 2 ghutchis
                end
982
 
983 24 ghutchis
              // GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
984
              8'b00100111  :
985 2 ghutchis
                begin
986 24 ghutchis
                  // DAA
987
                  Set_BusA_To[2:0] = 3'b111;
988
                  Read_To_Reg = 1'b1;
989
                  ALU_Op = 4'b1100;
990
                  Save_ALU = 1'b1;
991
                end
992 2 ghutchis
 
993 24 ghutchis
              8'b00101111  :
994
                // CPL
995
                I_CPL = 1'b1;
996 2 ghutchis
 
997 24 ghutchis
              8'b00111111  :
998
                // CCF
999
                I_CCF = 1'b1;
1000 2 ghutchis
 
1001 24 ghutchis
              8'b00110111  :
1002
                // SCF
1003
                I_SCF = 1'b1;
1004 2 ghutchis
 
1005 24 ghutchis
              8'b00000000  :
1006
                begin
1007
                  if (NMICycle == 1'b1 )
1008
                    begin
1009
                      // NMI
1010
                      MCycles = 3'b011;
1011
                      case (1'b1) // MCycle
1012
                        MCycle[0] :
1013
                          begin
1014
                            TStates = 3'b101;
1015
                            IncDec_16 = 4'b1111;
1016
                            Set_Addr_To = aSP;
1017
                            Set_BusB_To = 4'b1101;
1018
                          end
1019 2 ghutchis
 
1020 24 ghutchis
                        MCycle[1] :
1021
                          begin
1022
                            TStates = 3'b100;
1023
                            Write = 1'b1;
1024
                            IncDec_16 = 4'b1111;
1025
                            Set_Addr_To = aSP;
1026
                            Set_BusB_To = 4'b1100;
1027
                          end
1028
 
1029
                        MCycle[2] :
1030
                          begin
1031
                            TStates = 3'b100;
1032
                            Write = 1'b1;
1033
                          end
1034
 
1035
                        default :;
1036
                      endcase // case(MCycle)
1037
 
1038
                    end
1039
                  else if (IntCycle == 1'b1 )
1040
                    begin
1041
                      // INT (IM 2)
1042
                      MCycles = 3'b101;
1043
                      case (1'b1) // MCycle
1044
                        MCycle[0] :
1045
                          begin
1046
                            LDZ = 1'b1;
1047
                            TStates = 3'b101;
1048
                            IncDec_16 = 4'b1111;
1049
                            Set_Addr_To = aSP;
1050
                            Set_BusB_To = 4'b1101;
1051
                          end
1052
 
1053
                        MCycle[1] :
1054
                          begin
1055
                            TStates = 3'b100;
1056
                            Write = 1'b1;
1057
                            IncDec_16 = 4'b1111;
1058
                            Set_Addr_To = aSP;
1059
                            Set_BusB_To = 4'b1100;
1060
                          end
1061
 
1062
                        MCycle[2] :
1063
                          begin
1064
                            TStates = 3'b100;
1065
                            Write = 1'b1;
1066
                          end
1067
 
1068
                        MCycle[3] :
1069
                          begin
1070
                            Inc_PC = 1'b1;
1071
                            LDZ = 1'b1;
1072
                          end
1073
 
1074
                        MCycle[4] :
1075
                          Jump = 1'b1;
1076
                        default :;
1077
                      endcase
1078
                    end
1079
                end // case: 8'b00000000
1080 2 ghutchis
 
1081 24 ghutchis
              8'b11110011  :
1082
                // DI
1083
                SetDI = 1'b1;
1084 2 ghutchis
 
1085 24 ghutchis
              8'b11111011  :
1086
                // EI
1087
                SetEI = 1'b1;
1088 2 ghutchis
 
1089
              // 16 BIT ARITHMETIC GROUP
1090 90 ghutchis
              8'b00zz1001  :
1091 2 ghutchis
                begin
1092 24 ghutchis
                  // ADD HL,ss
1093
                  MCycles = 3'b011;
1094
                  case (1'b1) // MCycle
1095
                    MCycle[1] :
1096 2 ghutchis
                      begin
1097 24 ghutchis
                        NoRead = 1'b1;
1098
                        ALU_Op = 4'b0000;
1099
                        Read_To_Reg = 1'b1;
1100
                        Save_ALU = 1'b1;
1101
                        Set_BusA_To[2:0] = 3'b101;
1102
                        case (IR[5:4])
1103
                          0,1,2  :
1104 2 ghutchis
                            begin
1105 24 ghutchis
                              Set_BusB_To[2:1] = IR[5:4];
1106
                              Set_BusB_To[0] = 1'b1;
1107 2 ghutchis
                            end
1108
 
1109 24 ghutchis
                          default :
1110
                            Set_BusB_To = 4'b1000;
1111
                        endcase // case(IR[5:4])
1112 2 ghutchis
 
1113 24 ghutchis
                        TStates = 3'b100;
1114
                        Arith16 = 1'b1;
1115 2 ghutchis
                      end // case: 2
1116
 
1117 24 ghutchis
                    MCycle[2] :
1118 2 ghutchis
                      begin
1119 24 ghutchis
                        NoRead = 1'b1;
1120
                        Read_To_Reg = 1'b1;
1121
                        Save_ALU = 1'b1;
1122
                        ALU_Op = 4'b0001;
1123
                        Set_BusA_To[2:0] = 3'b100;
1124
                        case (IR[5:4])
1125
                          0,1,2  :
1126
                            Set_BusB_To[2:1] = IR[5:4];
1127
                          default :
1128
                            Set_BusB_To = 4'b1001;
1129
                        endcase
1130
                        Arith16 = 1'b1;
1131 2 ghutchis
                      end // case: 3
1132
 
1133 24 ghutchis
                    default :;
1134
                  endcase // case(MCycle)
1135 2 ghutchis
                end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001              
1136 24 ghutchis
 
1137 90 ghutchis
              8'b00zz0011 :
1138 2 ghutchis
                begin
1139 24 ghutchis
                  // INC ss
1140
                  TStates = 3'b110;
1141
                  IncDec_16[3:2] = 2'b01;
1142
                  IncDec_16[1:0] = DPAIR;
1143 2 ghutchis
                end
1144
 
1145 90 ghutchis
              8'b00zz1011 :
1146 2 ghutchis
                begin
1147 24 ghutchis
                  // DEC ss
1148
                  TStates = 3'b110;
1149
                  IncDec_16[3:2] = 2'b11;
1150
                  IncDec_16[1:0] = DPAIR;
1151 2 ghutchis
                end
1152
 
1153 24 ghutchis
              // ROTATE AND SHIFT GROUP
1154
              8'b00000111,
1155
                  // RLCA
1156
                  8'b00010111,
1157
                  // RLA
1158
                  8'b00001111,
1159
                  // RRCA
1160
                  8'b00011111 :
1161
                    // RRA
1162
                    begin
1163
                      Set_BusA_To[2:0] = 3'b111;
1164
                      ALU_Op = 4'b1000;
1165
                      Read_To_Reg = 1'b1;
1166
                      Save_ALU = 1'b1;
1167
                    end // case: 8'b00000111,...
1168 2 ghutchis
 
1169
 
1170 24 ghutchis
              // JUMP GROUP
1171
              8'b11000011  :
1172 2 ghutchis
                begin
1173 24 ghutchis
                  // JP nn
1174
                  MCycles = 3'b011;
1175 23 ghutchis
                  if (MCycle[1])
1176 24 ghutchis
                    begin
1177
                      Inc_PC = 1'b1;
1178
                      LDZ = 1'b1;
1179
                    end
1180
 
1181 23 ghutchis
                  if (MCycle[2])
1182 24 ghutchis
                    begin
1183
                      Inc_PC = 1'b1;
1184
                      Jump = 1'b1;
1185
                    end
1186
 
1187 2 ghutchis
                end // case: 8'b11000011
1188
 
1189 90 ghutchis
              8'b11zzz010  :
1190 2 ghutchis
                begin
1191 24 ghutchis
                  if (IR[5] == 1'b1 && Mode == 3 )
1192 2 ghutchis
                    begin
1193 80 ghutchis
                      case (IR[4:3])
1194 24 ghutchis
                        2'b00  :
1195 2 ghutchis
                          begin
1196 24 ghutchis
                            // LD ($FF00+C),A
1197
                            MCycles = 3'b010;
1198
                            case (1'b1) // MCycle
1199
                              MCycle[0] :
1200 2 ghutchis
                                begin
1201 24 ghutchis
                                  Set_Addr_To = aBC;
1202
                                  Set_BusB_To   = 4'b0111;
1203 2 ghutchis
                                end
1204 24 ghutchis
                              MCycle[1] :
1205 2 ghutchis
                                begin
1206 24 ghutchis
                                  Write = 1'b1;
1207
                                  IORQ = 1'b1;
1208 2 ghutchis
                                end
1209
 
1210 24 ghutchis
                              default :;
1211
                            endcase // case(MCycle)
1212 2 ghutchis
                          end // case: 2'b00
1213
 
1214 24 ghutchis
                        2'b01  :
1215 2 ghutchis
                          begin
1216 24 ghutchis
                            // LD (nn),A
1217
                            MCycles = 3'b100;
1218
                            case (1'b1) // MCycle
1219
                              MCycle[1] :
1220 2 ghutchis
                                begin
1221 24 ghutchis
                                  Inc_PC = 1'b1;
1222
                                  LDZ = 1'b1;
1223 2 ghutchis
                                end
1224
 
1225 24 ghutchis
                              MCycle[2] :
1226 2 ghutchis
                                begin
1227 24 ghutchis
                                  Set_Addr_To = aZI;
1228
                                  Inc_PC = 1'b1;
1229
                                  Set_BusB_To = 4'b0111;
1230 2 ghutchis
                                end
1231
 
1232 24 ghutchis
                              MCycle[3] :
1233
                                Write = 1'b1;
1234
                              default :;
1235
                            endcase // case(MCycle)
1236 2 ghutchis
                          end // case: default :...
1237
 
1238 24 ghutchis
                        2'b10  :
1239 2 ghutchis
                          begin
1240 24 ghutchis
                            // LD A,($FF00+C)
1241
                            MCycles = 3'b010;
1242
                            case (1'b1) // MCycle
1243
                              MCycle[0] :
1244
                                Set_Addr_To = aBC;
1245
                              MCycle[1] :
1246 2 ghutchis
                                begin
1247 24 ghutchis
                                  Read_To_Acc = 1'b1;
1248
                                  IORQ = 1'b1;
1249 2 ghutchis
                                end
1250 24 ghutchis
                              default :;
1251
                            endcase // case(MCycle)
1252 2 ghutchis
                          end // case: 2'b10
1253
 
1254 24 ghutchis
                        2'b11  :
1255 2 ghutchis
                          begin
1256 24 ghutchis
                            // LD A,(nn)
1257
                            MCycles = 3'b100;
1258
                            case (1'b1) // MCycle
1259
                              MCycle[1] :
1260 2 ghutchis
                                begin
1261 24 ghutchis
                                  Inc_PC = 1'b1;
1262
                                  LDZ = 1'b1;
1263 2 ghutchis
                                end
1264 24 ghutchis
                              MCycle[2] :
1265 2 ghutchis
                                begin
1266 24 ghutchis
                                  Set_Addr_To = aZI;
1267
                                  Inc_PC = 1'b1;
1268 2 ghutchis
                                end
1269 24 ghutchis
                              MCycle[3] :
1270
                                Read_To_Acc = 1'b1;
1271
                              default :;
1272
                            endcase // case(MCycle)
1273 2 ghutchis
                          end
1274 24 ghutchis
                      endcase
1275
                    end
1276 2 ghutchis
                  else
1277
                    begin
1278 24 ghutchis
                      // JP cc,nn
1279
                      MCycles = 3'b011;
1280
                      case (1'b1) // MCycle
1281
                        MCycle[1] :
1282 2 ghutchis
                          begin
1283 24 ghutchis
                            Inc_PC = 1'b1;
1284
                            LDZ = 1'b1;
1285 2 ghutchis
                          end
1286 24 ghutchis
                        MCycle[2] :
1287 2 ghutchis
                          begin
1288 24 ghutchis
                            Inc_PC = 1'b1;
1289
                            if (is_cc_true(F, IR[5:3]) )
1290 2 ghutchis
                              begin
1291 24 ghutchis
                                Jump = 1'b1;
1292
                              end
1293 2 ghutchis
                          end
1294
 
1295 24 ghutchis
                        default :;
1296
                      endcase
1297
                    end // else: !if(DPAIR == 2'b11 )
1298 2 ghutchis
                end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010
1299
 
1300 24 ghutchis
              8'b00011000  :
1301 2 ghutchis
                begin
1302 24 ghutchis
                  if (Mode != 2 )
1303 2 ghutchis
                    begin
1304 24 ghutchis
                      // JR e
1305
                      MCycles = 3'b011;
1306
                      case (1'b1) // MCycle
1307
                        MCycle[1] :
1308
                          Inc_PC = 1'b1;
1309
                        MCycle[2] :
1310 2 ghutchis
                          begin
1311 24 ghutchis
                            NoRead = 1'b1;
1312
                            JumpE = 1'b1;
1313
                            TStates = 3'b101;
1314 2 ghutchis
                          end
1315 24 ghutchis
                        default :;
1316
                      endcase
1317
                    end // if (Mode != 2 )
1318 2 ghutchis
                end // case: 8'b00011000
1319 80 ghutchis
 
1320
              // Conditional relative jumps (JR [C/NC/Z/NZ], e)
1321 90 ghutchis
              8'b001zz000  :
1322 2 ghutchis
                begin
1323 24 ghutchis
                  if (Mode != 2 )
1324 2 ghutchis
                    begin
1325 80 ghutchis
                      MCycles = 3'd3;
1326 24 ghutchis
                      case (1'b1) // MCycle
1327
                        MCycle[1] :
1328 2 ghutchis
                          begin
1329 24 ghutchis
                            Inc_PC = 1'b1;
1330 80 ghutchis
 
1331
                            case (IR[4:3])
1332
 
1333
                              1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3;
1334
                              2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3;
1335
                              3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3;
1336
                            endcase
1337 2 ghutchis
                          end
1338
 
1339 24 ghutchis
                        MCycle[2] :
1340 2 ghutchis
                          begin
1341 24 ghutchis
                            NoRead = 1'b1;
1342
                            JumpE = 1'b1;
1343 80 ghutchis
                            TStates = 3'd5;
1344 2 ghutchis
                          end
1345 24 ghutchis
                        default :;
1346
                      endcase
1347
                    end // if (Mode != 2 )
1348 80 ghutchis
                end // case: 8'b00111000              
1349 2 ghutchis
 
1350 24 ghutchis
              8'b11101001  :
1351
                // JP (HL)
1352
                JumpXY = 1'b1;
1353 2 ghutchis
 
1354 24 ghutchis
              8'b00010000  :
1355 2 ghutchis
                begin
1356 24 ghutchis
                  if (Mode == 3 )
1357 2 ghutchis
                    begin
1358 24 ghutchis
                      I_DJNZ = 1'b1;
1359
                    end
1360 2 ghutchis
                  else if (Mode < 2 )
1361
                    begin
1362 24 ghutchis
                      // DJNZ,e
1363
                      MCycles = 3'b011;
1364
                      case (1'b1) // MCycle
1365
                        MCycle[0] :
1366 2 ghutchis
                          begin
1367 24 ghutchis
                            TStates = 3'b101;
1368
                            I_DJNZ = 1'b1;
1369
                            Set_BusB_To = 4'b1010;
1370
                            Set_BusA_To[2:0] = 3'b000;
1371
                            Read_To_Reg = 1'b1;
1372
                            Save_ALU = 1'b1;
1373
                            ALU_Op = 4'b0010;
1374 2 ghutchis
                          end
1375 24 ghutchis
                        MCycle[1] :
1376 2 ghutchis
                          begin
1377 24 ghutchis
                            I_DJNZ = 1'b1;
1378
                            Inc_PC = 1'b1;
1379 2 ghutchis
                          end
1380 24 ghutchis
                        MCycle[2] :
1381 2 ghutchis
                          begin
1382 24 ghutchis
                            NoRead = 1'b1;
1383
                            JumpE = 1'b1;
1384
                            TStates = 3'b101;
1385 2 ghutchis
                          end
1386 24 ghutchis
                        default :;
1387
                      endcase
1388
                    end // if (Mode < 2 )
1389 2 ghutchis
                end // case: 8'b00010000
1390
 
1391
 
1392 24 ghutchis
              // CALL AND RETURN GROUP
1393
              8'b11001101  :
1394 2 ghutchis
                begin
1395 24 ghutchis
                  // CALL nn
1396
                  MCycles = 3'b101;
1397
                  case (1'b1) // MCycle
1398
                    MCycle[1] :
1399 2 ghutchis
                      begin
1400 24 ghutchis
                        Inc_PC = 1'b1;
1401
                        LDZ = 1'b1;
1402 2 ghutchis
                      end
1403 24 ghutchis
                    MCycle[2] :
1404 2 ghutchis
                      begin
1405 24 ghutchis
                        IncDec_16 = 4'b1111;
1406
                        Inc_PC = 1'b1;
1407
                        TStates = 3'b100;
1408
                        Set_Addr_To = aSP;
1409
                        LDW = 1'b1;
1410
                        Set_BusB_To = 4'b1101;
1411 2 ghutchis
                      end
1412 24 ghutchis
                    MCycle[3] :
1413 2 ghutchis
                      begin
1414 24 ghutchis
                        Write = 1'b1;
1415
                        IncDec_16 = 4'b1111;
1416
                        Set_Addr_To = aSP;
1417
                        Set_BusB_To = 4'b1100;
1418 2 ghutchis
                      end
1419 24 ghutchis
                    MCycle[4] :
1420 2 ghutchis
                      begin
1421 24 ghutchis
                        Write = 1'b1;
1422
                        Call = 1'b1;
1423 2 ghutchis
                      end
1424 24 ghutchis
                    default :;
1425
                  endcase // case(MCycle)
1426 2 ghutchis
                end // case: 8'b11001101
1427
 
1428 90 ghutchis
              8'b11zzz100  :
1429 2 ghutchis
                begin
1430 24 ghutchis
                  if (IR[5] == 1'b0 || Mode != 3 )
1431 2 ghutchis
                    begin
1432 24 ghutchis
                      // CALL cc,nn
1433
                      MCycles = 3'b101;
1434
                      case (1'b1) // MCycle
1435
                        MCycle[1] :
1436 2 ghutchis
                          begin
1437 24 ghutchis
                            Inc_PC = 1'b1;
1438
                            LDZ = 1'b1;
1439 2 ghutchis
                          end
1440 24 ghutchis
                        MCycle[2] :
1441 2 ghutchis
                          begin
1442 24 ghutchis
                            Inc_PC = 1'b1;
1443
                            LDW = 1'b1;
1444
                            if (is_cc_true(F, IR[5:3]) )
1445 2 ghutchis
                              begin
1446 24 ghutchis
                                IncDec_16 = 4'b1111;
1447
                                Set_Addr_To = aSP;
1448
                                TStates = 3'b100;
1449
                                Set_BusB_To = 4'b1101;
1450
                              end
1451 2 ghutchis
                            else
1452
                              begin
1453 24 ghutchis
                                MCycles = 3'b011;
1454
                              end // else: !if(is_cc_true(F, IR[5:3]) )
1455 2 ghutchis
                          end // case: 3
1456
 
1457 24 ghutchis
                        MCycle[3] :
1458 2 ghutchis
                          begin
1459 24 ghutchis
                            Write = 1'b1;
1460
                            IncDec_16 = 4'b1111;
1461
                            Set_Addr_To = aSP;
1462
                            Set_BusB_To = 4'b1100;
1463 2 ghutchis
                          end
1464
 
1465 24 ghutchis
                        MCycle[4] :
1466 2 ghutchis
                          begin
1467 24 ghutchis
                            Write = 1'b1;
1468
                            Call = 1'b1;
1469 2 ghutchis
                          end
1470
 
1471 24 ghutchis
                        default :;
1472
                      endcase
1473
                    end // if (IR[5] == 1'b0 || Mode != 3 )
1474 2 ghutchis
                end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100
1475
 
1476 24 ghutchis
              8'b11001001  :
1477 2 ghutchis
                begin
1478 24 ghutchis
                  // RET
1479
                  MCycles = 3'b011;
1480
                  case (1'b1) // MCycle
1481
                    MCycle[0] :
1482 2 ghutchis
                      begin
1483 24 ghutchis
                        TStates = 3'b101;
1484
                        Set_Addr_To = aSP;
1485 2 ghutchis
                      end
1486
 
1487 24 ghutchis
                    MCycle[1] :
1488 2 ghutchis
                      begin
1489 24 ghutchis
                        IncDec_16 = 4'b0111;
1490
                        Set_Addr_To = aSP;
1491
                        LDZ = 1'b1;
1492 2 ghutchis
                      end
1493
 
1494 24 ghutchis
                    MCycle[2] :
1495 2 ghutchis
                      begin
1496 24 ghutchis
                        Jump = 1'b1;
1497
                        IncDec_16 = 4'b0111;
1498 2 ghutchis
                      end
1499
 
1500 24 ghutchis
                    default :;
1501
                  endcase // case(MCycle)
1502 2 ghutchis
                end // case: 8'b11001001
1503
 
1504 24 ghutchis
              8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000  :
1505 2 ghutchis
                begin
1506 24 ghutchis
                  if (IR[5] == 1'b1 && Mode == 3 )
1507 2 ghutchis
                    begin
1508 80 ghutchis
                      case (IR[4:3])
1509 24 ghutchis
                        2'b00  :
1510 2 ghutchis
                          begin
1511 24 ghutchis
                            // LD ($FF00+nn),A
1512
                            MCycles = 3'b011;
1513
                            case (1'b1) // MCycle
1514
                              MCycle[1] :
1515 2 ghutchis
                                begin
1516 24 ghutchis
                                  Inc_PC = 1'b1;
1517
                                  Set_Addr_To = aIOA;
1518
                                  Set_BusB_To   = 4'b0111;
1519 2 ghutchis
                                end
1520
 
1521 24 ghutchis
                              MCycle[2] :
1522
                                Write = 1'b1;
1523
                              default :;
1524
                            endcase // case(MCycle)
1525 2 ghutchis
                          end // case: 2'b00
1526
 
1527 24 ghutchis
                        2'b01  :
1528 2 ghutchis
                          begin
1529 24 ghutchis
                            // ADD SP,n
1530
                            MCycles = 3'b011;
1531
                            case (1'b1) // MCycle
1532
                              MCycle[1] :
1533 2 ghutchis
                                begin
1534 24 ghutchis
                                  ALU_Op = 4'b0000;
1535
                                  Inc_PC = 1'b1;
1536
                                  Read_To_Reg = 1'b1;
1537
                                  Save_ALU = 1'b1;
1538
                                  Set_BusA_To = 4'b1000;
1539
                                  Set_BusB_To = 4'b0110;
1540 2 ghutchis
                                end
1541
 
1542 24 ghutchis
                              MCycle[2] :
1543 2 ghutchis
                                begin
1544 24 ghutchis
                                  NoRead = 1'b1;
1545
                                  Read_To_Reg = 1'b1;
1546
                                  Save_ALU = 1'b1;
1547
                                  ALU_Op = 4'b0001;
1548
                                  Set_BusA_To = 4'b1001;
1549
                                  Set_BusB_To = 4'b1110;        // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
1550 2 ghutchis
                                end
1551
 
1552 24 ghutchis
                              default :;
1553
                            endcase // case(MCycle)
1554 2 ghutchis
                          end // case: 2'b01
1555
 
1556 24 ghutchis
                        2'b10  :
1557 2 ghutchis
                          begin
1558 24 ghutchis
                            // LD A,($FF00+nn)
1559
                            MCycles = 3'b011;
1560
                            case (1'b1) // MCycle
1561
                              MCycle[1] :
1562 2 ghutchis
                                begin
1563 24 ghutchis
                                  Inc_PC = 1'b1;
1564
                                  Set_Addr_To = aIOA;
1565 2 ghutchis
                                end
1566
 
1567 24 ghutchis
                              MCycle[2] :
1568
                                Read_To_Acc = 1'b1;
1569
                              default :;
1570
                            endcase // case(MCycle)
1571 2 ghutchis
                          end // case: 2'b10
1572
 
1573 24 ghutchis
                        2'b11  :
1574 2 ghutchis
                          begin
1575 24 ghutchis
                            // LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
1576
                            MCycles = 3'b101;
1577
                            case (1'b1) // MCycle
1578
                              MCycle[1] :
1579 2 ghutchis
                                begin
1580 24 ghutchis
                                  Inc_PC = 1'b1;
1581
                                  LDZ = 1'b1;
1582 2 ghutchis
                                end
1583
 
1584 24 ghutchis
                              MCycle[2] :
1585 2 ghutchis
                                begin
1586 24 ghutchis
                                  Set_Addr_To = aZI;
1587
                                  Inc_PC = 1'b1;
1588
                                  LDW = 1'b1;
1589 2 ghutchis
                                end
1590
 
1591 24 ghutchis
                              MCycle[3] :
1592 2 ghutchis
                                begin
1593 24 ghutchis
                                  Set_BusA_To[2:0] = 3'b101; // L
1594
                                  Read_To_Reg = 1'b1;
1595
                                  Inc_WZ = 1'b1;
1596
                                  Set_Addr_To = aZI;
1597 2 ghutchis
                                end
1598
 
1599 24 ghutchis
                              MCycle[4] :
1600 2 ghutchis
                                begin
1601 24 ghutchis
                                  Set_BusA_To[2:0] = 3'b100; // H
1602
                                  Read_To_Reg = 1'b1;
1603 2 ghutchis
                                end
1604
 
1605 24 ghutchis
                              default :;
1606
                            endcase // case(MCycle)
1607 2 ghutchis
                          end // case: 2'b11
1608
 
1609 80 ghutchis
                      endcase // case(IR[4:3])
1610 2 ghutchis
 
1611 24 ghutchis
                    end
1612 2 ghutchis
                  else
1613
                    begin
1614 24 ghutchis
                      // RET cc
1615
                      MCycles = 3'b011;
1616
                      case (1'b1) // MCycle
1617
                        MCycle[0] :
1618 2 ghutchis
                          begin
1619 24 ghutchis
                            if (is_cc_true(F, IR[5:3]) )
1620 2 ghutchis
                              begin
1621 24 ghutchis
                                Set_Addr_To = aSP;
1622
                              end
1623 2 ghutchis
                            else
1624
                              begin
1625
                                MCycles = 3'b001;
1626 24 ghutchis
                              end
1627
                            TStates = 3'b101;
1628 2 ghutchis
                          end // case: 1
1629
 
1630 24 ghutchis
                        MCycle[1] :
1631
                          begin
1632
                            IncDec_16 = 4'b0111;
1633
                            Set_Addr_To = aSP;
1634
                            LDZ = 1'b1;
1635 2 ghutchis
                          end
1636 24 ghutchis
                        MCycle[2] :
1637
                          begin
1638
                            Jump = 1'b1;
1639
                            IncDec_16 = 4'b0111;
1640 2 ghutchis
                          end
1641 24 ghutchis
                        default :;
1642
                      endcase
1643
                    end // else: !if(IR[5] == 1'b1 && Mode == 3 )
1644 2 ghutchis
                end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000
1645
 
1646 24 ghutchis
              8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111  :
1647 2 ghutchis
                begin
1648 24 ghutchis
                  // RST p
1649
                  MCycles = 3'b011;
1650
                  case (1'b1) // MCycle
1651
                    MCycle[0] :
1652 2 ghutchis
                      begin
1653 24 ghutchis
                        TStates = 3'b101;
1654
                        IncDec_16 = 4'b1111;
1655
                        Set_Addr_To = aSP;
1656
                        Set_BusB_To = 4'b1101;
1657 2 ghutchis
                      end
1658
 
1659 24 ghutchis
                    MCycle[1] :
1660 2 ghutchis
                      begin
1661 24 ghutchis
                        Write = 1'b1;
1662
                        IncDec_16 = 4'b1111;
1663
                        Set_Addr_To = aSP;
1664
                        Set_BusB_To = 4'b1100;
1665 2 ghutchis
                      end
1666
 
1667 24 ghutchis
                    MCycle[2] :
1668 2 ghutchis
                      begin
1669 24 ghutchis
                        Write = 1'b1;
1670
                        RstP = 1'b1;
1671 2 ghutchis
                      end
1672
 
1673 24 ghutchis
                    default :;
1674
                  endcase // case(MCycle)
1675 2 ghutchis
                end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111
1676
 
1677 24 ghutchis
              // INPUT AND OUTPUT GROUP
1678
              8'b11011011  :
1679 2 ghutchis
                begin
1680 24 ghutchis
                  if (Mode != 3 )
1681 2 ghutchis
                    begin
1682 24 ghutchis
                      // IN A,(n)
1683
                      MCycles = 3'b011;
1684
                      case (1'b1) // MCycle
1685
                        MCycle[1] :
1686 2 ghutchis
                          begin
1687 24 ghutchis
                            Inc_PC = 1'b1;
1688
                            Set_Addr_To = aIOA;
1689 2 ghutchis
                          end
1690
 
1691 24 ghutchis
                        MCycle[2] :
1692 2 ghutchis
                          begin
1693 24 ghutchis
                            Read_To_Acc = 1'b1;
1694
                            IORQ = 1'b1;
1695 2 ghutchis
                          end
1696
 
1697 24 ghutchis
                        default :;
1698
                      endcase
1699
                    end // if (Mode != 3 )
1700 2 ghutchis
                end // case: 8'b11011011
1701
 
1702 24 ghutchis
              8'b11010011  :
1703 2 ghutchis
                begin
1704 24 ghutchis
                  if (Mode != 3 )
1705 2 ghutchis
                    begin
1706 24 ghutchis
                      // OUT (n),A
1707
                      MCycles = 3'b011;
1708
                      case (1'b1) // MCycle
1709
                        MCycle[1] :
1710 2 ghutchis
                          begin
1711 24 ghutchis
                            Inc_PC = 1'b1;
1712
                            Set_Addr_To = aIOA;
1713
                            Set_BusB_To = 4'b0111;
1714 2 ghutchis
                          end
1715
 
1716 24 ghutchis
                        MCycle[2] :
1717 2 ghutchis
                          begin
1718 24 ghutchis
                            Write = 1'b1;
1719
                            IORQ = 1'b1;
1720 2 ghutchis
                          end
1721
 
1722 24 ghutchis
                        default :;
1723
                      endcase
1724
                    end // if (Mode != 3 )
1725 2 ghutchis
                end // case: 8'b11010011
1726
 
1727
 
1728 24 ghutchis
              //----------------------------------------------------------------------------
1729
              //----------------------------------------------------------------------------
1730
              // MULTIBYTE INSTRUCTIONS
1731
              //----------------------------------------------------------------------------
1732
              //----------------------------------------------------------------------------
1733 2 ghutchis
 
1734 24 ghutchis
              8'b11001011  :
1735 2 ghutchis
                begin
1736 24 ghutchis
                  if (Mode != 2 )
1737 2 ghutchis
                    begin
1738 24 ghutchis
                      Prefix = 2'b01;
1739
                    end
1740 2 ghutchis
                end
1741
 
1742 24 ghutchis
              8'b11101101  :
1743 2 ghutchis
                begin
1744 24 ghutchis
                  if (Mode < 2 )
1745 2 ghutchis
                    begin
1746 24 ghutchis
                      Prefix = 2'b10;
1747
                    end
1748 2 ghutchis
                end
1749
 
1750 24 ghutchis
              8'b11011101,8'b11111101  :
1751 2 ghutchis
                begin
1752 24 ghutchis
                  if (Mode < 2 )
1753 2 ghutchis
                    begin
1754 24 ghutchis
                      Prefix = 2'b11;
1755
                    end
1756 2 ghutchis
                end
1757
 
1758 80 ghutchis
            endcase // case(IR)
1759 2 ghutchis
          end // case: 2'b00
1760
 
1761
 
1762 24 ghutchis
        2'b01  :
1763 2 ghutchis
          begin
1764
 
1765
 
1766
            //----------------------------------------------------------------------------
1767
            //
1768 24 ghutchis
            //  CB prefixed instructions
1769 2 ghutchis
            //
1770
            //----------------------------------------------------------------------------
1771
 
1772 24 ghutchis
            Set_BusA_To[2:0] = IR[2:0];
1773
            Set_BusB_To[2:0] = IR[2:0];
1774 2 ghutchis
 
1775 90 ghutchis
            casez (IR)
1776 24 ghutchis
              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
1777
              8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
1778
              8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
1779
              8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
1780
              8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
1781
              8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111,
1782
              8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111,
1783
              8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 :
1784 2 ghutchis
                begin
1785 24 ghutchis
                  // RLC r
1786
                  // RL r
1787
                  // RRC r
1788
                  // RR r
1789
                  // SLA r
1790
                  // SRA r
1791
                  // SRL r
1792
                  // SLL r (Undocumented) / SWAP r
1793
                  if (MCycle[0] ) begin
1794
                    ALU_Op = 4'b1000;
1795
                    Read_To_Reg = 1'b1;
1796
                    Save_ALU = 1'b1;
1797
                  end
1798 2 ghutchis
                end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
1799
 
1800 90 ghutchis
              8'b00zzz110  :
1801 2 ghutchis
                begin
1802 24 ghutchis
                  // RLC (HL)
1803
                  // RL (HL)
1804
                  // RRC (HL)
1805
                  // RR (HL)
1806
                  // SRA (HL)
1807
                  // SRL (HL)
1808
                  // SLA (HL)
1809
                  // SLL (HL) (Undocumented) / SWAP (HL)
1810
                  MCycles = 3'b011;
1811
                  case (1'b1) // MCycle
1812 23 ghutchis
                    MCycle[0], MCycle[6] :
1813 24 ghutchis
                      Set_Addr_To = aXY;
1814
                    MCycle[1] :
1815 2 ghutchis
                      begin
1816 24 ghutchis
                        ALU_Op = 4'b1000;
1817
                        Read_To_Reg = 1'b1;
1818
                        Save_ALU = 1'b1;
1819
                        Set_Addr_To = aXY;
1820
                        TStates = 3'b100;
1821 2 ghutchis
                      end
1822
 
1823 24 ghutchis
                    MCycle[2] :
1824
                      Write = 1'b1;
1825
                    default :;
1826
                  endcase // case(MCycle)
1827 2 ghutchis
                end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
1828
 
1829 24 ghutchis
              8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
1830
                  8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
1831
                  8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
1832
                  8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
1833
                  8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
1834
                  8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
1835
                  8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
1836
                  8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
1837 2 ghutchis
                    begin
1838 24 ghutchis
                      // BIT b,r
1839
                      if (MCycle[0] )
1840 2 ghutchis
                        begin
1841
                          Set_BusB_To[2:0] = IR[2:0];
1842 24 ghutchis
                          ALU_Op = 4'b1001;
1843
                        end
1844 2 ghutchis
                    end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
1845
 
1846 24 ghutchis
              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110  :
1847 2 ghutchis
                begin
1848 24 ghutchis
                  // BIT b,(HL)
1849
                  MCycles = 3'b010;
1850
                  case (1'b1) // MCycle
1851 23 ghutchis
                    MCycle[0], MCycle[6] :
1852 24 ghutchis
                      Set_Addr_To = aXY;
1853
                    MCycle[1] :
1854 2 ghutchis
                      begin
1855 24 ghutchis
                        ALU_Op = 4'b1001;
1856
                        TStates = 3'b100;
1857 2 ghutchis
                      end
1858
 
1859 24 ghutchis
                    default :;
1860
                  endcase // case(MCycle)
1861 2 ghutchis
                end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110
1862
 
1863 24 ghutchis
              8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,
1864
                  8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111,
1865
                  8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111,
1866
                  8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111,
1867
                  8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111,
1868
                  8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
1869
                  8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
1870
                  8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
1871 2 ghutchis
                    begin
1872 24 ghutchis
                      // SET b,r
1873
                      if (MCycle[0] )
1874 2 ghutchis
                        begin
1875 24 ghutchis
                          ALU_Op = 4'b1010;
1876
                          Read_To_Reg = 1'b1;
1877
                          Save_ALU = 1'b1;
1878
                        end
1879 2 ghutchis
                    end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,...
1880
 
1881 24 ghutchis
              8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110  :
1882 2 ghutchis
                begin
1883 24 ghutchis
                  // SET b,(HL)
1884
                  MCycles = 3'b011;
1885
                  case (1'b1) // MCycle
1886 23 ghutchis
                    MCycle[0], MCycle[6] :
1887 24 ghutchis
                      Set_Addr_To = aXY;
1888
                    MCycle[1] :
1889 2 ghutchis
                      begin
1890 24 ghutchis
                        ALU_Op = 4'b1010;
1891
                        Read_To_Reg = 1'b1;
1892
                        Save_ALU = 1'b1;
1893
                        Set_Addr_To = aXY;
1894
                        TStates = 3'b100;
1895 2 ghutchis
                      end
1896 24 ghutchis
                    MCycle[2] :
1897
                      Write = 1'b1;
1898
                    default :;
1899
                  endcase // case(MCycle)
1900 2 ghutchis
                end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
1901
 
1902 24 ghutchis
              8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
1903
                  8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
1904
                  8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
1905
                  8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
1906
                  8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
1907
                  8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
1908
                  8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
1909
                  8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
1910 2 ghutchis
                    begin
1911 24 ghutchis
                      // RES b,r
1912
                      if (MCycle[0] )
1913 2 ghutchis
                        begin
1914 24 ghutchis
                          ALU_Op = 4'b1011;
1915
                          Read_To_Reg = 1'b1;
1916
                          Save_ALU = 1'b1;
1917
                        end
1918 2 ghutchis
                    end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
1919
 
1920 24 ghutchis
              8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110  :
1921 2 ghutchis
                begin
1922 24 ghutchis
                  // RES b,(HL)
1923
                  MCycles = 3'b011;
1924
                  case (1'b1) // MCycle
1925 23 ghutchis
                    MCycle[0], MCycle[6] :
1926 24 ghutchis
                      Set_Addr_To = aXY;
1927
                    MCycle[1] :
1928 2 ghutchis
                      begin
1929 24 ghutchis
                        ALU_Op = 4'b1011;
1930
                        Read_To_Reg = 1'b1;
1931
                        Save_ALU = 1'b1;
1932
                        Set_Addr_To = aXY;
1933
                        TStates = 3'b100;
1934 2 ghutchis
                      end
1935
 
1936 24 ghutchis
                    MCycle[2] :
1937
                      Write = 1'b1;
1938
                    default :;
1939
                  endcase // case(MCycle)
1940 2 ghutchis
                end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
1941
 
1942 80 ghutchis
            endcase // case(IR)
1943 2 ghutchis
          end // case: 2'b01
1944
 
1945 24 ghutchis
 
1946
        default :
1947
          begin : default_ed_block
1948 2 ghutchis
 
1949
            //----------------------------------------------------------------------------
1950
            //
1951 24 ghutchis
            //  ED prefixed instructions
1952 2 ghutchis
            //
1953
            //----------------------------------------------------------------------------
1954
 
1955 90 ghutchis
            casez (IR)
1956 80 ghutchis
              /*
1957
               * Undocumented NOP instructions commented out to reduce size of mcode
1958
               *
1959 24 ghutchis
              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
1960
                ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
1961
                  ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111
1962
                    ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111
1963
                      ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111
1964
                        ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111
1965
                          ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111
1966
                            ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111
1967
 
1968 2 ghutchis
 
1969 24 ghutchis
                              ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111
1970
                                ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111
1971
                                  ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111
1972
                                    ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111
1973
                                      ,                                            8'b10100100,8'b10100101,8'b10100110,8'b10100111
1974
                                        ,                                            8'b10101100,8'b10101101,8'b10101110,8'b10101111
1975
                                          ,                                            8'b10110100,8'b10110101,8'b10110110,8'b10110111
1976
                                            ,                                            8'b10111100,8'b10111101,8'b10111110,8'b10111111
1977
                                              ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111
1978
                                                ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111
1979
                                                  ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111
1980
                                                    ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111
1981
                                                      ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111
1982
                                                        ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111
1983
                                                          ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111
1984
                                                            ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 :
1985
                                                              ; // NOP, undocumented
1986
 
1987
              8'b01111110,8'b01111111  :
1988
                // NOP, undocumented
1989
                ;
1990 80 ghutchis
               */
1991
 
1992 24 ghutchis
              // 8 BIT LOAD GROUP
1993
              8'b01010111  :
1994
                begin
1995
                  // LD A,I
1996
                  Special_LD = 3'b100;
1997
                  TStates = 3'b101;
1998
                end
1999
 
2000
              8'b01011111  :
2001
                begin
2002
                  // LD A,R
2003
                  Special_LD = 3'b101;
2004
                  TStates = 3'b101;
2005
                end
2006
 
2007
              8'b01000111  :
2008
                begin
2009
                  // LD I,A
2010
                  Special_LD = 3'b110;
2011
                  TStates = 3'b101;
2012
                end
2013
 
2014
              8'b01001111  :
2015
                begin
2016
                  // LD R,A
2017
                  Special_LD = 3'b111;
2018
                  TStates = 3'b101;
2019
                end
2020
 
2021
              // 16 BIT LOAD GROUP
2022
              8'b01001011,8'b01011011,8'b01101011,8'b01111011  :
2023
                begin
2024
                  // LD dd,(nn)
2025
                  MCycles = 3'b101;
2026
                  case (1'b1) // MCycle
2027
                    MCycle[1] :
2028
                      begin
2029
                        Inc_PC = 1'b1;
2030
                        LDZ = 1'b1;
2031
                      end
2032
 
2033
                    MCycle[2] :
2034
                      begin
2035
                        Set_Addr_To = aZI;
2036
                        Inc_PC = 1'b1;
2037
                        LDW = 1'b1;
2038
                      end
2039
 
2040
                    MCycle[3] :
2041
                      begin
2042
                        Read_To_Reg = 1'b1;
2043
                        if (IR[5:4] == 2'b11 )
2044 2 ghutchis
                          begin
2045 24 ghutchis
                            Set_BusA_To = 4'b1000;
2046
                          end
2047
                        else
2048 2 ghutchis
                          begin
2049 24 ghutchis
                            Set_BusA_To[2:1] = IR[5:4];
2050
                            Set_BusA_To[0] = 1'b1;
2051 2 ghutchis
                          end
2052 24 ghutchis
                        Inc_WZ = 1'b1;
2053
                        Set_Addr_To = aZI;
2054
                      end // case: 4
2055
 
2056
                    MCycle[4] :
2057
                      begin
2058
                        Read_To_Reg = 1'b1;
2059
                        if (IR[5:4] == 2'b11 )
2060 2 ghutchis
                          begin
2061 24 ghutchis
                            Set_BusA_To = 4'b1001;
2062
                          end
2063
                        else
2064 2 ghutchis
                          begin
2065 24 ghutchis
                            Set_BusA_To[2:1] = IR[5:4];
2066
                            Set_BusA_To[0] = 1'b0;
2067 2 ghutchis
                          end
2068 24 ghutchis
                      end // case: 5
2069
 
2070
                    default :;
2071
                  endcase // case(MCycle)
2072
                end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011
2073
 
2074
 
2075
              8'b01000011,8'b01010011,8'b01100011,8'b01110011  :
2076
                begin
2077
                  // LD (nn),dd
2078
                  MCycles = 3'b101;
2079
                  case (1'b1) // MCycle
2080
                    MCycle[1] :
2081
                      begin
2082
                        Inc_PC = 1'b1;
2083
                        LDZ = 1'b1;
2084
                      end
2085
 
2086
                    MCycle[2] :
2087
                      begin
2088
                        Set_Addr_To = aZI;
2089
                        Inc_PC = 1'b1;
2090
                        LDW = 1'b1;
2091
                        if (IR[5:4] == 2'b11 )
2092 2 ghutchis
                          begin
2093 24 ghutchis
                            Set_BusB_To = 4'b1000;
2094
                          end
2095
                        else
2096 2 ghutchis
                          begin
2097 24 ghutchis
                            Set_BusB_To[2:1] = IR[5:4];
2098
                            Set_BusB_To[0] = 1'b1;
2099
                            Set_BusB_To[3] = 1'b0;
2100 2 ghutchis
                          end
2101 24 ghutchis
                      end // case: 3
2102
 
2103
                    MCycle[3] :
2104
                      begin
2105
                        Inc_WZ = 1'b1;
2106
                        Set_Addr_To = aZI;
2107
                        Write = 1'b1;
2108
                        if (IR[5:4] == 2'b11 )
2109 2 ghutchis
                          begin
2110 24 ghutchis
                            Set_BusB_To = 4'b1001;
2111
                          end
2112
                        else
2113 2 ghutchis
                          begin
2114 24 ghutchis
                            Set_BusB_To[2:1] = IR[5:4];
2115
                            Set_BusB_To[0] = 1'b0;
2116
                            Set_BusB_To[3] = 1'b0;
2117 2 ghutchis
                          end
2118 24 ghutchis
                      end // case: 4
2119
 
2120
                    MCycle[4] :
2121
                      begin
2122
                        Write = 1'b1;
2123
                      end
2124
 
2125
                    default :;
2126
                  endcase // case(MCycle)
2127
                end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011
2128
 
2129
              8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000  :
2130
                begin
2131
                  // LDI, LDD, LDIR, LDDR
2132
                  MCycles = 3'b100;
2133
                  case (1'b1) // MCycle
2134
                    MCycle[0] :
2135
                      begin
2136
                        Set_Addr_To = aXY;
2137
                        IncDec_16 = 4'b1100; // BC
2138
                      end
2139
 
2140
                    MCycle[1] :
2141
                      begin
2142
                        Set_BusB_To = 4'b0110;
2143
                        Set_BusA_To[2:0] = 3'b111;
2144
                        ALU_Op = 4'b0000;
2145
                        Set_Addr_To = aDE;
2146
                        if (IR[3] == 1'b0 )
2147 2 ghutchis
                          begin
2148 24 ghutchis
                            IncDec_16 = 4'b0110; // IX
2149
                          end
2150
                        else
2151 2 ghutchis
                          begin
2152 24 ghutchis
                            IncDec_16 = 4'b1110;
2153 2 ghutchis
                          end
2154 24 ghutchis
                      end // case: 2
2155
 
2156
                    MCycle[2] :
2157
                      begin
2158
                        I_BT = 1'b1;
2159
                        TStates = 3'b101;
2160
                        Write = 1'b1;
2161
                        if (IR[3] == 1'b0 )
2162 2 ghutchis
                          begin
2163 24 ghutchis
                            IncDec_16 = 4'b0101; // DE
2164
                          end
2165
                        else
2166 2 ghutchis
                          begin
2167 24 ghutchis
                            IncDec_16 = 4'b1101;
2168 2 ghutchis
                          end
2169 24 ghutchis
                      end // case: 3
2170
 
2171
                    MCycle[3] :
2172
                      begin
2173
                        NoRead = 1'b1;
2174
                        TStates = 3'b101;
2175
                      end
2176
 
2177
                    default :;
2178
                  endcase // case(MCycle)
2179
                end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000
2180
 
2181
              8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001  :
2182
                begin
2183
                  // CPI, CPD, CPIR, CPDR
2184
                  MCycles = 3'b100;
2185
                  case (1'b1) // MCycle
2186
                    MCycle[0] :
2187
                      begin
2188
                        Set_Addr_To = aXY;
2189
                        IncDec_16 = 4'b1100; // BC
2190
                      end
2191
 
2192
                    MCycle[1] :
2193
                      begin
2194
                        Set_BusB_To = 4'b0110;
2195
                        Set_BusA_To[2:0] = 3'b111;
2196
                        ALU_Op = 4'b0111;
2197
                        Save_ALU = 1'b1;
2198
                        PreserveC = 1'b1;
2199
                        if (IR[3] == 1'b0 )
2200 2 ghutchis
                          begin
2201 24 ghutchis
                            IncDec_16 = 4'b0110;
2202
                          end
2203
                        else
2204 2 ghutchis
                          begin
2205 24 ghutchis
                            IncDec_16 = 4'b1110;
2206 2 ghutchis
                          end
2207 24 ghutchis
                      end // case: 2
2208
 
2209
                    MCycle[2] :
2210
                      begin
2211
                        NoRead = 1'b1;
2212
                        I_BC = 1'b1;
2213
                        TStates = 3'b101;
2214
                      end
2215
 
2216
                    MCycle[3] :
2217
                      begin
2218
                        NoRead = 1'b1;
2219
                        TStates = 3'b101;
2220
                      end
2221
 
2222
                    default :;
2223
                  endcase // case(MCycle)
2224
                end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001
2225
 
2226
              8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100  :
2227
                begin
2228
                  // NEG
2229
                  ALU_Op = 4'b0010;
2230
                  Set_BusB_To = 4'b0111;
2231
                  Set_BusA_To = 4'b1010;
2232
                  Read_To_Acc = 1'b1;
2233
                  Save_ALU = 1'b1;
2234
                end
2235
 
2236
              8'b01000110,8'b01001110,8'b01100110,8'b01101110  :
2237
                begin
2238
                  // IM 0
2239
                  IMode = 2'b00;
2240
                end
2241
 
2242
              8'b01010110,8'b01110110  :
2243
                // IM 1
2244
                IMode = 2'b01;
2245
 
2246
              8'b01011110,8'b01110111  :
2247
                // IM 2
2248
                IMode = 2'b10;
2249
 
2250
              // 16 bit arithmetic
2251
              8'b01001010,8'b01011010,8'b01101010,8'b01111010  :
2252
                begin
2253
                  // ADC HL,ss
2254
                  MCycles = 3'b011;
2255
                  case (1'b1) // MCycle
2256
                    MCycle[1] :
2257
                      begin
2258
                        NoRead = 1'b1;
2259
                        ALU_Op = 4'b0001;
2260
                        Read_To_Reg = 1'b1;
2261
                        Save_ALU = 1'b1;
2262
                        Set_BusA_To[2:0] = 3'b101;
2263
                        case (IR[5:4])
2264
                          0,1,2  :
2265
                            begin
2266
                              Set_BusB_To[2:1] = IR[5:4];
2267
                              Set_BusB_To[0] = 1'b1;
2268
                            end
2269
                          default :
2270
                            Set_BusB_To = 4'b1000;
2271
                        endcase
2272
                        TStates = 3'b100;
2273
                      end // case: 2
2274
 
2275
                    MCycle[2] :
2276
                      begin
2277
                        NoRead = 1'b1;
2278
                        Read_To_Reg = 1'b1;
2279
                        Save_ALU = 1'b1;
2280
                        ALU_Op = 4'b0001;
2281
                        Set_BusA_To[2:0] = 3'b100;
2282
                        case (IR[5:4])
2283
                          0,1,2  :
2284
                            begin
2285
                              Set_BusB_To[2:1] = IR[5:4];
2286
                              Set_BusB_To[0] = 1'b0;
2287
                            end
2288
                          default :
2289
                            Set_BusB_To = 4'b1001;
2290
                        endcase // case(IR[5:4])
2291
                      end // case: 3
2292
 
2293
                    default :;
2294
                  endcase // case(MCycle)
2295
                end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010
2296
 
2297
              8'b01000010,8'b01010010,8'b01100010,8'b01110010  :
2298
                begin
2299
                  // SBC HL,ss
2300
                  MCycles = 3'b011;
2301
                  case (1'b1) // MCycle
2302
                    MCycle[1] :
2303
                      begin
2304
                        NoRead = 1'b1;
2305
                        ALU_Op = 4'b0011;
2306
                        Read_To_Reg = 1'b1;
2307
                        Save_ALU = 1'b1;
2308
                        Set_BusA_To[2:0] = 3'b101;
2309
                        case (IR[5:4])
2310
                          0,1,2  :
2311
                            begin
2312
                              Set_BusB_To[2:1] = IR[5:4];
2313
                              Set_BusB_To[0] = 1'b1;
2314
                            end
2315
                          default :
2316
                            Set_BusB_To = 4'b1000;
2317
                        endcase
2318
                        TStates = 3'b100;
2319
                      end // case: 2
2320
 
2321
                    MCycle[2] :
2322
                      begin
2323
                        NoRead = 1'b1;
2324
                        ALU_Op = 4'b0011;
2325
                        Read_To_Reg = 1'b1;
2326
                        Save_ALU = 1'b1;
2327
                        Set_BusA_To[2:0] = 3'b100;
2328
                        case (IR[5:4])
2329
                          0,1,2  :
2330
                            Set_BusB_To[2:1] = IR[5:4];
2331
                          default :
2332
                            Set_BusB_To = 4'b1001;
2333
                        endcase
2334
                      end // case: 3
2335
 
2336
                    default :;
2337
 
2338
                  endcase // case(MCycle)
2339
                end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010
2340
 
2341
              8'b01101111  :
2342
                begin
2343
                  // RLD
2344
                  MCycles = 3'b100;
2345
                  case (1'b1) // MCycle
2346
                    MCycle[1] :
2347
                      begin
2348
                        NoRead = 1'b1;
2349
                        Set_Addr_To = aXY;
2350
                      end
2351
 
2352
                    MCycle[2] :
2353
                      begin
2354
                        Read_To_Reg = 1'b1;
2355
                        Set_BusB_To[2:0] = 3'b110;
2356
                        Set_BusA_To[2:0] = 3'b111;
2357
                        ALU_Op = 4'b1101;
2358
                        TStates = 3'b100;
2359
                        Set_Addr_To = aXY;
2360
                        Save_ALU = 1'b1;
2361
                      end
2362
 
2363
                    MCycle[3] :
2364
                      begin
2365
                        I_RLD = 1'b1;
2366
                        Write = 1'b1;
2367
                      end
2368
 
2369
                    default :;
2370
                  endcase // case(MCycle)
2371
                end // case: 8'b01101111
2372
 
2373
              8'b01100111  :
2374
                begin
2375
                  // RRD
2376
                  MCycles = 3'b100;
2377
                  case (1'b1) // MCycle
2378
                    MCycle[1] :
2379
                      Set_Addr_To = aXY;
2380
                    MCycle[2] :
2381
                      begin
2382
                        Read_To_Reg = 1'b1;
2383
                        Set_BusB_To[2:0] = 3'b110;
2384
                        Set_BusA_To[2:0] = 3'b111;
2385
                        ALU_Op = 4'b1110;
2386
                        TStates = 3'b100;
2387
                        Set_Addr_To = aXY;
2388
                        Save_ALU = 1'b1;
2389
                      end
2390
 
2391
                    MCycle[3] :
2392
                      begin
2393
                        I_RRD = 1'b1;
2394
                        Write = 1'b1;
2395
                      end
2396
 
2397
                    default :;
2398
                  endcase // case(MCycle)
2399
                end // case: 8'b01100111
2400
 
2401
              8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101  :
2402
                begin
2403
                  // RETI, RETN
2404
                  MCycles = 3'b011;
2405
                  case (1'b1) // MCycle
2406
                    MCycle[0] :
2407
                      Set_Addr_To = aSP;
2408
 
2409
                    MCycle[1] :
2410
                      begin
2411
                        IncDec_16 = 4'b0111;
2412
                        Set_Addr_To = aSP;
2413
                        LDZ = 1'b1;
2414
                      end
2415
 
2416
                    MCycle[2] :
2417
                      begin
2418
                        Jump = 1'b1;
2419
                        IncDec_16 = 4'b0111;
2420
                        I_RETN = 1'b1;
2421
                      end
2422
 
2423
                    default :;
2424
                  endcase // case(MCycle)
2425
                end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101
2426
 
2427
              8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000  :
2428
                begin
2429
                  // IN r,(C)
2430
                  MCycles = 3'b010;
2431
                  case (1'b1) // MCycle
2432
                    MCycle[0] :
2433
                      Set_Addr_To = aBC;
2434
 
2435
                    MCycle[1] :
2436
                      begin
2437
                        IORQ = 1'b1;
2438
                        if (IR[5:3] != 3'b110 )
2439 2 ghutchis
                          begin
2440 24 ghutchis
                            Read_To_Reg = 1'b1;
2441
                            Set_BusA_To[2:0] = IR[5:3];
2442 2 ghutchis
                          end
2443 24 ghutchis
                        I_INRC = 1'b1;
2444
                      end
2445
 
2446
                    default :;
2447
                  endcase // case(MCycle)
2448
                end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000
2449
 
2450
              8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001  :
2451
                begin
2452
                  // OUT (C),r
2453
                  // OUT (C),0
2454
                  MCycles = 3'b010;
2455
                  case (1'b1) // MCycle
2456
                    MCycle[0] :
2457
                      begin
2458
                        Set_Addr_To = aBC;
2459
                        Set_BusB_To[2:0]        = IR[5:3];
2460
                        if (IR[5:3] == 3'b110 )
2461 2 ghutchis
                          begin
2462 24 ghutchis
                            Set_BusB_To[3] = 1'b1;
2463 2 ghutchis
                          end
2464 24 ghutchis
                      end
2465
 
2466
                    MCycle[1] :
2467
                      begin
2468
                        Write = 1'b1;
2469
                        IORQ = 1'b1;
2470
                      end
2471
 
2472
                    default :;
2473
                  endcase // case(MCycle)
2474
                end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001
2475
 
2476
              8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010  :
2477
                begin
2478
                  // INI, IND, INIR, INDR
2479
                  MCycles = 3'b100;
2480
                  case (1'b1) // MCycle
2481
                    MCycle[0] :
2482
                      begin
2483
                        Set_Addr_To = aBC;
2484
                        Set_BusB_To = 4'b1010;
2485
                        Set_BusA_To = 4'b0000;
2486
                        Read_To_Reg = 1'b1;
2487
                        Save_ALU = 1'b1;
2488
                        ALU_Op = 4'b0010;
2489
                      end
2490
 
2491
                    MCycle[1] :
2492
                      begin
2493
                        IORQ = 1'b1;
2494
                        Set_BusB_To = 4'b0110;
2495
                        Set_Addr_To = aXY;
2496
                      end
2497
 
2498
                    MCycle[2] :
2499
                      begin
2500
                        if (IR[3] == 1'b0 )
2501 2 ghutchis
                          begin
2502 24 ghutchis
                            IncDec_16 = 4'b0110;
2503
                          end
2504
                        else
2505 2 ghutchis
                          begin
2506 24 ghutchis
                            IncDec_16 = 4'b1110;
2507 2 ghutchis
                          end
2508 24 ghutchis
                        TStates = 3'b100;
2509
                        Write = 1'b1;
2510
                        I_BTR = 1'b1;
2511
                      end // case: 3
2512
 
2513
                    MCycle[3] :
2514
                      begin
2515
                        NoRead = 1'b1;
2516
                        TStates = 3'b101;
2517
                      end
2518
 
2519
                    default :;
2520
                  endcase // case(MCycle)
2521
                end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010
2522
 
2523
              8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011  :
2524
                begin
2525
                  // OUTI, OUTD, OTIR, OTDR
2526
                  MCycles = 3'b100;
2527
                  case (1'b1) // MCycle
2528
                    MCycle[0] :
2529
                      begin
2530
                        TStates = 3'b101;
2531
                        Set_Addr_To = aXY;
2532
                        Set_BusB_To = 4'b1010;
2533
                        Set_BusA_To = 4'b0000;
2534
                        Read_To_Reg = 1'b1;
2535
                        Save_ALU = 1'b1;
2536
                        ALU_Op = 4'b0010;
2537
                      end
2538
 
2539
                    MCycle[1] :
2540
                      begin
2541
                        Set_BusB_To = 4'b0110;
2542
                        Set_Addr_To = aBC;
2543 33 ghutchis
                        if (IR[3] == 1'b0 )
2544
                          begin
2545
                            IncDec_16 = 4'b0110;
2546
                          end
2547
                        else
2548
                          begin
2549
                            IncDec_16 = 4'b1110;
2550
                          end
2551 24 ghutchis
                      end
2552
 
2553
                    MCycle[2] :
2554
                      begin
2555
                        if (IR[3] == 1'b0 )
2556 2 ghutchis
                          begin
2557 33 ghutchis
                            IncDec_16 = 4'b0010;
2558 24 ghutchis
                          end
2559
                        else
2560 2 ghutchis
                          begin
2561 33 ghutchis
                            IncDec_16 = 4'b1010;
2562 2 ghutchis
                          end
2563 24 ghutchis
                        IORQ = 1'b1;
2564
                        Write = 1'b1;
2565
                        I_BTR = 1'b1;
2566
                      end // case: 3
2567
 
2568
                    MCycle[3] :
2569
                      begin
2570
                        NoRead = 1'b1;
2571
                        TStates = 3'b101;
2572
                      end
2573
 
2574
                    default :;
2575
                  endcase // case(MCycle)
2576
                end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
2577 90 ghutchis
 
2578
              default : ;
2579 24 ghutchis
 
2580 80 ghutchis
            endcase // case(IR)                  
2581 2 ghutchis
          end // block: default_ed_block        
2582
      endcase // case(ISet)
2583 24 ghutchis
 
2584 2 ghutchis
      if (Mode == 1 )
2585
        begin
2586 24 ghutchis
          if (MCycle[0] )
2587 2 ghutchis
            begin
2588
              //TStates = 3'b100;
2589 24 ghutchis
            end
2590 2 ghutchis
          else
2591
            begin
2592 24 ghutchis
              TStates = 3'b011;
2593
            end
2594
        end
2595 2 ghutchis
 
2596
      if (Mode == 3 )
2597
        begin
2598 24 ghutchis
          if (MCycle[0] )
2599 2 ghutchis
            begin
2600 24 ghutchis
              //TStates = 3'b100;
2601
            end
2602 2 ghutchis
          else
2603
            begin
2604 24 ghutchis
              TStates = 3'b100;
2605
            end
2606
        end
2607 2 ghutchis
 
2608
      if (Mode < 2 )
2609
        begin
2610 24 ghutchis
          if (MCycle[5] )
2611 2 ghutchis
            begin
2612 24 ghutchis
              Inc_PC = 1'b1;
2613
              if (Mode == 1 )
2614 2 ghutchis
                begin
2615 24 ghutchis
                  Set_Addr_To = aXY;
2616
                  TStates = 3'b100;
2617
                  Set_BusB_To[2:0] = SSS;
2618
                  Set_BusB_To[3] = 1'b0;
2619
                end
2620 80 ghutchis
              if (IR == 8'b00110110 || IR == 8'b11001011 )
2621 2 ghutchis
                begin
2622 24 ghutchis
                  Set_Addr_To = aNone;
2623
                end
2624
            end
2625
          if (MCycle[6] )
2626 2 ghutchis
            begin
2627 24 ghutchis
              if (Mode == 0 )
2628 2 ghutchis
                begin
2629 24 ghutchis
                  TStates = 3'b101;
2630
                end
2631
              if (ISet != 2'b01 )
2632 2 ghutchis
                begin
2633 24 ghutchis
                  Set_Addr_To = aXY;
2634
                end
2635
              Set_BusB_To[2:0] = SSS;
2636
              Set_BusB_To[3] = 1'b0;
2637 80 ghutchis
              if (IR == 8'b00110110 || ISet == 2'b01 )
2638 2 ghutchis
                begin
2639 24 ghutchis
                  // LD (HL),n
2640
                  Inc_PC = 1'b1;
2641
                end
2642 2 ghutchis
              else
2643
                begin
2644 24 ghutchis
                  NoRead = 1'b1;
2645
                end
2646
            end
2647
        end // if (Mode < 2 )      
2648 2 ghutchis
 
2649
    end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
2650
endmodule // T80_MCode

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