Subversion Repositories tv80

//

// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)

//

// Permission is hereby granted, free of charge, to any person obtaining a 

// copy of this software and associated documentation files (the "Software"), 

// to deal in the Software without restriction, including without limitation 

// the rights to use, copy, modify, merge, publish, distribute, sublicense, 

// and/or sell copies of the Software, and to permit persons to whom the 

// Software is furnished to do so, subject to the following conditions:

//

// The above copyright notice and this permission notice shall be included 

// in all copies or substantial portions of the Software.

//

// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 

// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 

// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 

// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 

// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 

// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 

// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

// Simple wrapper for a clock synchronizer

//

// The following code can (should) be replaced with metastability-hardened

// flops from your technology library.

module sync2

  ( input     clk,

    input     data_in,

    output    data_out );

  reg         sync_ff1, sync_ff2;

  always @(posedge clk)

    begin

      sync_ff1 <= #1 data_in;

      sync_ff2 <= #1 sync_ff1;

    end

  assign data_out = sync_ff2;

endmodule // sync2