OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [sc_env/] [sc_env_top.cpp] - Blame information for rev 113

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 91 ghutchis
#include "systemc.h"
2 94 ghutchis
#include "systemperl.h"
3 91 ghutchis
#include "env_memory.h"
4 92 ghutchis
#include "tv_responder.h"
5 91 ghutchis
#include "Vtv80s.h"
6 97 ghutchis
#include "VT16450.h"
7 94 ghutchis
#include "SpTraceVcd.h"
8 95 ghutchis
#include <unistd.h>
9 96 ghutchis
#include "z80_decoder.h"
10 97 ghutchis
#include "di_mux.h"
11 91 ghutchis
 
12 95 ghutchis
extern char *optarg;
13
extern int optind, opterr, optopt;
14
 
15 98 ghutchis
#define FILENAME_SZ 80
16
 
17 91 ghutchis
int sc_main(int argc, char *argv[])
18
{
19 95 ghutchis
        bool dumping = false;
20
        bool memfile = false;
21
        int index;
22 98 ghutchis
        char dumpfile_name[FILENAME_SZ];
23
        char mem_src_name[FILENAME_SZ];
24 95 ghutchis
        SpTraceFile *tfp;
25 96 ghutchis
    z80_decoder dec0 ("dec0");
26 95 ghutchis
 
27
        sc_clock clk("clk125", 8, SC_NS, 0.5);
28 91 ghutchis
 
29
        sc_signal<bool> reset_n;
30
        sc_signal<bool> wait_n;
31
        sc_signal<bool> int_n;
32
        sc_signal<bool> nmi_n;
33
        sc_signal<bool> busrq_n;
34
        sc_signal<bool> m1_n;
35
        sc_signal<bool> mreq_n;
36
        sc_signal<bool> iorq_n;
37
        sc_signal<bool> rd_n;
38
        sc_signal<bool> wr_n;
39
        sc_signal<bool> rfsh_n;
40
        sc_signal<bool> halt_n;
41
        sc_signal<bool> busak_n;
42
        sc_signal<uint32_t>     di;
43 92 ghutchis
        sc_signal<uint32_t> di_mem;
44
        sc_signal<uint32_t> di_resp;
45 97 ghutchis
        sc_signal<uint32_t> di_uart;
46 91 ghutchis
        sc_signal<uint32_t>     dout;
47
        sc_signal<uint32_t>     addr;
48
 
49 97 ghutchis
    sc_signal<bool> uart_cs_n, serial, cts_n, dsr_n, ri_n, dcd_n;
50
    sc_signal<bool> baudout, uart_int;
51
 
52
        while ( (index = getopt(argc, argv, "d:i:k")) != -1) {
53
                printf ("DEBUG: getopt optind=%d index=%d char=%c\n", optind, index, (char) index);
54
                if  (index == 'd') {
55 98 ghutchis
                        strncpy (dumpfile_name, optarg, FILENAME_SZ);
56 97 ghutchis
                        dumping = true;
57
                        printf ("VCD dump enabled to %s\n", dumpfile_name);
58
                } else if (index == 'i') {
59 98 ghutchis
                        strncpy (mem_src_name, optarg, FILENAME_SZ);
60 97 ghutchis
                        memfile = true;
61
                } else if (index == 'k') {
62
                        printf ("Z80 Instruction decode enabled\n");
63
                        dec0.en_decode = true;
64
                }
65
        }
66
 
67 91 ghutchis
        Vtv80s tv80s ("tv80s");
68
        tv80s.A (addr);
69
        tv80s.reset_n (reset_n);
70
        tv80s.clk (clk);
71
        tv80s.wait_n (wait_n);
72
        tv80s.int_n (int_n);
73
        tv80s.nmi_n (nmi_n);
74
        tv80s.busrq_n (busrq_n);
75
        tv80s.m1_n (m1_n);
76
        tv80s.mreq_n (mreq_n);
77
        tv80s.iorq_n (iorq_n);
78
        tv80s.rd_n (rd_n);
79
        tv80s.wr_n (wr_n);
80
        tv80s.rfsh_n (rfsh_n);
81
        tv80s.halt_n (halt_n);
82
        tv80s.busak_n (busak_n);
83
        tv80s.di (di);
84
        tv80s.dout (dout);
85
 
86 97 ghutchis
        di_mux di_mux0("di_mux0");
87
        di_mux0.mreq_n (mreq_n);
88
        di_mux0.iorq_n (iorq_n);
89
        di_mux0.addr   (addr);
90
        di_mux0.di     (di);
91
        di_mux0.di_mem (di_mem);
92
        di_mux0.di_uart (di_uart);
93
        di_mux0.di_resp (di_resp);
94
        di_mux0.uart_cs_n (uart_cs_n);
95
 
96 91 ghutchis
    env_memory env_memory0("env_memory0");
97
    env_memory0.clk (clk);
98
    env_memory0.wr_data (dout);
99 97 ghutchis
    env_memory0.rd_data (di_mem);
100 91 ghutchis
    env_memory0.mreq_n (mreq_n);
101
    env_memory0.rd_n (rd_n);
102
    env_memory0.wr_n (wr_n);
103
    env_memory0.addr (addr);
104 94 ghutchis
    env_memory0.reset_n (reset_n);
105 92 ghutchis
 
106
    tv_responder tv_resp0("tv_resp0");
107
    tv_resp0.clk (clk);
108
    tv_resp0.reset_n (reset_n);
109
    tv_resp0.wait_n (wait_n);
110
    tv_resp0.int_n (int_n);
111
    tv_resp0.nmi_n (nmi_n);
112
    tv_resp0.busak_n (busak_n);
113
    tv_resp0.busrq_n (busrq_n);
114
    tv_resp0.m1_n (m1_n);
115
    tv_resp0.mreq_n (mreq_n);
116
    tv_resp0.iorq_n (iorq_n);
117
    tv_resp0.rd_n (rd_n);
118
    tv_resp0.wr_n (wr_n);
119
    tv_resp0.addr (addr);
120
    tv_resp0.di_resp (di_resp);
121
    tv_resp0.dout (dout);
122
    tv_resp0.halt_n (halt_n);
123 96 ghutchis
 
124
    dec0.clk (clk);
125
    dec0.m1_n (m1_n);
126
    dec0.addr (addr);
127
    dec0.mreq_n (mreq_n);
128
    dec0.rd_n (rd_n);
129
    dec0.wait_n (wait_n);
130
    dec0.di (di);
131
    dec0.reset_n (reset_n);
132 97 ghutchis
 
133
    VT16450 t16450 ("t16450");
134
    t16450.reset_n (reset_n);
135
    t16450.clk  (clk);
136
    t16450.rclk (clk);
137
    t16450.cs_n (uart_cs_n);
138
    t16450.rd_n (rd_n);
139
    t16450.wr_n (wr_n);
140
    t16450.addr (addr);
141
    t16450.wr_data (dout);
142
    t16450.rd_data (di_uart);
143
    t16450.sin (serial);
144
    t16450.cts_n (cts_n);
145
    t16450.dsr_n (dsr_n);
146
    t16450.ri_n  (ri_n);
147
    t16450.dcd_n (dcd_n);
148
 
149
    t16450.sout (serial);
150
    t16450.rts_n (cts_n);
151
    t16450.dtr_n (dsr_n);
152
    t16450.out1_n (ri_n);
153
    t16450.out2_n (dcd_n);
154
    t16450.baudout (baudout);
155
    t16450.intr (uart_int);
156 91 ghutchis
 
157 92 ghutchis
    // create dumpfile
158 94 ghutchis
    /*
159 92 ghutchis
    sc_trace_file *trace_file;
160
    trace_file = sc_create_vcd_trace_file("sc_tv80_env");
161
    sc_trace (trace_file, clk, "clk");
162
    sc_trace (trace_file, reset_n, "reset_n");
163
    sc_trace (trace_file, wait_n, "wait_n");
164
    sc_trace (trace_file, int_n, "int_n");
165
    sc_trace (trace_file, nmi_n, "nmi_n");
166
    sc_trace (trace_file, busrq_n, "busrq_n");
167
    sc_trace (trace_file, m1_n, "m1_n");
168
    sc_trace (trace_file, mreq_n, "mreq_n");
169
    sc_trace (trace_file, iorq_n, "iorq_n");
170
    sc_trace (trace_file, rd_n, "rd_n");
171
    sc_trace (trace_file, wr_n, "wr_n");
172
    sc_trace (trace_file, halt_n, "halt_n");
173
    sc_trace (trace_file, busak_n, "busak_n");
174
    sc_trace (trace_file, di, "di");
175
    sc_trace (trace_file, dout, "dout");
176
    sc_trace (trace_file, addr, "addr");
177 95 ghutchis
    */
178 94 ghutchis
 
179
    // Start Verilator traces
180 95 ghutchis
    if (dumping) {
181
        Verilated::traceEverOn(true);
182
        tfp = new SpTraceFile;
183
        tv80s.trace (tfp, 99);
184
        tfp->open (dumpfile_name);
185
    }
186 92 ghutchis
 
187 94 ghutchis
        // check for command line argument
188 95 ghutchis
        if (memfile) {
189
                printf ("Loading IHEX file %s\n", mem_src_name);
190
                env_memory0.load_ihex (mem_src_name);
191 94 ghutchis
        }
192
 
193
        // set reset to 0 before sim start
194
        reset_n.write (0);
195 92 ghutchis
 
196 94 ghutchis
    sc_start();
197
    /*
198 92 ghutchis
    sc_close_vcd_trace_file (trace_file);
199 94 ghutchis
    */
200 95 ghutchis
    if (dumping)
201
        tfp->close();
202 92 ghutchis
 
203 91 ghutchis
    return 0;
204 92 ghutchis
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.