OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [sc_env/] [sc_env_top.cpp] - Blame information for rev 92

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 91 ghutchis
#include "systemc.h"
2
#include "env_memory.h"
3 92 ghutchis
#include "tv_responder.h"
4 91 ghutchis
#include "Vtv80s.h"
5
 
6
int sc_main(int argc, char *argv[])
7
{
8
        sc_clock clk("clk125", 8, SC_NS, 0.5, 0.0, SC_NS);
9
 
10
        sc_signal<bool> reset_n;
11
        sc_signal<bool> wait_n;
12
        sc_signal<bool> int_n;
13
        sc_signal<bool> nmi_n;
14
        sc_signal<bool> busrq_n;
15
        sc_signal<bool> m1_n;
16
        sc_signal<bool> mreq_n;
17
        sc_signal<bool> iorq_n;
18
        sc_signal<bool> rd_n;
19
        sc_signal<bool> wr_n;
20
        sc_signal<bool> rfsh_n;
21
        sc_signal<bool> halt_n;
22
        sc_signal<bool> busak_n;
23
        sc_signal<uint32_t>     di;
24 92 ghutchis
        sc_signal<uint32_t> di_mem;
25
        sc_signal<uint32_t> di_resp;
26 91 ghutchis
        sc_signal<uint32_t>     dout;
27
        sc_signal<uint32_t>     addr;
28
 
29
        Vtv80s tv80s ("tv80s");
30
        tv80s.A (addr);
31
        tv80s.reset_n (reset_n);
32
        tv80s.clk (clk);
33
        tv80s.wait_n (wait_n);
34
        tv80s.int_n (int_n);
35
        tv80s.nmi_n (nmi_n);
36
        tv80s.busrq_n (busrq_n);
37
        tv80s.m1_n (m1_n);
38
        tv80s.mreq_n (mreq_n);
39
        tv80s.iorq_n (iorq_n);
40
        tv80s.rd_n (rd_n);
41
        tv80s.wr_n (wr_n);
42
        tv80s.rfsh_n (rfsh_n);
43
        tv80s.halt_n (halt_n);
44
        tv80s.busak_n (busak_n);
45
        tv80s.di (di);
46
        tv80s.dout (dout);
47
 
48
    env_memory env_memory0("env_memory0");
49
    env_memory0.clk (clk);
50
    env_memory0.wr_data (dout);
51
    env_memory0.rd_data (di);
52
    env_memory0.mreq_n (mreq_n);
53
    env_memory0.rd_n (rd_n);
54
    env_memory0.wr_n (wr_n);
55
    env_memory0.addr (addr);
56 92 ghutchis
 
57
    tv_responder tv_resp0("tv_resp0");
58
    tv_resp0.clk (clk);
59
    tv_resp0.reset_n (reset_n);
60
    tv_resp0.wait_n (wait_n);
61
    tv_resp0.int_n (int_n);
62
    tv_resp0.nmi_n (nmi_n);
63
    tv_resp0.busak_n (busak_n);
64
    tv_resp0.busrq_n (busrq_n);
65
    tv_resp0.m1_n (m1_n);
66
    tv_resp0.mreq_n (mreq_n);
67
    tv_resp0.iorq_n (iorq_n);
68
    tv_resp0.rd_n (rd_n);
69
    tv_resp0.wr_n (wr_n);
70
    tv_resp0.addr (addr);
71
    tv_resp0.di_resp (di_resp);
72
    tv_resp0.dout (dout);
73
    tv_resp0.halt_n (halt_n);
74 91 ghutchis
 
75 92 ghutchis
    // create dumpfile
76
    sc_trace_file *trace_file;
77
    trace_file = sc_create_vcd_trace_file("sc_tv80_env");
78
    sc_trace (trace_file, clk, "clk");
79
    sc_trace (trace_file, reset_n, "reset_n");
80
    sc_trace (trace_file, wait_n, "wait_n");
81
    sc_trace (trace_file, int_n, "int_n");
82
    sc_trace (trace_file, nmi_n, "nmi_n");
83
    sc_trace (trace_file, busrq_n, "busrq_n");
84
    sc_trace (trace_file, m1_n, "m1_n");
85
    sc_trace (trace_file, mreq_n, "mreq_n");
86
    sc_trace (trace_file, iorq_n, "iorq_n");
87
    sc_trace (trace_file, rd_n, "rd_n");
88
    sc_trace (trace_file, wr_n, "wr_n");
89
    sc_trace (trace_file, halt_n, "halt_n");
90
    sc_trace (trace_file, busak_n, "busak_n");
91
    sc_trace (trace_file, di, "di");
92
    sc_trace (trace_file, dout, "dout");
93
    sc_trace (trace_file, addr, "addr");
94
 
95
 
96 91 ghutchis
    sc_start(8000);
97 92 ghutchis
    sc_close_vcd_trace_file (trace_file);
98
 
99 91 ghutchis
    return 0;
100 92 ghutchis
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.