OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [sc_env/] [tv_responder.cpp] - Blame information for rev 94

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 92 ghutchis
#include "tv_responder.h"
2
 
3
void tv_responder::event ()
4
{
5
        // init
6 94 ghutchis
        //reset_n = 0;
7
        /*
8 92 ghutchis
        wait_n = 1;
9
        int_n = 1;
10
        nmi_n = 1;
11
        busrq_n = 1;
12
        di_resp = 0;
13 94 ghutchis
        */
14 92 ghutchis
 
15 94 ghutchis
        if (reset_time > 0) {
16
                reset_n = 0;
17
            wait_n = 1;
18
                int_n = 1;
19
                nmi_n = 1;
20
                busrq_n = 1;
21
                di_resp = 0;
22
                reset_time--;
23
                if (reset_time == 0)
24
                        printf ("Initialization complete.\n");
25
                return;
26
        } else {
27
                if (reset_time == 0) {
28
                        reset_n = 1;
29
                        reset_time--;
30
                }
31
        }
32
 
33
 
34
    if (!iorq_n & !rd_n)
35
        {
36
          switch (addr) {
37
            case (0x82) : di_resp = timeout_ctl; break;
38
                        case(0x83) : di_resp = max_timeout & 0xff; break;
39
                        case(0x84) : di_resp = max_timeout >> 8; break;
40
 
41
                case(0x90) : di_resp = int_countdown; break;
42
            case(0x91) : di_resp = checksum; break;
43
            case(0x93) : di_resp = ior_value; break;
44
            case(0x94) : di_resp = rand();  break;
45
            case(0x95) : di_resp = nmi_countdown; break;
46
            case(0xA0) : di_resp = nmi_trigger; break;
47
            default : di_resp = 0;
48
          }
49
        } // if (!iorq_n & !rd_n)
50
 
51
//  wire wr_stb;
52
//  reg last_iowrite;
53
 
54
//  assign wr_stb = (!iorq_n & !wr_n);
55
 
56
//  always @(posedge clk)
57
//   begin
58
      //last_iowrite <= #1 wr_stb;
59
    //if (!iorq_n && !wr_n)
60
    //  printf ("DEBUG:  I/O Write detected addr=%02x\n", 0xff & (int) addr.read());
61
 
62
    if (!iorq_n && !wr_n && !last_iowrite) {
63
        int l_dout, l_addr;
64
 
65
        l_addr = addr.read();
66
        l_dout = dout.read();
67
 
68
        last_iowrite = true;
69
                switch ( l_addr & 0xff) {
70
                        case(0x80) :
71
                        // dump control deprecated
72
                        if (l_dout == 1) {
73
                                printf ("%8d: --- TEST PASSED ---\n", 0);
74
                                sc_stop();
75
                        } else if (l_dout == 2) {
76
                                printf ("%8d: !!! TEST FAILED !!!\n", 0);
77
                                sc_stop();
78
                        }
79
                        break;
80
 
81
                        case(0x81) :
82
 
83
                        //printf ("%s: DEBUG   : Detected write of character %x\n", sc_time_stamp().to_string(), l_dout);
84
                        //cout << sc_time_stamp().to_string() << "DEBUG   : Detected write of character " << l_dout << endl;
85
                        if (l_dout == 0x0A) {
86
                                        //printf ("%8d: PROGRAM : ", sc_simulation_time());
87
                                        cout << sc_time_stamp() << ": PROGRAM : ";
88
 
89
                                        for (int i=0; i<buf_ptr; i=i+1)
90
                                                //printf ("%s", str_buf[i]);
91
                                                cout << str_buf[i];
92
 
93
                                        //printf ("\n");
94
                                        cout << endl;
95
                                        buf_ptr = 0;
96
                                } else {
97
                                str_buf[buf_ptr] = (char) (l_dout & 0xff);
98
                                buf_ptr = buf_ptr + 1;
99
                        }
100
                    break;
101
 
102
                        case(0x82) :
103
                        timeout_ctl = l_dout;
104
                                break;
105
 
106
                        case(0x83) :
107
                                max_timeout = l_dout | (max_timeout & 0xFF00);
108
                                break;
109
 
110
                        case(0x84) :
111
                                max_timeout = l_dout << 8 | (max_timeout & 0x00FF);
112
                                break;
113
 
114
                        case(0x90) : int_countdown = dout; break;
115
                        case(0x91) : checksum = dout; break;
116
                        case(0x92) : checksum = checksum + dout; break;
117
                        case(0x93) : ior_value = dout; break;
118
                        case(0x95) : nmi_countdown = dout; break;
119
                        case(0xA0) : nmi_trigger = dout; break;
120
                }
121
    } else if (iorq_n)
122
        last_iowrite = false;
123
 
124
        if (timeout_ctl & 0x2)
125
                cur_timeout = 0;
126
    else if (timeout_ctl & 0x1)
127
                cur_timeout = cur_timeout + 1;
128
 
129
    if (cur_timeout >= max_timeout) {
130
          printf ("%8d: ERROR   : Reached timeout %d cycles\n", 0, max_timeout);
131
          //tb_top.test_fail;
132
          sc_stop();
133
    }
134
 
135
        if (int_countdown == 0) {
136
                int_n = 1;
137
        } else if (int_countdown == 1)
138
                int_n  = 0;
139
    else if (int_countdown > 1) {
140
          int_countdown = int_countdown - 1;
141
          int_n  = 1;
142
    }
143
 
144
    // when nmi countdown reaches 1, an NMI will be issued.
145
    // to clear the interrupt, write nmi_countdown to 0.
146
    if ((nmi_countdown == 0) && (nmi_trigger == 0))
147
                nmi_n = 1;
148
    else if (nmi_countdown == 1)
149
                nmi_n = 0;
150
    else if (nmi_countdown > 1) {
151
                nmi_countdown = nmi_countdown - 1;
152
                nmi_n = 1;
153
    }
154
 
155
    // when IR equals the target instruction, an NMI will be
156
    // issued.  To clear the interrupt, write nmi_trigger to
157
    // zero.
158
    /*  can't do this in systemc
159
    if (nmi_trigger != 0) {
160
          if (nmi_trigger === tb_top.tv80s_inst.i_tv80_core.IR[7:0])
161
            begin
162
              tb_top.nmi_n <= #80 0;
163
              tb_top.nmi_n <= #160 1;
164
            end
165
    } else if (nmi_countdown == 0)
166
        nmi_n = 1;
167
     */
168 92 ghutchis
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.