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ghutchis |
#!/usr/bin/env python
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# Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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# to deal in the Software without restriction, including without limitation
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# the rights to use, copy, modify, merge, publish, distribute, sublicense,
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# and/or sell copies of the Software, and to permit persons to whom the
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# Software is furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included
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# in all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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import string, math
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def log2 (num):
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return math.ceil (math.log (num) / math.log (2))
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def comb_block (statements):
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result = 'always @*\n'
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result += ' begin\n'
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for s in statements:
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result += ' ' + s + '\n'
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result += ' end\n'
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return result
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def seq_block (clock, statements):
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result = 'always @(posedge ' + clock + ')\n'
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result += ' begin\n'
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for s in statements:
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result += ' ' + s + '\n'
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result += ' end\n'
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return result
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class net:
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def __init__ (self, type, name, width=1):
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self.width = width
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self.name = name
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self.type = type
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def declaration (self):
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if (self.width == 1):
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return self.type + ' ' + self.name + ';'
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else:
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return "%s [%d:0] %s;" % (self.type, self.width-1, self.name)
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class port:
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def __init__ (self, direction, name, width=1):
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self.direction = direction
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self.width = width
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self.name = name
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def declaration (self):
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if (self.width == 1):
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return self.direction + ' ' + self.name + ';'
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else:
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return "%s [%d:0] %s;" % (self.direction, self.width-1, self.name)
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class register_group:
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def __init__ (self, mem_mapped=0):
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self.base_addr = 0
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self.addr_size = 16
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self.data_size = 8
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self.name = ''
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self.local_width = 1
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self.registers = []
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self.ports = [port ('input', 'clk'), port('input','reset')]
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self.nets = []
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if (mem_mapped):
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self.req_pin = 'mreq_n'
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else:
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self.req_pin = 'iorq_n'
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self.tv80_intf()
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def tv80_intf (self):
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self.ports.append (port ('input', 'addr', self.addr_size))
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self.ports.append (port ('input', 'wr_data', self.data_size))
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self.ports.append (port ('output', 'rd_data', self.data_size))
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self.ports.append (port ('output', 'doe'))
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self.ports.append (port ('input','rd_n'))
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self.ports.append (port ('input', 'wr_n'))
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self.ports.append (port ('input', self.req_pin))
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def global_logic (self):
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# create select pin for this block
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self.nets.append (net('reg','block_select'))
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statements = ["block_select = (addr[%d:%d] == %d) & !%s;" % (self.addr_size-1,self.local_width,self.base_addr >> self.local_width, self.req_pin)]
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# create read and write selects for each register
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for r in self.registers:
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s = "%s_rd_sel = block_select & (addr[%d:%d] == %d) & !rd_n;" % (r.name,self.local_width-1,0,r.offset)
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statements.append (s)
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if r.write_cap():
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s = "%s_wr_sel = block_select & (addr[%d:%d] == %d) & !wr_n;" % (r.name,self.local_width-1,0,r.offset)
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statements.append (s)
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return comb_block (statements)
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def read_mux (self):
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s = ''
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for r in self.registers:
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s += "assign rd_data = (%s_rd_sel) ? %s : %d'bz;\n" % (r.name, r.name, self.data_size)
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return s
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def verilog (self):
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result = 'module ' + self.name + ' (\n'
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result += string.join (map (lambda x: x.name, self.ports), ',')
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result += ');\n'
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# print port list
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for p in self.ports:
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result += p.declaration() + '\n'
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# print net list
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for n in self.nets:
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result += n.declaration() + '\n'
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# create global logic
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result += self.global_logic()
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result += self.read_mux()
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# print function blocks
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for r in self.registers:
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result += r.verilog_body()
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result += 'endmodule;\n'
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return result
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def add_register (self, name, type, width):
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if (type == 'status'):
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self.add (status_reg (name,width))
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elif (type == 'config'):
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self.add (config_reg (name,width))
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else:
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print "Unknown register type",type
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def add (self, reg):
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self.registers.append (reg)
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self.ports.extend (reg.io())
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self.nets.extend (reg.nets())
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self.local_width = int(math.ceil (log2 (len (self.registers))))
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rnum = 0
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for r in self.registers:
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r.offset = rnum
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rnum += 1
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class basic_register:
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def __init__ (self, name='', width=0):
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self.offset = 0
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self.width = width
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self.name = name
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def verilog_body (self):
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pass
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def io (self):
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return []
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def nets (self):
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return []
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def write_cap (self):
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return 0
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class status_reg (basic_register):
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def __init__ (self, name='', width=0):
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basic_register.__init__(self, name, width)
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def verilog_body (self):
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pass
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def io (self):
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return [('input',self.width, self.name)]
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def nets (self):
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return [ net('reg', name + '_rd_sel')]
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class config_reg (basic_register):
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def __init__ (self, name='', width=0):
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basic_register.__init__(self, name, width)
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self.default = 0
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def verilog_body (self):
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statements = ["if (reset) %s <= %d;" % (self.name, self.default),
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"else if %s_wr_sel %s <= %s;" % (self.name, self.name, 'wr_data')
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]
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return seq_block ('clk', statements)
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def io (self):
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return [ port('output',self.name, self.width) ]
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def nets (self):
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return [ net('reg', self.name + '_rd_sel'), net('reg', self.name + '_wr_sel')]
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def write_cap (self):
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return 1
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