| 1 |
2 |
spyros |
-- Twofish.vhd
|
| 2 |
|
|
-- Copyright (C) 2006 Spyros Ninos
|
| 3 |
|
|
--
|
| 4 |
|
|
-- This program is free software; you can redistribute it and/or modify
|
| 5 |
|
|
-- it under the terms of the GNU General Public License as published by
|
| 6 |
|
|
-- the Free Software Foundation; either version 2 of the License, or
|
| 7 |
|
|
-- (at your option) any later version.
|
| 8 |
|
|
--
|
| 9 |
|
|
-- This program is distributed in the hope that it will be useful,
|
| 10 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 11 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 12 |
|
|
-- GNU General Public License for more details.
|
| 13 |
|
|
--
|
| 14 |
|
|
-- You should have received a copy of the GNU General Public License
|
| 15 |
|
|
-- along with this library; see the file COPYING. If not, write to:
|
| 16 |
|
|
--
|
| 17 |
|
|
-- Free Software Foundation
|
| 18 |
|
|
-- 59 Temple Place - Suite 330
|
| 19 |
|
|
-- Boston, MA 02111-1307, USA.
|
| 20 |
|
|
|
| 21 |
|
|
-- description : this file includes all the components necessary to perform symmetric encryption
|
| 22 |
|
|
-- with the twofish 128 bit block cipher. Within there are four main parts of the file.
|
| 23 |
|
|
-- the first part is the twofish crypto primitives which are independent of the key
|
| 24 |
|
|
-- input length, the second part is the 128 bit key input components, the third part
|
| 25 |
|
|
-- is the 192 bit key components and finaly the 256 bit key input components
|
| 26 |
|
|
--
|
| 27 |
|
|
|
| 28 |
|
|
|
| 29 |
|
|
-- ====================================================== --
|
| 30 |
|
|
-- ====================================================== --
|
| 31 |
|
|
-- --
|
| 32 |
|
|
-- first part: key input independent component primitives --
|
| 33 |
|
|
-- --
|
| 34 |
|
|
-- ====================================================== --
|
| 35 |
|
|
-- ====================================================== --
|
| 36 |
|
|
|
| 37 |
|
|
--
|
| 38 |
|
|
-- q0
|
| 39 |
|
|
--
|
| 40 |
|
|
|
| 41 |
|
|
library ieee;
|
| 42 |
|
|
Use ieee.std_logic_1164.all;
|
| 43 |
|
|
|
| 44 |
|
|
entity q0 is
|
| 45 |
|
|
port (
|
| 46 |
|
|
in_q0 : in std_logic_vector(7 downto 0);
|
| 47 |
|
|
out_q0 : out std_logic_vector(7 downto 0)
|
| 48 |
|
|
);
|
| 49 |
|
|
end q0;
|
| 50 |
|
|
|
| 51 |
|
|
architecture q0_arch of q0 is
|
| 52 |
|
|
|
| 53 |
|
|
-- declaring internal signals
|
| 54 |
|
|
signal a0,b0,
|
| 55 |
|
|
a1,b1,
|
| 56 |
|
|
a2,b2,
|
| 57 |
|
|
a3,b3,
|
| 58 |
|
|
a4,b4 : std_logic_vector(3 downto 0);
|
| 59 |
|
|
signal b0_ror4,
|
| 60 |
|
|
a0_times_8,
|
| 61 |
|
|
b2_ror4,
|
| 62 |
|
|
a2_times_8 : std_logic_vector(3 downto 0);
|
| 63 |
|
|
|
| 64 |
|
|
-- beginning of the architecture description
|
| 65 |
|
|
begin
|
| 66 |
|
|
|
| 67 |
|
|
-- little endian
|
| 68 |
|
|
b0 <= in_q0(3 downto 0);
|
| 69 |
|
|
a0 <= in_q0(7 downto 4);
|
| 70 |
|
|
|
| 71 |
|
|
a1 <= a0 XOR b0;
|
| 72 |
|
|
|
| 73 |
|
|
-- signal b0 is ror4'ed by 1 bit
|
| 74 |
|
|
b0_ror4(2 downto 0) <= b0(3 downto 1);
|
| 75 |
|
|
b0_ror4(3) <= b0(0);
|
| 76 |
|
|
|
| 77 |
|
|
-- 8*a0 = 2^3*a0= a0 << 3
|
| 78 |
|
|
a0_times_8(2 downto 0) <= (others => '0');
|
| 79 |
|
|
a0_times_8(3) <= a0(0);
|
| 80 |
|
|
|
| 81 |
|
|
b1 <= a0 XOR b0_ror4 XOR a0_times_8;
|
| 82 |
|
|
|
| 83 |
|
|
--
|
| 84 |
|
|
-- t0 table
|
| 85 |
|
|
--
|
| 86 |
|
|
with a1 select
|
| 87 |
|
|
a2 <= "1000" when "0000", -- 8
|
| 88 |
|
|
"0001" when "0001", -- 1
|
| 89 |
|
|
"0111" when "0010", -- 7
|
| 90 |
|
|
"1101" when "0011", -- D
|
| 91 |
|
|
"0110" when "0100", -- 6
|
| 92 |
|
|
"1111" when "0101", -- F
|
| 93 |
|
|
"0011" when "0110", -- 3
|
| 94 |
|
|
"0010" when "0111", -- 2
|
| 95 |
|
|
"0000" when "1000", -- 0
|
| 96 |
|
|
"1011" when "1001", -- B
|
| 97 |
|
|
"0101" when "1010", -- 5
|
| 98 |
|
|
"1001" when "1011", -- 9
|
| 99 |
|
|
"1110" when "1100", -- E
|
| 100 |
|
|
"1100" when "1101", -- C
|
| 101 |
|
|
"1010" when "1110", -- A
|
| 102 |
|
|
"0100" when others; -- 4
|
| 103 |
|
|
|
| 104 |
|
|
--
|
| 105 |
|
|
-- t1 table
|
| 106 |
|
|
--
|
| 107 |
|
|
with b1 select
|
| 108 |
|
|
b2 <= "1110" when "0000", -- E
|
| 109 |
|
|
"1100" when "0001", -- C
|
| 110 |
|
|
"1011" when "0010", -- B
|
| 111 |
|
|
"1000" when "0011", -- 8
|
| 112 |
|
|
"0001" when "0100", -- 1
|
| 113 |
|
|
"0010" when "0101", -- 2
|
| 114 |
|
|
"0011" when "0110", -- 3
|
| 115 |
|
|
"0101" when "0111", -- 5
|
| 116 |
|
|
"1111" when "1000", -- F
|
| 117 |
|
|
"0100" when "1001", -- 4
|
| 118 |
|
|
"1010" when "1010", -- A
|
| 119 |
|
|
"0110" when "1011", -- 6
|
| 120 |
|
|
"0111" when "1100", -- 7
|
| 121 |
|
|
"0000" when "1101", -- 0
|
| 122 |
|
|
"1001" when "1110", -- 9
|
| 123 |
|
|
"1101" when others; -- D
|
| 124 |
|
|
|
| 125 |
|
|
a3 <= a2 XOR b2;
|
| 126 |
|
|
|
| 127 |
|
|
-- signal b2 is ror4'ed by 1 bit
|
| 128 |
|
|
b2_ror4(2 downto 0) <= b2(3 downto 1);
|
| 129 |
|
|
b2_ror4(3) <= b2(0);
|
| 130 |
|
|
|
| 131 |
|
|
-- 8*a2 = 2^3*a2=a2<<3
|
| 132 |
|
|
a2_times_8(2 downto 0) <= (others => '0');
|
| 133 |
|
|
a2_times_8(3) <= a2(0);
|
| 134 |
|
|
|
| 135 |
|
|
b3 <= a2 XOR b2_ror4 XOR a2_times_8;
|
| 136 |
|
|
|
| 137 |
|
|
|
| 138 |
|
|
--
|
| 139 |
|
|
-- t0 table
|
| 140 |
|
|
--
|
| 141 |
|
|
with a3 select
|
| 142 |
|
|
a4 <= "1011" when "0000", -- B
|
| 143 |
|
|
"1010" when "0001", -- A
|
| 144 |
|
|
"0101" when "0010", -- 5
|
| 145 |
|
|
"1110" when "0011", -- E
|
| 146 |
|
|
"0110" when "0100", -- 6
|
| 147 |
|
|
"1101" when "0101", -- D
|
| 148 |
|
|
"1001" when "0110", -- 9
|
| 149 |
|
|
"0000" when "0111", -- 0
|
| 150 |
|
|
"1100" when "1000", -- C
|
| 151 |
|
|
"1000" when "1001", -- 8
|
| 152 |
|
|
"1111" when "1010", -- F
|
| 153 |
|
|
"0011" when "1011", -- 3
|
| 154 |
|
|
"0010" when "1100", -- 2
|
| 155 |
|
|
"0100" when "1101", -- 4
|
| 156 |
|
|
"0111" when "1110", -- 7
|
| 157 |
|
|
"0001" when others; -- 1
|
| 158 |
|
|
|
| 159 |
|
|
--
|
| 160 |
|
|
-- t1 table
|
| 161 |
|
|
--
|
| 162 |
|
|
with b3 select
|
| 163 |
|
|
b4 <= "1101" when "0000", -- D
|
| 164 |
|
|
"0111" when "0001", -- 7
|
| 165 |
|
|
"1111" when "0010", -- F
|
| 166 |
|
|
"0100" when "0011", -- 4
|
| 167 |
|
|
"0001" when "0100", -- 1
|
| 168 |
|
|
"0010" when "0101", -- 2
|
| 169 |
|
|
"0110" when "0110", -- 6
|
| 170 |
|
|
"1110" when "0111", -- E
|
| 171 |
|
|
"1001" when "1000", -- 9
|
| 172 |
|
|
"1011" when "1001", -- B
|
| 173 |
|
|
"0011" when "1010", -- 3
|
| 174 |
|
|
"0000" when "1011", -- 0
|
| 175 |
|
|
"1000" when "1100", -- 8
|
| 176 |
|
|
"0101" when "1101", -- 5
|
| 177 |
|
|
"1100" when "1110", -- C
|
| 178 |
|
|
"1010" when others; -- A
|
| 179 |
|
|
|
| 180 |
|
|
-- the output of q0
|
| 181 |
|
|
out_q0 <= b4 & a4;
|
| 182 |
|
|
|
| 183 |
|
|
end q0_arch;
|
| 184 |
|
|
|
| 185 |
|
|
|
| 186 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 187 |
|
|
-- --
|
| 188 |
|
|
-- new component --
|
| 189 |
|
|
-- --
|
| 190 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 191 |
|
|
|
| 192 |
|
|
--
|
| 193 |
|
|
-- q1
|
| 194 |
|
|
--
|
| 195 |
|
|
|
| 196 |
|
|
library ieee;
|
| 197 |
|
|
Use ieee.std_logic_1164.all;
|
| 198 |
|
|
|
| 199 |
|
|
entity q1 is
|
| 200 |
|
|
port (
|
| 201 |
|
|
in_q1 : in std_logic_vector(7 downto 0);
|
| 202 |
|
|
out_q1 : out std_logic_vector(7 downto 0)
|
| 203 |
|
|
);
|
| 204 |
|
|
end q1;
|
| 205 |
|
|
|
| 206 |
|
|
-- architecture description
|
| 207 |
|
|
architecture q1_arch of q1 is
|
| 208 |
|
|
|
| 209 |
|
|
-- declaring the internal signals
|
| 210 |
|
|
signal a0,b0,
|
| 211 |
|
|
a1,b1,
|
| 212 |
|
|
a2,b2,
|
| 213 |
|
|
a3,b3,
|
| 214 |
|
|
a4,b4 : std_logic_vector(3 downto 0);
|
| 215 |
|
|
signal b0_ror4,
|
| 216 |
|
|
a0_times_8,
|
| 217 |
|
|
b2_ror4,
|
| 218 |
|
|
a2_times_8 : std_logic_vector(3 downto 0);
|
| 219 |
|
|
|
| 220 |
|
|
-- begin the architecture description
|
| 221 |
|
|
begin
|
| 222 |
|
|
|
| 223 |
|
|
-- little endian
|
| 224 |
|
|
b0 <= in_q1(3 downto 0);
|
| 225 |
|
|
a0 <= in_q1(7 downto 4);
|
| 226 |
|
|
|
| 227 |
|
|
a1 <= a0 XOR b0;
|
| 228 |
|
|
|
| 229 |
|
|
-- signal b0 is ror4'ed by 1 bit
|
| 230 |
|
|
b0_ror4(2 downto 0) <= b0(3 downto 1);
|
| 231 |
|
|
b0_ror4(3) <= b0(0);
|
| 232 |
|
|
|
| 233 |
|
|
-- 8*a0 = 2^3*a0=a0<<3
|
| 234 |
|
|
a0_times_8(2 downto 0) <= (others => '0');
|
| 235 |
|
|
a0_times_8(3) <= a0(0);
|
| 236 |
|
|
|
| 237 |
|
|
b1 <= a0 XOR b0_ror4 XOR a0_times_8;
|
| 238 |
|
|
|
| 239 |
|
|
--
|
| 240 |
|
|
-- t0 table
|
| 241 |
|
|
--
|
| 242 |
|
|
with a1 select
|
| 243 |
|
|
a2 <= "0010" when "0000", -- 2
|
| 244 |
|
|
"1000" when "0001", -- 8
|
| 245 |
|
|
"1011" when "0010", -- b
|
| 246 |
|
|
"1101" when "0011", -- d
|
| 247 |
|
|
"1111" when "0100", -- f
|
| 248 |
|
|
"0111" when "0101", -- 7
|
| 249 |
|
|
"0110" when "0110", -- 6
|
| 250 |
|
|
"1110" when "0111", -- e
|
| 251 |
|
|
"0011" when "1000", -- 3
|
| 252 |
|
|
"0001" when "1001", -- 1
|
| 253 |
|
|
"1001" when "1010", -- 9
|
| 254 |
|
|
"0100" when "1011", -- 4
|
| 255 |
|
|
"0000" when "1100", -- 0
|
| 256 |
|
|
"1010" when "1101", -- a
|
| 257 |
|
|
"1100" when "1110", -- c
|
| 258 |
|
|
"0101" when others; -- 5
|
| 259 |
|
|
|
| 260 |
|
|
--
|
| 261 |
|
|
-- t1 table
|
| 262 |
|
|
--
|
| 263 |
|
|
with b1 select
|
| 264 |
|
|
b2 <= "0001" when "0000", -- 1
|
| 265 |
|
|
"1110" when "0001", -- e
|
| 266 |
|
|
"0010" when "0010", -- 2
|
| 267 |
|
|
"1011" when "0011", -- b
|
| 268 |
|
|
"0100" when "0100", -- 4
|
| 269 |
|
|
"1100" when "0101", -- c
|
| 270 |
|
|
"0011" when "0110", -- 3
|
| 271 |
|
|
"0111" when "0111", -- 7
|
| 272 |
|
|
"0110" when "1000", -- 6
|
| 273 |
|
|
"1101" when "1001", -- d
|
| 274 |
|
|
"1010" when "1010", -- a
|
| 275 |
|
|
"0101" when "1011", -- 5
|
| 276 |
|
|
"1111" when "1100", -- f
|
| 277 |
|
|
"1001" when "1101", -- 9
|
| 278 |
|
|
"0000" when "1110", -- 0
|
| 279 |
|
|
"1000" when others; -- 8
|
| 280 |
|
|
|
| 281 |
|
|
a3 <= a2 XOR b2;
|
| 282 |
|
|
|
| 283 |
|
|
-- signal b2 is ror4'ed by 1 bit
|
| 284 |
|
|
b2_ror4(2 downto 0) <= b2(3 downto 1);
|
| 285 |
|
|
b2_ror4(3) <= b2(0);
|
| 286 |
|
|
|
| 287 |
|
|
-- 8*a2 = 2^3*a2=a2<<3
|
| 288 |
|
|
a2_times_8(2 downto 0) <= (others => '0');
|
| 289 |
|
|
a2_times_8(3) <= a2(0);
|
| 290 |
|
|
|
| 291 |
|
|
b3 <= a2 XOR b2_ror4 XOR a2_times_8;
|
| 292 |
|
|
|
| 293 |
|
|
--
|
| 294 |
|
|
-- t0 table
|
| 295 |
|
|
--
|
| 296 |
|
|
with a3 select
|
| 297 |
|
|
a4 <= "0100" when "0000", -- 4
|
| 298 |
|
|
"1100" when "0001", -- c
|
| 299 |
|
|
"0111" when "0010", -- 7
|
| 300 |
|
|
"0101" when "0011", -- 5
|
| 301 |
|
|
"0001" when "0100", -- 1
|
| 302 |
|
|
"0110" when "0101", -- 6
|
| 303 |
|
|
"1001" when "0110", -- 9
|
| 304 |
|
|
"1010" when "0111", -- a
|
| 305 |
|
|
"0000" when "1000", -- 0
|
| 306 |
|
|
"1110" when "1001", -- e
|
| 307 |
|
|
"1101" when "1010", -- d
|
| 308 |
|
|
"1000" when "1011", -- 8
|
| 309 |
|
|
"0010" when "1100", -- 2
|
| 310 |
|
|
"1011" when "1101", -- b
|
| 311 |
|
|
"0011" when "1110", -- 3
|
| 312 |
|
|
"1111" when others; -- f
|
| 313 |
|
|
|
| 314 |
|
|
--
|
| 315 |
|
|
-- t1 table
|
| 316 |
|
|
--
|
| 317 |
|
|
with b3 select
|
| 318 |
|
|
b4 <= "1011" when "0000", -- b
|
| 319 |
|
|
"1001" when "0001", -- 9
|
| 320 |
|
|
"0101" when "0010", -- 5
|
| 321 |
|
|
"0001" when "0011", -- 1
|
| 322 |
|
|
"1100" when "0100", -- c
|
| 323 |
|
|
"0011" when "0101", -- 3
|
| 324 |
|
|
"1101" when "0110", -- d
|
| 325 |
|
|
"1110" when "0111", -- e
|
| 326 |
|
|
"0110" when "1000", -- 6
|
| 327 |
|
|
"0100" when "1001", -- 4
|
| 328 |
|
|
"0111" when "1010", -- 7
|
| 329 |
|
|
"1111" when "1011", -- f
|
| 330 |
|
|
"0010" when "1100", -- 2
|
| 331 |
|
|
"0000" when "1101", -- 0
|
| 332 |
|
|
"1000" when "1110", -- 8
|
| 333 |
|
|
"1010" when others; -- a
|
| 334 |
|
|
|
| 335 |
|
|
-- output of q1
|
| 336 |
|
|
out_q1 <= b4 & a4;
|
| 337 |
|
|
|
| 338 |
|
|
end q1_arch;
|
| 339 |
|
|
|
| 340 |
|
|
|
| 341 |
|
|
|
| 342 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 343 |
|
|
-- --
|
| 344 |
|
|
-- new component --
|
| 345 |
|
|
-- --
|
| 346 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 347 |
|
|
|
| 348 |
|
|
--
|
| 349 |
|
|
-- ef multiplier
|
| 350 |
|
|
--
|
| 351 |
|
|
|
| 352 |
|
|
library ieee;
|
| 353 |
|
|
use ieee.std_logic_1164.all;
|
| 354 |
|
|
|
| 355 |
|
|
entity mul_ef is
|
| 356 |
|
|
port (
|
| 357 |
|
|
in_ef : in std_logic_vector(7 downto 0);
|
| 358 |
|
|
out_ef : out std_logic_vector(7 downto 0)
|
| 359 |
|
|
);
|
| 360 |
|
|
end mul_ef;
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
architecture mul_ef_arch of mul_ef is
|
| 364 |
|
|
|
| 365 |
|
|
begin
|
| 366 |
|
|
out_ef(0) <= in_ef(2) XOR in_ef(1) XOR in_ef(0);
|
| 367 |
|
|
out_ef(1) <= in_ef(3) XOR in_ef(2) XOR in_ef(1) XOR in_ef(0);
|
| 368 |
|
|
out_ef(2) <= in_ef(4) XOR in_ef(3) XOR in_ef(2) XOR in_ef(1) XOR in_ef(0);
|
| 369 |
|
|
out_ef(3) <= in_ef(5) XOR in_ef(4) XOR in_ef(3) XOR in_ef(0);
|
| 370 |
|
|
out_ef(4) <= in_ef(6) XOR in_ef(5) XOR in_ef(4) XOR in_ef(1);
|
| 371 |
|
|
out_ef(5) <= in_ef(7) XOR in_ef(6) XOR in_ef(5) XOR in_ef(1) XOR in_ef(0);
|
| 372 |
|
|
out_ef(6) <= in_ef(7) XOR in_ef(6) XOR in_ef(0);
|
| 373 |
|
|
out_ef(7) <= in_ef(7) XOR in_ef(1) XOR in_ef(0);
|
| 374 |
|
|
end mul_ef_arch;
|
| 375 |
|
|
|
| 376 |
|
|
|
| 377 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 378 |
|
|
-- --
|
| 379 |
|
|
-- new component --
|
| 380 |
|
|
-- --
|
| 381 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 382 |
|
|
|
| 383 |
|
|
|
| 384 |
|
|
--
|
| 385 |
|
|
-- 5b multiplier
|
| 386 |
|
|
--
|
| 387 |
|
|
|
| 388 |
|
|
library ieee;
|
| 389 |
|
|
use ieee.std_logic_1164.all;
|
| 390 |
|
|
|
| 391 |
|
|
entity mul_5b is
|
| 392 |
|
|
port (
|
| 393 |
|
|
in_5b : in std_logic_vector(7 downto 0);
|
| 394 |
|
|
out_5b : out std_logic_vector(7 downto 0)
|
| 395 |
|
|
);
|
| 396 |
|
|
end mul_5b;
|
| 397 |
|
|
|
| 398 |
|
|
architecture mul_5b_arch of mul_5b is
|
| 399 |
|
|
begin
|
| 400 |
|
|
out_5b(0) <= in_5b(2) XOR in_5b(0);
|
| 401 |
|
|
out_5b(1) <= in_5b(3) XOR in_5b(1) XOR in_5b(0);
|
| 402 |
|
|
out_5b(2) <= in_5b(4) XOR in_5b(2) XOR in_5b(1);
|
| 403 |
|
|
out_5b(3) <= in_5b(5) XOR in_5b(3) XOR in_5b(0);
|
| 404 |
|
|
out_5b(4) <= in_5b(6) XOR in_5b(4) XOR in_5b(1) XOR in_5b(0);
|
| 405 |
|
|
out_5b(5) <= in_5b(7) XOR in_5b(5) XOR in_5b(1);
|
| 406 |
|
|
out_5b(6) <= in_5b(6) XOR in_5b(0);
|
| 407 |
|
|
out_5b(7) <= in_5b(7) XOR in_5b(1);
|
| 408 |
|
|
end mul_5b_arch;
|
| 409 |
|
|
|
| 410 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 411 |
|
|
-- --
|
| 412 |
|
|
-- new component --
|
| 413 |
|
|
-- --
|
| 414 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 415 |
|
|
|
| 416 |
|
|
--
|
| 417 |
|
|
-- mds
|
| 418 |
|
|
--
|
| 419 |
|
|
|
| 420 |
|
|
library ieee;
|
| 421 |
|
|
use ieee.std_logic_1164.all;
|
| 422 |
|
|
|
| 423 |
|
|
entity mds is
|
| 424 |
|
|
port (
|
| 425 |
|
|
y0,
|
| 426 |
|
|
y1,
|
| 427 |
|
|
y2,
|
| 428 |
|
|
y3 : in std_logic_vector(7 downto 0);
|
| 429 |
|
|
z0,
|
| 430 |
|
|
z1,
|
| 431 |
|
|
z2,
|
| 432 |
|
|
z3 : out std_logic_vector(7 downto 0)
|
| 433 |
|
|
);
|
| 434 |
|
|
end mds;
|
| 435 |
|
|
|
| 436 |
|
|
|
| 437 |
|
|
-- architecture description of mds component
|
| 438 |
|
|
architecture mds_arch of mds is
|
| 439 |
|
|
|
| 440 |
|
|
-- we declare the multiplier by ef
|
| 441 |
|
|
component mul_ef
|
| 442 |
|
|
port (
|
| 443 |
|
|
in_ef : in std_logic_vector(7 downto 0);
|
| 444 |
|
|
out_ef : out std_logic_vector(7 downto 0)
|
| 445 |
|
|
);
|
| 446 |
|
|
end component;
|
| 447 |
|
|
|
| 448 |
|
|
-- we declare the multiplier by 5b
|
| 449 |
|
|
component mul_5b
|
| 450 |
|
|
port (
|
| 451 |
|
|
in_5b : in std_logic_vector(7 downto 0);
|
| 452 |
|
|
out_5b : out std_logic_vector(7 downto 0)
|
| 453 |
|
|
);
|
| 454 |
|
|
end component;
|
| 455 |
|
|
|
| 456 |
|
|
-- we declare the multiplier's outputs
|
| 457 |
|
|
signal y0_ef, y0_5b,
|
| 458 |
|
|
y1_ef, y1_5b,
|
| 459 |
|
|
y2_ef, y2_5b,
|
| 460 |
|
|
y3_ef, y3_5b : std_logic_vector(7 downto 0);
|
| 461 |
|
|
|
| 462 |
|
|
begin
|
| 463 |
|
|
|
| 464 |
|
|
-- we perform the signal multiplication
|
| 465 |
|
|
y0_times_ef: mul_ef
|
| 466 |
|
|
port map (
|
| 467 |
|
|
in_ef => y0,
|
| 468 |
|
|
out_ef => y0_ef
|
| 469 |
|
|
);
|
| 470 |
|
|
|
| 471 |
|
|
y0_times_5b: mul_5b
|
| 472 |
|
|
port map (
|
| 473 |
|
|
in_5b => y0,
|
| 474 |
|
|
out_5b => y0_5b
|
| 475 |
|
|
);
|
| 476 |
|
|
|
| 477 |
|
|
y1_times_ef: mul_ef
|
| 478 |
|
|
port map (
|
| 479 |
|
|
in_ef => y1,
|
| 480 |
|
|
out_ef => y1_ef
|
| 481 |
|
|
);
|
| 482 |
|
|
|
| 483 |
|
|
y1_times_5b: mul_5b
|
| 484 |
|
|
port map (
|
| 485 |
|
|
in_5b => y1,
|
| 486 |
|
|
out_5b => y1_5b
|
| 487 |
|
|
);
|
| 488 |
|
|
|
| 489 |
|
|
y2_times_ef: mul_ef
|
| 490 |
|
|
port map (
|
| 491 |
|
|
in_ef => y2,
|
| 492 |
|
|
out_ef => y2_ef
|
| 493 |
|
|
);
|
| 494 |
|
|
|
| 495 |
|
|
y2_times_5b: mul_5b
|
| 496 |
|
|
port map (
|
| 497 |
|
|
in_5b => y2,
|
| 498 |
|
|
out_5b => y2_5b
|
| 499 |
|
|
);
|
| 500 |
|
|
|
| 501 |
|
|
y3_times_ef: mul_ef
|
| 502 |
|
|
port map (
|
| 503 |
|
|
in_ef => y3,
|
| 504 |
|
|
out_ef => y3_ef
|
| 505 |
|
|
);
|
| 506 |
|
|
|
| 507 |
|
|
y3_times_5b: mul_5b
|
| 508 |
|
|
port map (
|
| 509 |
|
|
in_5b => y3,
|
| 510 |
|
|
out_5b => y3_5b
|
| 511 |
|
|
);
|
| 512 |
|
|
|
| 513 |
|
|
-- we perform the addition of the partial results in order to receive
|
| 514 |
|
|
-- the table output
|
| 515 |
|
|
|
| 516 |
|
|
-- z0 = y0*01 + y1*ef + y2*5b + y3*5b , opoy + bazoyme XOR
|
| 517 |
|
|
z0 <= y0 XOR y1_ef XOR y2_5b XOR y3_5b;
|
| 518 |
|
|
|
| 519 |
|
|
-- z1 = y0*5b + y1*ef + y2*ef + y3*01
|
| 520 |
|
|
z1 <= y0_5b XOR y1_ef XOR y2_ef XOR y3;
|
| 521 |
|
|
|
| 522 |
|
|
-- z2 = y0*ef + y1*5b + y2*01 +y3*ef
|
| 523 |
|
|
z2 <= y0_ef XOR y1_5b XOR y2 XOR y3_ef;
|
| 524 |
|
|
|
| 525 |
|
|
-- z3 = y0*ef + y1*01 + y2*ef + y3*5b
|
| 526 |
|
|
z3 <= y0_ef XOR y1 XOR y2_ef XOR y3_5b;
|
| 527 |
|
|
|
| 528 |
|
|
end mds_arch;
|
| 529 |
|
|
|
| 530 |
|
|
|
| 531 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 532 |
|
|
-- --
|
| 533 |
|
|
-- new component --
|
| 534 |
|
|
-- --
|
| 535 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 536 |
|
|
|
| 537 |
|
|
--
|
| 538 |
|
|
-- 1 bit adder
|
| 539 |
|
|
--
|
| 540 |
|
|
|
| 541 |
|
|
library ieee;
|
| 542 |
|
|
use ieee.std_logic_1164.all;
|
| 543 |
|
|
|
| 544 |
|
|
entity adder is
|
| 545 |
|
|
port (
|
| 546 |
|
|
in1_adder,
|
| 547 |
|
|
in2_adder,
|
| 548 |
|
|
in_carry_adder : in std_logic;
|
| 549 |
|
|
out_adder,
|
| 550 |
|
|
out_carry_adder : out std_logic
|
| 551 |
|
|
);
|
| 552 |
|
|
end adder;
|
| 553 |
|
|
|
| 554 |
|
|
architecture adder_arch of adder is
|
| 555 |
|
|
begin
|
| 556 |
|
|
|
| 557 |
|
|
out_adder <= in_carry_adder XOR in1_adder XOR in2_adder;
|
| 558 |
|
|
out_carry_adder <= (in_carry_adder AND (in1_adder XOR in2_adder)) OR (in1_adder AND in2_adder);
|
| 559 |
|
|
|
| 560 |
|
|
end adder_arch;
|
| 561 |
|
|
|
| 562 |
|
|
|
| 563 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 564 |
|
|
-- --
|
| 565 |
|
|
-- new component --
|
| 566 |
|
|
-- --
|
| 567 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 568 |
|
|
|
| 569 |
|
|
--
|
| 570 |
|
|
-- pht
|
| 571 |
|
|
--
|
| 572 |
|
|
|
| 573 |
|
|
library ieee;
|
| 574 |
|
|
use ieee.std_logic_1164.all;
|
| 575 |
|
|
|
| 576 |
|
|
entity pht is
|
| 577 |
|
|
port (
|
| 578 |
|
|
up_in_pht,
|
| 579 |
|
|
down_in_pht : in std_logic_vector(31 downto 0);
|
| 580 |
|
|
up_out_pht,
|
| 581 |
|
|
down_out_pht : out std_logic_vector(31 downto 0)
|
| 582 |
|
|
);
|
| 583 |
|
|
end pht;
|
| 584 |
|
|
|
| 585 |
|
|
|
| 586 |
|
|
-- architecture description
|
| 587 |
|
|
architecture pht_arch of pht is
|
| 588 |
|
|
|
| 589 |
|
|
-- we declare internal signals
|
| 590 |
|
|
signal intermediate_carry1,
|
| 591 |
|
|
intermediate_carry2,
|
| 592 |
|
|
to_upper_out : std_logic_vector(31 downto 0);
|
| 593 |
|
|
signal zero : std_logic;
|
| 594 |
|
|
|
| 595 |
|
|
component adder
|
| 596 |
|
|
port (
|
| 597 |
|
|
in1_adder,
|
| 598 |
|
|
in2_adder,
|
| 599 |
|
|
in_carry_adder : in std_logic;
|
| 600 |
|
|
out_adder,
|
| 601 |
|
|
out_carry_adder : out std_logic
|
| 602 |
|
|
);
|
| 603 |
|
|
end component;
|
| 604 |
|
|
|
| 605 |
|
|
begin
|
| 606 |
|
|
|
| 607 |
|
|
-- initializing zero signal
|
| 608 |
|
|
zero <= '0';
|
| 609 |
|
|
|
| 610 |
|
|
-- instantiating the upper adder of 32 bits
|
| 611 |
|
|
up_adder: for i in 0 to 31 generate
|
| 612 |
|
|
adder_one: if (i=0) generate
|
| 613 |
|
|
the_adder: adder
|
| 614 |
|
|
port map (
|
| 615 |
|
|
in1_adder => up_in_pht(0),
|
| 616 |
|
|
in2_adder => down_in_pht(0),
|
| 617 |
|
|
in_carry_adder => zero,
|
| 618 |
|
|
out_adder => to_upper_out(0),
|
| 619 |
|
|
out_carry_adder => intermediate_carry1(0)
|
| 620 |
|
|
);
|
| 621 |
|
|
end generate adder_one;
|
| 622 |
|
|
rest_adders: if (i>0) generate
|
| 623 |
|
|
next_adder: adder
|
| 624 |
|
|
port map (
|
| 625 |
|
|
in1_adder => up_in_pht(i),
|
| 626 |
|
|
in2_adder => down_in_pht(i),
|
| 627 |
|
|
in_carry_adder => intermediate_carry1(i-1),
|
| 628 |
|
|
out_adder => to_upper_out(i),
|
| 629 |
|
|
out_carry_adder => intermediate_carry1(i)
|
| 630 |
|
|
);
|
| 631 |
|
|
end generate rest_adders;
|
| 632 |
|
|
end generate up_adder;
|
| 633 |
|
|
|
| 634 |
|
|
intermediate_carry1(31) <= '0';
|
| 635 |
|
|
|
| 636 |
|
|
-- receiving the upper pht output
|
| 637 |
|
|
up_out_pht <= to_upper_out;
|
| 638 |
|
|
|
| 639 |
|
|
-- instantiating the lower adder of 32 bits
|
| 640 |
|
|
down_adder: for i in 0 to 31 generate
|
| 641 |
|
|
adder_one_1: if (i=0) generate
|
| 642 |
|
|
the_adder_1: adder
|
| 643 |
|
|
port map (
|
| 644 |
|
|
in1_adder => down_in_pht(0),
|
| 645 |
|
|
in2_adder => to_upper_out(0),
|
| 646 |
|
|
in_carry_adder => zero,
|
| 647 |
|
|
out_adder => down_out_pht(0),
|
| 648 |
|
|
out_carry_adder => intermediate_carry2(0)
|
| 649 |
|
|
);
|
| 650 |
|
|
end generate adder_one_1;
|
| 651 |
|
|
rest_adders_1: if (i>0) generate
|
| 652 |
|
|
next_adder_1: adder
|
| 653 |
|
|
port map (
|
| 654 |
|
|
in1_adder => down_in_pht(i),
|
| 655 |
|
|
in2_adder => to_upper_out(i),
|
| 656 |
|
|
in_carry_adder => intermediate_carry2(i-1),
|
| 657 |
|
|
out_adder => down_out_pht(i),
|
| 658 |
|
|
out_carry_adder => intermediate_carry2(i)
|
| 659 |
|
|
);
|
| 660 |
|
|
end generate rest_adders_1;
|
| 661 |
|
|
end generate down_adder;
|
| 662 |
|
|
|
| 663 |
|
|
intermediate_carry2(31) <= '0';
|
| 664 |
|
|
|
| 665 |
|
|
end pht_arch;
|
| 666 |
|
|
|
| 667 |
|
|
|
| 668 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 669 |
|
|
-- --
|
| 670 |
|
|
-- new component --
|
| 671 |
|
|
-- --
|
| 672 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 673 |
|
|
|
| 674 |
|
|
--
|
| 675 |
|
|
-- multiplier by 01
|
| 676 |
|
|
--
|
| 677 |
|
|
|
| 678 |
|
|
library ieee;
|
| 679 |
|
|
use ieee.std_logic_1164.all;
|
| 680 |
|
|
|
| 681 |
|
|
entity mul01 is
|
| 682 |
|
|
port (
|
| 683 |
|
|
in_mul01 : in std_logic_vector(7 downto 0);
|
| 684 |
|
|
out_mul01 : out std_logic_vector(7 downto 0)
|
| 685 |
|
|
);
|
| 686 |
|
|
end mul01;
|
| 687 |
|
|
|
| 688 |
|
|
architecture mul01_arch of mul01 is
|
| 689 |
|
|
begin
|
| 690 |
|
|
out_mul01 <= in_mul01;
|
| 691 |
|
|
end mul01_arch;
|
| 692 |
|
|
|
| 693 |
|
|
|
| 694 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 695 |
|
|
-- --
|
| 696 |
|
|
-- new component --
|
| 697 |
|
|
-- --
|
| 698 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 699 |
|
|
|
| 700 |
|
|
--
|
| 701 |
|
|
-- multiplier by a4
|
| 702 |
|
|
--
|
| 703 |
|
|
|
| 704 |
|
|
library ieee;
|
| 705 |
|
|
use ieee.std_logic_1164.all;
|
| 706 |
|
|
|
| 707 |
|
|
entity mula4 is
|
| 708 |
|
|
port (
|
| 709 |
|
|
in_mula4 : in std_logic_vector(7 downto 0);
|
| 710 |
|
|
out_mula4 : out std_logic_vector(7 downto 0)
|
| 711 |
|
|
);
|
| 712 |
|
|
end mula4;
|
| 713 |
|
|
|
| 714 |
|
|
architecture mula4_arch of mula4 is
|
| 715 |
|
|
begin
|
| 716 |
|
|
out_mula4(0) <= in_mula4(7) xor in_mula4(1);
|
| 717 |
|
|
out_mula4(1) <= in_mula4(2);
|
| 718 |
|
|
out_mula4(2) <= in_mula4(7) xor in_mula4(3) xor in_mula4(1) xor in_mula4(0);
|
| 719 |
|
|
out_mula4(3) <= in_mula4(7) xor in_mula4(4) xor in_mula4(2);
|
| 720 |
|
|
out_mula4(4) <= in_mula4(5) xor in_mula4(3);
|
| 721 |
|
|
out_mula4(5) <= in_mula4(6) xor in_mula4(4) xor in_mula4(0);
|
| 722 |
|
|
out_mula4(6) <= in_mula4(5);
|
| 723 |
|
|
out_mula4(7) <= in_mula4(6) xor in_mula4(0);
|
| 724 |
|
|
end mula4_arch;
|
| 725 |
|
|
|
| 726 |
|
|
|
| 727 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 728 |
|
|
-- --
|
| 729 |
|
|
-- new component --
|
| 730 |
|
|
-- --
|
| 731 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 732 |
|
|
|
| 733 |
|
|
--
|
| 734 |
|
|
-- multiplier by 55
|
| 735 |
|
|
--
|
| 736 |
|
|
|
| 737 |
|
|
library ieee;
|
| 738 |
|
|
use ieee.std_logic_1164.all;
|
| 739 |
|
|
|
| 740 |
|
|
entity mul55 is
|
| 741 |
|
|
port (
|
| 742 |
|
|
in_mul55 : in std_logic_vector(7 downto 0);
|
| 743 |
|
|
out_mul55 : out std_logic_vector(7 downto 0)
|
| 744 |
|
|
);
|
| 745 |
|
|
end mul55;
|
| 746 |
|
|
|
| 747 |
|
|
architecture mul55_arch of mul55 is
|
| 748 |
|
|
begin
|
| 749 |
|
|
out_mul55(0) <= in_mul55(7) xor in_mul55(6) xor in_mul55(2) xor in_mul55(0);
|
| 750 |
|
|
out_mul55(1) <= in_mul55(7) xor in_mul55(3) xor in_mul55(1);
|
| 751 |
|
|
out_mul55(2) <= in_mul55(7) xor in_mul55(6) xor in_mul55(4) xor in_mul55(0);
|
| 752 |
|
|
out_mul55(3) <= in_mul55(6) xor in_mul55(5) xor in_mul55(2) xor in_mul55(1);
|
| 753 |
|
|
out_mul55(4) <= in_mul55(7) xor in_mul55(6) xor in_mul55(3) xor in_mul55(2) xor in_mul55(0);
|
| 754 |
|
|
out_mul55(5) <= in_mul55(7) xor in_mul55(4) xor in_mul55(3) xor in_mul55(1);
|
| 755 |
|
|
out_mul55(6) <= in_mul55(7) xor in_mul55(6) xor in_mul55(5) xor in_mul55(4) xor in_mul55(0);
|
| 756 |
|
|
out_mul55(7) <= in_mul55(7) xor in_mul55(6) xor in_mul55(5) xor in_mul55(1);
|
| 757 |
|
|
end mul55_arch;
|
| 758 |
|
|
|
| 759 |
|
|
|
| 760 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 761 |
|
|
-- --
|
| 762 |
|
|
-- new component --
|
| 763 |
|
|
-- --
|
| 764 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 765 |
|
|
|
| 766 |
|
|
--
|
| 767 |
|
|
-- multiplier by 87
|
| 768 |
|
|
--
|
| 769 |
|
|
|
| 770 |
|
|
library ieee;
|
| 771 |
|
|
use ieee.std_logic_1164.all;
|
| 772 |
|
|
|
| 773 |
|
|
entity mul87 is
|
| 774 |
|
|
port (
|
| 775 |
|
|
in_mul87 : in std_logic_vector(7 downto 0);
|
| 776 |
|
|
out_mul87 : out std_logic_vector(7 downto 0)
|
| 777 |
|
|
);
|
| 778 |
|
|
end mul87;
|
| 779 |
|
|
|
| 780 |
|
|
architecture mul87_arch of mul87 is
|
| 781 |
|
|
begin
|
| 782 |
|
|
out_mul87(0) <= in_mul87(7) xor in_mul87(5) xor in_mul87(3) xor in_mul87(1) xor in_mul87(0);
|
| 783 |
|
|
out_mul87(1) <= in_mul87(6) xor in_mul87(4) xor in_mul87(2) xor in_mul87(1) xor in_mul87(0);
|
| 784 |
|
|
out_mul87(2) <= in_mul87(2) xor in_mul87(0);
|
| 785 |
|
|
out_mul87(3) <= in_mul87(7) xor in_mul87(5);
|
| 786 |
|
|
out_mul87(4) <= in_mul87(6);
|
| 787 |
|
|
out_mul87(5) <= in_mul87(7);
|
| 788 |
|
|
out_mul87(6) <= in_mul87(7) xor in_mul87(5) xor in_mul87(3) xor in_mul87(1);
|
| 789 |
|
|
out_mul87(7) <= in_mul87(6) xor in_mul87(4) xor in_mul87(2) xor in_mul87(0);
|
| 790 |
|
|
end mul87_arch;
|
| 791 |
|
|
|
| 792 |
|
|
|
| 793 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 794 |
|
|
-- --
|
| 795 |
|
|
-- new component --
|
| 796 |
|
|
-- --
|
| 797 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 798 |
|
|
|
| 799 |
|
|
--
|
| 800 |
|
|
-- multiplier by 5a
|
| 801 |
|
|
--
|
| 802 |
|
|
|
| 803 |
|
|
library ieee;
|
| 804 |
|
|
use ieee.std_logic_1164.all;
|
| 805 |
|
|
|
| 806 |
|
|
entity mul5a is
|
| 807 |
|
|
port (
|
| 808 |
|
|
in_mul5a : in std_logic_vector(7 downto 0);
|
| 809 |
|
|
out_mul5a : out std_logic_vector(7 downto 0)
|
| 810 |
|
|
);
|
| 811 |
|
|
end mul5a;
|
| 812 |
|
|
|
| 813 |
|
|
architecture mul5a_arch of mul5a is
|
| 814 |
|
|
begin
|
| 815 |
|
|
out_mul5a(0) <= in_mul5a(7) xor in_mul5a(5) xor in_mul5a(2);
|
| 816 |
|
|
out_mul5a(1) <= in_mul5a(6) xor in_mul5a(3) xor in_mul5a(0);
|
| 817 |
|
|
out_mul5a(2) <= in_mul5a(5) xor in_mul5a(4) xor in_mul5a(2) xor in_mul5a(1);
|
| 818 |
|
|
out_mul5a(3) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(3) xor in_mul5a(0);
|
| 819 |
|
|
out_mul5a(4) <= in_mul5a(7) xor in_mul5a(4) xor in_mul5a(1) xor in_mul5a(0);
|
| 820 |
|
|
out_mul5a(5) <= in_mul5a(5) xor in_mul5a(2) xor in_mul5a(1);
|
| 821 |
|
|
out_mul5a(6) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(5) xor in_mul5a(3) xor in_mul5a(0);
|
| 822 |
|
|
out_mul5a(7) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(4) xor in_mul5a(1);
|
| 823 |
|
|
end mul5a_arch;
|
| 824 |
|
|
|
| 825 |
|
|
|
| 826 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 827 |
|
|
-- --
|
| 828 |
|
|
-- new component --
|
| 829 |
|
|
-- --
|
| 830 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 831 |
|
|
|
| 832 |
|
|
--
|
| 833 |
|
|
-- multiplier by 58
|
| 834 |
|
|
--
|
| 835 |
|
|
|
| 836 |
|
|
library ieee;
|
| 837 |
|
|
use ieee.std_logic_1164.all;
|
| 838 |
|
|
|
| 839 |
|
|
entity mul58 is
|
| 840 |
|
|
port (
|
| 841 |
|
|
in_mul58 : in std_logic_vector(7 downto 0);
|
| 842 |
|
|
out_mul58 : out std_logic_vector(7 downto 0)
|
| 843 |
|
|
);
|
| 844 |
|
|
end mul58;
|
| 845 |
|
|
|
| 846 |
|
|
architecture mul58_arch of mul58 is
|
| 847 |
|
|
begin
|
| 848 |
|
|
out_mul58(0) <= in_mul58(5) xor in_mul58(2);
|
| 849 |
|
|
out_mul58(1) <= in_mul58(6) xor in_mul58(3);
|
| 850 |
|
|
out_mul58(2) <= in_mul58(7) xor in_mul58(5) xor in_mul58(4) xor in_mul58(2);
|
| 851 |
|
|
out_mul58(3) <= in_mul58(6) xor in_mul58(3) xor in_mul58(2) xor in_mul58(0);
|
| 852 |
|
|
out_mul58(4) <= in_mul58(7) xor in_mul58(4) xor in_mul58(3) xor in_mul58(1) xor in_mul58(0);
|
| 853 |
|
|
out_mul58(5) <= in_mul58(5) xor in_mul58(4) xor in_mul58(2) xor in_mul58(1);
|
| 854 |
|
|
out_mul58(6) <= in_mul58(6) xor in_mul58(3) xor in_mul58(0);
|
| 855 |
|
|
out_mul58(7) <= in_mul58(7) xor in_mul58(4) xor in_mul58(1);
|
| 856 |
|
|
end mul58_arch;
|
| 857 |
|
|
|
| 858 |
|
|
|
| 859 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 860 |
|
|
-- --
|
| 861 |
|
|
-- new component --
|
| 862 |
|
|
-- --
|
| 863 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 864 |
|
|
|
| 865 |
|
|
--
|
| 866 |
|
|
-- multiplier by db
|
| 867 |
|
|
--
|
| 868 |
|
|
|
| 869 |
|
|
library ieee;
|
| 870 |
|
|
use ieee.std_logic_1164.all;
|
| 871 |
|
|
|
| 872 |
|
|
entity muldb is
|
| 873 |
|
|
port (
|
| 874 |
|
|
in_muldb : in std_logic_vector(7 downto 0);
|
| 875 |
|
|
out_muldb : out std_logic_vector(7 downto 0)
|
| 876 |
|
|
);
|
| 877 |
|
|
end muldb;
|
| 878 |
|
|
|
| 879 |
|
|
architecture muldb_arch of muldb is
|
| 880 |
|
|
begin
|
| 881 |
|
|
out_muldb(0) <= in_muldb(7) xor in_muldb(6) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
|
| 882 |
|
|
out_muldb(1) <= in_muldb(7) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
|
| 883 |
|
|
out_muldb(2) <= in_muldb(7) xor in_muldb(6) xor in_muldb(5) xor in_muldb(4);
|
| 884 |
|
|
out_muldb(3) <= in_muldb(5) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
|
| 885 |
|
|
out_muldb(4) <= in_muldb(6) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
|
| 886 |
|
|
out_muldb(5) <= in_muldb(7) xor in_muldb(5) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1);
|
| 887 |
|
|
out_muldb(6) <= in_muldb(7) xor in_muldb(5) xor in_muldb(4) xor in_muldb(1) xor in_muldb(0);
|
| 888 |
|
|
out_muldb(7) <= in_muldb(6) xor in_muldb(5) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);
|
| 889 |
|
|
end muldb_arch;
|
| 890 |
|
|
|
| 891 |
|
|
|
| 892 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 893 |
|
|
-- --
|
| 894 |
|
|
-- new component --
|
| 895 |
|
|
-- --
|
| 896 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 897 |
|
|
|
| 898 |
|
|
--
|
| 899 |
|
|
-- multiplier by 9e
|
| 900 |
|
|
--
|
| 901 |
|
|
|
| 902 |
|
|
library ieee;
|
| 903 |
|
|
use ieee.std_logic_1164.all;
|
| 904 |
|
|
|
| 905 |
|
|
entity mul9e is
|
| 906 |
|
|
port (
|
| 907 |
|
|
in_mul9e : in std_logic_vector(7 downto 0);
|
| 908 |
|
|
out_mul9e : out std_logic_vector(7 downto 0)
|
| 909 |
|
|
);
|
| 910 |
|
|
end mul9e;
|
| 911 |
|
|
|
| 912 |
|
|
architecture mul9e_arch of mul9e is
|
| 913 |
|
|
begin
|
| 914 |
|
|
out_mul9e(0) <= in_mul9e(6) xor in_mul9e(4) xor in_mul9e(3) xor in_mul9e(1);
|
| 915 |
|
|
out_mul9e(1) <= in_mul9e(7) xor in_mul9e(5) xor in_mul9e(4) xor in_mul9e(2) xor in_mul9e(0);
|
| 916 |
|
|
out_mul9e(2) <= in_mul9e(5) xor in_mul9e(4) xor in_mul9e(0);
|
| 917 |
|
|
out_mul9e(3) <= in_mul9e(5) xor in_mul9e(4) xor in_mul9e(3) xor in_mul9e(0);
|
| 918 |
|
|
out_mul9e(4) <= in_mul9e(6) xor in_mul9e(5) xor in_mul9e(4) xor in_mul9e(1) xor in_mul9e(0);
|
| 919 |
|
|
out_mul9e(5) <= in_mul9e(7) xor in_mul9e(6) xor in_mul9e(5) xor in_mul9e(2) xor in_mul9e(1);
|
| 920 |
|
|
out_mul9e(6) <= in_mul9e(7) xor in_mul9e(4) xor in_mul9e(2) xor in_mul9e(1);
|
| 921 |
|
|
out_mul9e(7) <= in_mul9e(5) xor in_mul9e(3) xor in_mul9e(2) xor in_mul9e(0);
|
| 922 |
|
|
end mul9e_arch;
|
| 923 |
|
|
|
| 924 |
|
|
|
| 925 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 926 |
|
|
-- --
|
| 927 |
|
|
-- new component --
|
| 928 |
|
|
-- --
|
| 929 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 930 |
|
|
|
| 931 |
|
|
--
|
| 932 |
|
|
-- multiplier by 56
|
| 933 |
|
|
--
|
| 934 |
|
|
|
| 935 |
|
|
library ieee;
|
| 936 |
|
|
use ieee.std_logic_1164.all;
|
| 937 |
|
|
|
| 938 |
|
|
entity mul56 is
|
| 939 |
|
|
port (
|
| 940 |
|
|
in_mul56 : in std_logic_vector(7 downto 0);
|
| 941 |
|
|
out_mul56 : out std_logic_vector(7 downto 0)
|
| 942 |
|
|
);
|
| 943 |
|
|
end mul56;
|
| 944 |
|
|
|
| 945 |
|
|
architecture mul56_arch of mul56 is
|
| 946 |
|
|
begin
|
| 947 |
|
|
out_mul56(0) <= in_mul56(6) xor in_mul56(2);
|
| 948 |
|
|
out_mul56(1) <= in_mul56(7) xor in_mul56(3) xor in_mul56(0);
|
| 949 |
|
|
out_mul56(2) <= in_mul56(6) xor in_mul56(4) xor in_mul56(2) xor in_mul56(1) xor in_mul56(0);
|
| 950 |
|
|
out_mul56(3) <= in_mul56(7) xor in_mul56(6) xor in_mul56(5) xor in_mul56(3) xor in_mul56(1);
|
| 951 |
|
|
out_mul56(4) <= in_mul56(7) xor in_mul56(6) xor in_mul56(4) xor in_mul56(2) xor in_mul56(0);
|
| 952 |
|
|
out_mul56(5) <= in_mul56(7) xor in_mul56(5) xor in_mul56(3) xor in_mul56(1);
|
| 953 |
|
|
out_mul56(6) <= in_mul56(4) xor in_mul56(0);
|
| 954 |
|
|
out_mul56(7) <= in_mul56(5) xor in_mul56(1);
|
| 955 |
|
|
end mul56_arch;
|
| 956 |
|
|
|
| 957 |
|
|
|
| 958 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 959 |
|
|
-- --
|
| 960 |
|
|
-- new component --
|
| 961 |
|
|
-- --
|
| 962 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 963 |
|
|
|
| 964 |
|
|
--
|
| 965 |
|
|
-- multiplier by 82
|
| 966 |
|
|
--
|
| 967 |
|
|
|
| 968 |
|
|
library ieee;
|
| 969 |
|
|
use ieee.std_logic_1164.all;
|
| 970 |
|
|
|
| 971 |
|
|
entity mul82 is
|
| 972 |
|
|
port (
|
| 973 |
|
|
in_mul82 : in std_logic_vector(7 downto 0);
|
| 974 |
|
|
out_mul82 : out std_logic_vector(7 downto 0)
|
| 975 |
|
|
);
|
| 976 |
|
|
end mul82;
|
| 977 |
|
|
|
| 978 |
|
|
architecture mul82_arch of mul82 is
|
| 979 |
|
|
begin
|
| 980 |
|
|
out_mul82(0) <= in_mul82(7) xor in_mul82(6) xor in_mul82(5) xor in_mul82(3) xor in_mul82(1);
|
| 981 |
|
|
out_mul82(1) <= in_mul82(7) xor in_mul82(6) xor in_mul82(4) xor in_mul82(2) xor in_mul82(0);
|
| 982 |
|
|
out_mul82(2) <= in_mul82(6);
|
| 983 |
|
|
out_mul82(3) <= in_mul82(6) xor in_mul82(5) xor in_mul82(3) xor in_mul82(1);
|
| 984 |
|
|
out_mul82(4) <= in_mul82(7) xor in_mul82(6) xor in_mul82(4) xor in_mul82(2);
|
| 985 |
|
|
out_mul82(5) <= in_mul82(7) xor in_mul82(5) xor in_mul82(3);
|
| 986 |
|
|
out_mul82(6) <= in_mul82(7) xor in_mul82(5) xor in_mul82(4) xor in_mul82(3) xor in_mul82(1);
|
| 987 |
|
|
out_mul82(7) <= in_mul82(6) xor in_mul82(5) xor in_mul82(4) xor in_mul82(2) xor in_mul82(0);
|
| 988 |
|
|
end mul82_arch;
|
| 989 |
|
|
|
| 990 |
|
|
|
| 991 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 992 |
|
|
-- --
|
| 993 |
|
|
-- new component --
|
| 994 |
|
|
-- --
|
| 995 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 996 |
|
|
|
| 997 |
|
|
--
|
| 998 |
|
|
-- multiplier by f3
|
| 999 |
|
|
--
|
| 1000 |
|
|
|
| 1001 |
|
|
library ieee;
|
| 1002 |
|
|
use ieee.std_logic_1164.all;
|
| 1003 |
|
|
|
| 1004 |
|
|
entity mulf3 is
|
| 1005 |
|
|
port (
|
| 1006 |
|
|
in_mulf3 : in std_logic_vector(7 downto 0);
|
| 1007 |
|
|
out_mulf3 : out std_logic_vector(7 downto 0)
|
| 1008 |
|
|
);
|
| 1009 |
|
|
end mulf3;
|
| 1010 |
|
|
|
| 1011 |
|
|
architecture mulf3_arch of mulf3 is
|
| 1012 |
|
|
begin
|
| 1013 |
|
|
out_mulf3(0) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(2) xor in_mulf3(1) xor in_mulf3(0);
|
| 1014 |
|
|
out_mulf3(1) <= in_mulf3(7) xor in_mulf3(3) xor in_mulf3(2) xor in_mulf3(1) xor in_mulf3(0);
|
| 1015 |
|
|
out_mulf3(2) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(4) xor in_mulf3(3);
|
| 1016 |
|
|
out_mulf3(3) <= in_mulf3(6) xor in_mulf3(5) xor in_mulf3(4) xor in_mulf3(2) xor in_mulf3(1);
|
| 1017 |
|
|
out_mulf3(4) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(5) xor in_mulf3(3) xor in_mulf3(2) xor in_mulf3(0);
|
| 1018 |
|
|
out_mulf3(5) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(4) xor in_mulf3(3) xor in_mulf3(1) xor in_mulf3(0);
|
| 1019 |
|
|
out_mulf3(6) <= in_mulf3(6) xor in_mulf3(5) xor in_mulf3(4) xor in_mulf3(0);
|
| 1020 |
|
|
out_mulf3(7) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(5) xor in_mulf3(1) xor in_mulf3(0);
|
| 1021 |
|
|
end mulf3_arch;
|
| 1022 |
|
|
|
| 1023 |
|
|
|
| 1024 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1025 |
|
|
-- --
|
| 1026 |
|
|
-- new component --
|
| 1027 |
|
|
-- --
|
| 1028 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1029 |
|
|
|
| 1030 |
|
|
--
|
| 1031 |
|
|
-- multiplier by 1e
|
| 1032 |
|
|
--
|
| 1033 |
|
|
|
| 1034 |
|
|
|
| 1035 |
|
|
library ieee;
|
| 1036 |
|
|
use ieee.std_logic_1164.all;
|
| 1037 |
|
|
|
| 1038 |
|
|
entity mul1e is
|
| 1039 |
|
|
port (
|
| 1040 |
|
|
in_mul1e : in std_logic_vector(7 downto 0);
|
| 1041 |
|
|
out_mul1e : out std_logic_vector(7 downto 0)
|
| 1042 |
|
|
);
|
| 1043 |
|
|
end mul1e;
|
| 1044 |
|
|
|
| 1045 |
|
|
architecture mul1e_arch of mul1e is
|
| 1046 |
|
|
begin
|
| 1047 |
|
|
out_mul1e(0) <= in_mul1e(5) xor in_mul1e(4);
|
| 1048 |
|
|
out_mul1e(1) <= in_mul1e(6) xor in_mul1e(5) xor in_mul1e(0);
|
| 1049 |
|
|
out_mul1e(2) <= in_mul1e(7) xor in_mul1e(6) xor in_mul1e(5) xor in_mul1e(4) xor in_mul1e(1) xor in_mul1e(0);
|
| 1050 |
|
|
out_mul1e(3) <= in_mul1e(7) xor in_mul1e(6) xor in_mul1e(4) xor in_mul1e(2) xor in_mul1e(1) xor in_mul1e(0);
|
| 1051 |
|
|
out_mul1e(4) <= in_mul1e(7) xor in_mul1e(5) xor in_mul1e(3) xor in_mul1e(2) xor in_mul1e(1) xor in_mul1e(0);
|
| 1052 |
|
|
out_mul1e(5) <= in_mul1e(6) xor in_mul1e(4) xor in_mul1e(3) xor in_mul1e(2) xor in_mul1e(1);
|
| 1053 |
|
|
out_mul1e(6) <= in_mul1e(7) xor in_mul1e(3) xor in_mul1e(2);
|
| 1054 |
|
|
out_mul1e(7) <= in_mul1e(4) xor in_mul1e(3);
|
| 1055 |
|
|
end mul1e_arch;
|
| 1056 |
|
|
|
| 1057 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1058 |
|
|
-- --
|
| 1059 |
|
|
-- new component --
|
| 1060 |
|
|
-- --
|
| 1061 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1062 |
|
|
|
| 1063 |
|
|
--
|
| 1064 |
|
|
-- multiplier by c6
|
| 1065 |
|
|
--
|
| 1066 |
|
|
|
| 1067 |
|
|
library ieee;
|
| 1068 |
|
|
use ieee.std_logic_1164.all;
|
| 1069 |
|
|
|
| 1070 |
|
|
entity mulc6 is
|
| 1071 |
|
|
port (
|
| 1072 |
|
|
in_mulc6 : in std_logic_vector(7 downto 0);
|
| 1073 |
|
|
out_mulc6 : out std_logic_vector(7 downto 0)
|
| 1074 |
|
|
);
|
| 1075 |
|
|
end mulc6;
|
| 1076 |
|
|
|
| 1077 |
|
|
architecture mulc6_arch of mulc6 is
|
| 1078 |
|
|
begin
|
| 1079 |
|
|
out_mulc6(0) <= in_mulc6(6) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(1);
|
| 1080 |
|
|
out_mulc6(1) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(0);
|
| 1081 |
|
|
out_mulc6(2) <= in_mulc6(7) xor in_mulc6(2) xor in_mulc6(0);
|
| 1082 |
|
|
out_mulc6(3) <= in_mulc6(6) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(2);
|
| 1083 |
|
|
out_mulc6(4) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(5) xor in_mulc6(3);
|
| 1084 |
|
|
out_mulc6(5) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(4);
|
| 1085 |
|
|
out_mulc6(6) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(1) xor in_mulc6(0);
|
| 1086 |
|
|
out_mulc6(7) <= in_mulc6(7) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(1) xor in_mulc6(0);
|
| 1087 |
|
|
end mulc6_arch;
|
| 1088 |
|
|
|
| 1089 |
|
|
|
| 1090 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1091 |
|
|
-- --
|
| 1092 |
|
|
-- new component --
|
| 1093 |
|
|
-- --
|
| 1094 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1095 |
|
|
|
| 1096 |
|
|
--
|
| 1097 |
|
|
-- multiplier by 68
|
| 1098 |
|
|
--
|
| 1099 |
|
|
|
| 1100 |
|
|
library ieee;
|
| 1101 |
|
|
use ieee.std_logic_1164.all;
|
| 1102 |
|
|
|
| 1103 |
|
|
entity mul68 is
|
| 1104 |
|
|
port (
|
| 1105 |
|
|
in_mul68 : in std_logic_vector(7 downto 0);
|
| 1106 |
|
|
out_mul68 : out std_logic_vector(7 downto 0)
|
| 1107 |
|
|
);
|
| 1108 |
|
|
end mul68;
|
| 1109 |
|
|
|
| 1110 |
|
|
|
| 1111 |
|
|
architecture mul68_arch of mul68 is
|
| 1112 |
|
|
begin
|
| 1113 |
|
|
out_mul68(0) <= in_mul68(7) xor in_mul68(6) xor in_mul68(4) xor in_mul68(3) xor in_mul68(2);
|
| 1114 |
|
|
out_mul68(1) <= in_mul68(7) xor in_mul68(5) xor in_mul68(4) xor in_mul68(3);
|
| 1115 |
|
|
out_mul68(2) <= in_mul68(7) xor in_mul68(5) xor in_mul68(3) xor in_mul68(2);
|
| 1116 |
|
|
out_mul68(3) <= in_mul68(7) xor in_mul68(2) xor in_mul68(0);
|
| 1117 |
|
|
out_mul68(4) <= in_mul68(3) xor in_mul68(1);
|
| 1118 |
|
|
out_mul68(5) <= in_mul68(4) xor in_mul68(2) xor in_mul68(0);
|
| 1119 |
|
|
out_mul68(6) <= in_mul68(7) xor in_mul68(6) xor in_mul68(5) xor in_mul68(4) xor in_mul68(2) xor in_mul68(1) xor in_mul68(0);
|
| 1120 |
|
|
out_mul68(7) <= in_mul68(7) xor in_mul68(6) xor in_mul68(5) xor in_mul68(3) xor in_mul68(2) xor in_mul68(1);
|
| 1121 |
|
|
end mul68_arch;
|
| 1122 |
|
|
|
| 1123 |
|
|
|
| 1124 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1125 |
|
|
-- --
|
| 1126 |
|
|
-- new component --
|
| 1127 |
|
|
-- --
|
| 1128 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1129 |
|
|
|
| 1130 |
|
|
--
|
| 1131 |
|
|
-- multiplier by e5
|
| 1132 |
|
|
--
|
| 1133 |
|
|
|
| 1134 |
|
|
library ieee;
|
| 1135 |
|
|
use ieee.std_logic_1164.all;
|
| 1136 |
|
|
|
| 1137 |
|
|
entity mule5 is
|
| 1138 |
|
|
port (
|
| 1139 |
|
|
in_mule5 : in std_logic_vector(7 downto 0);
|
| 1140 |
|
|
out_mule5 : out std_logic_vector(7 downto 0)
|
| 1141 |
|
|
);
|
| 1142 |
|
|
end mule5;
|
| 1143 |
|
|
|
| 1144 |
|
|
|
| 1145 |
|
|
architecture mule5_arch of mule5 is
|
| 1146 |
|
|
begin
|
| 1147 |
|
|
out_mule5(0) <= in_mule5(6) xor in_mule5(4) xor in_mule5(2) xor in_mule5(1) xor in_mule5(0);
|
| 1148 |
|
|
out_mule5(1) <= in_mule5(7) xor in_mule5(5) xor in_mule5(3) xor in_mule5(2) xor in_mule5(1);
|
| 1149 |
|
|
out_mule5(2) <= in_mule5(3) xor in_mule5(1) xor in_mule5(0);
|
| 1150 |
|
|
out_mule5(3) <= in_mule5(6);
|
| 1151 |
|
|
out_mule5(4) <= in_mule5(7);
|
| 1152 |
|
|
out_mule5(5) <= in_mule5(0);
|
| 1153 |
|
|
out_mule5(6) <= in_mule5(6) xor in_mule5(4) xor in_mule5(2) xor in_mule5(0);
|
| 1154 |
|
|
out_mule5(7) <= in_mule5(7) xor in_mule5(5) xor in_mule5(3) xor in_mule5(1) xor in_mule5(0);
|
| 1155 |
|
|
end mule5_arch;
|
| 1156 |
|
|
|
| 1157 |
|
|
|
| 1158 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1159 |
|
|
-- --
|
| 1160 |
|
|
-- new component --
|
| 1161 |
|
|
-- --
|
| 1162 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1163 |
|
|
|
| 1164 |
|
|
--
|
| 1165 |
|
|
-- multiplier by 02
|
| 1166 |
|
|
--
|
| 1167 |
|
|
|
| 1168 |
|
|
library ieee;
|
| 1169 |
|
|
use ieee.std_logic_1164.all;
|
| 1170 |
|
|
|
| 1171 |
|
|
entity mul02 is
|
| 1172 |
|
|
port (
|
| 1173 |
|
|
in_mul02 : in std_logic_vector(7 downto 0);
|
| 1174 |
|
|
out_mul02 : out std_logic_vector(7 downto 0)
|
| 1175 |
|
|
);
|
| 1176 |
|
|
end mul02;
|
| 1177 |
|
|
|
| 1178 |
|
|
|
| 1179 |
|
|
architecture mul02_arch of mul02 is
|
| 1180 |
|
|
begin
|
| 1181 |
|
|
out_mul02(0) <= in_mul02(7);
|
| 1182 |
|
|
out_mul02(1) <= in_mul02(0);
|
| 1183 |
|
|
out_mul02(2) <= in_mul02(7) xor in_mul02(1);
|
| 1184 |
|
|
out_mul02(3) <= in_mul02(7) xor in_mul02(2);
|
| 1185 |
|
|
out_mul02(4) <= in_mul02(3);
|
| 1186 |
|
|
out_mul02(5) <= in_mul02(4);
|
| 1187 |
|
|
out_mul02(6) <= in_mul02(7) xor in_mul02(5);
|
| 1188 |
|
|
out_mul02(7) <= in_mul02(6);
|
| 1189 |
|
|
end mul02_arch;
|
| 1190 |
|
|
|
| 1191 |
|
|
|
| 1192 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1193 |
|
|
-- --
|
| 1194 |
|
|
-- new component --
|
| 1195 |
|
|
-- --
|
| 1196 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1197 |
|
|
|
| 1198 |
|
|
--
|
| 1199 |
|
|
-- multiplier by a1
|
| 1200 |
|
|
--
|
| 1201 |
|
|
|
| 1202 |
|
|
library ieee;
|
| 1203 |
|
|
use ieee.std_logic_1164.all;
|
| 1204 |
|
|
|
| 1205 |
|
|
entity mula1 is
|
| 1206 |
|
|
port (
|
| 1207 |
|
|
in_mula1 : in std_logic_vector(7 downto 0);
|
| 1208 |
|
|
out_mula1 : out std_logic_vector(7 downto 0)
|
| 1209 |
|
|
);
|
| 1210 |
|
|
end mula1;
|
| 1211 |
|
|
|
| 1212 |
|
|
architecture mula1_arch of mula1 is
|
| 1213 |
|
|
begin
|
| 1214 |
|
|
out_mula1(0) <= in_mula1(7) xor in_mula1(6) xor in_mula1(1) xor in_mula1(0);
|
| 1215 |
|
|
out_mula1(1) <= in_mula1(7) xor in_mula1(2) xor in_mula1(1);
|
| 1216 |
|
|
out_mula1(2) <= in_mula1(7) xor in_mula1(6) xor in_mula1(3) xor in_mula1(2) xor in_mula1(1);
|
| 1217 |
|
|
out_mula1(3) <= in_mula1(6) xor in_mula1(4) xor in_mula1(3) xor in_mula1(2) xor in_mula1(1);
|
| 1218 |
|
|
out_mula1(4) <= in_mula1(7) xor in_mula1(5) xor in_mula1(4) xor in_mula1(3) xor in_mula1(2);
|
| 1219 |
|
|
out_mula1(5) <= in_mula1(6) xor in_mula1(5) xor in_mula1(4) xor in_mula1(3) xor in_mula1(0);
|
| 1220 |
|
|
out_mula1(6) <= in_mula1(5) xor in_mula1(4);
|
| 1221 |
|
|
out_mula1(7) <= in_mula1(6) xor in_mula1(5) xor in_mula1(0);
|
| 1222 |
|
|
end mula1_arch;
|
| 1223 |
|
|
|
| 1224 |
|
|
|
| 1225 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1226 |
|
|
-- --
|
| 1227 |
|
|
-- new component --
|
| 1228 |
|
|
-- --
|
| 1229 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1230 |
|
|
|
| 1231 |
|
|
--
|
| 1232 |
|
|
-- multiplier by fc
|
| 1233 |
|
|
--
|
| 1234 |
|
|
|
| 1235 |
|
|
library ieee;
|
| 1236 |
|
|
use ieee.std_logic_1164.all;
|
| 1237 |
|
|
|
| 1238 |
|
|
entity mulfc is
|
| 1239 |
|
|
port (
|
| 1240 |
|
|
in_mulfc : in std_logic_vector(7 downto 0);
|
| 1241 |
|
|
out_mulfc : out std_logic_vector(7 downto 0)
|
| 1242 |
|
|
);
|
| 1243 |
|
|
end mulfc;
|
| 1244 |
|
|
|
| 1245 |
|
|
|
| 1246 |
|
|
architecture mulfc_arch of mulfc is
|
| 1247 |
|
|
begin
|
| 1248 |
|
|
out_mulfc(0) <= in_mulfc(7) xor in_mulfc(5) xor in_mulfc(2) xor in_mulfc(1);
|
| 1249 |
|
|
out_mulfc(1) <= in_mulfc(6) xor in_mulfc(3) xor in_mulfc(2);
|
| 1250 |
|
|
out_mulfc(2) <= in_mulfc(5) xor in_mulfc(4) xor in_mulfc(3) xor in_mulfc(2) xor in_mulfc(1) xor in_mulfc(0);
|
| 1251 |
|
|
out_mulfc(3) <= in_mulfc(7) xor in_mulfc(6) xor in_mulfc(4) xor in_mulfc(3) xor in_mulfc(0);
|
| 1252 |
|
|
out_mulfc(4) <= in_mulfc(7) xor in_mulfc(5) xor in_mulfc(4) xor in_mulfc(1) xor in_mulfc(0);
|
| 1253 |
|
|
out_mulfc(5) <= in_mulfc(6) xor in_mulfc(5) xor in_mulfc(2) xor in_mulfc(1) xor in_mulfc(0);
|
| 1254 |
|
|
out_mulfc(6) <= in_mulfc(6) xor in_mulfc(5) xor in_mulfc(3) xor in_mulfc(0);
|
| 1255 |
|
|
out_mulfc(7) <= in_mulfc(7) xor in_mulfc(6) xor in_mulfc(4) xor in_mulfc(1) xor in_mulfc(0);
|
| 1256 |
|
|
end mulfc_arch;
|
| 1257 |
|
|
|
| 1258 |
|
|
|
| 1259 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1260 |
|
|
-- --
|
| 1261 |
|
|
-- new component --
|
| 1262 |
|
|
-- --
|
| 1263 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1264 |
|
|
|
| 1265 |
|
|
--
|
| 1266 |
|
|
-- multiplier by c1
|
| 1267 |
|
|
--
|
| 1268 |
|
|
|
| 1269 |
|
|
library ieee;
|
| 1270 |
|
|
use ieee.std_logic_1164.all;
|
| 1271 |
|
|
|
| 1272 |
|
|
entity mulc1 is
|
| 1273 |
|
|
port (
|
| 1274 |
|
|
in_mulc1 : in std_logic_vector(7 downto 0);
|
| 1275 |
|
|
out_mulc1 : out std_logic_vector(7 downto 0)
|
| 1276 |
|
|
);
|
| 1277 |
|
|
end mulc1;
|
| 1278 |
|
|
|
| 1279 |
|
|
|
| 1280 |
|
|
architecture mulc1_arch of mulc1 is
|
| 1281 |
|
|
begin
|
| 1282 |
|
|
out_mulc1(0) <= in_mulc1(7) xor in_mulc1(5) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1) xor in_mulc1(0);
|
| 1283 |
|
|
out_mulc1(1) <= in_mulc1(6) xor in_mulc1(5) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1);
|
| 1284 |
|
|
out_mulc1(2) <= in_mulc1(6) xor in_mulc1(1);
|
| 1285 |
|
|
out_mulc1(3) <= in_mulc1(5) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(1);
|
| 1286 |
|
|
out_mulc1(4) <= in_mulc1(6) xor in_mulc1(5) xor in_mulc1(4) xor in_mulc1(2);
|
| 1287 |
|
|
out_mulc1(5) <= in_mulc1(7) xor in_mulc1(6) xor in_mulc1(5) xor in_mulc1(3);
|
| 1288 |
|
|
out_mulc1(6) <= in_mulc1(6) xor in_mulc1(5) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1) xor in_mulc1(0);
|
| 1289 |
|
|
out_mulc1(7) <= in_mulc1(7) xor in_mulc1(6) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1) xor in_mulc1(0);
|
| 1290 |
|
|
end mulc1_arch;
|
| 1291 |
|
|
|
| 1292 |
|
|
|
| 1293 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1294 |
|
|
-- --
|
| 1295 |
|
|
-- new component --
|
| 1296 |
|
|
-- --
|
| 1297 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1298 |
|
|
|
| 1299 |
|
|
--
|
| 1300 |
|
|
-- multiplier by 47
|
| 1301 |
|
|
--
|
| 1302 |
|
|
|
| 1303 |
|
|
library ieee;
|
| 1304 |
|
|
use ieee.std_logic_1164.all;
|
| 1305 |
|
|
|
| 1306 |
|
|
entity mul47 is
|
| 1307 |
|
|
port (
|
| 1308 |
|
|
in_mul47 : in std_logic_vector(7 downto 0);
|
| 1309 |
|
|
out_mul47 : out std_logic_vector(7 downto 0)
|
| 1310 |
|
|
);
|
| 1311 |
|
|
end mul47;
|
| 1312 |
|
|
|
| 1313 |
|
|
architecture mul47_arch of mul47 is
|
| 1314 |
|
|
begin
|
| 1315 |
|
|
out_mul47(0) <= in_mul47(4) xor in_mul47(2) xor in_mul47(0);
|
| 1316 |
|
|
out_mul47(1) <= in_mul47(5) xor in_mul47(3) xor in_mul47(1) xor in_mul47(0);
|
| 1317 |
|
|
out_mul47(2) <= in_mul47(6) xor in_mul47(1) xor in_mul47(0);
|
| 1318 |
|
|
out_mul47(3) <= in_mul47(7) xor in_mul47(4) xor in_mul47(1);
|
| 1319 |
|
|
out_mul47(4) <= in_mul47(5) xor in_mul47(2);
|
| 1320 |
|
|
out_mul47(5) <= in_mul47(6) xor in_mul47(3);
|
| 1321 |
|
|
out_mul47(6) <= in_mul47(7) xor in_mul47(2) xor in_mul47(0);
|
| 1322 |
|
|
out_mul47(7) <= in_mul47(3) xor in_mul47(1);
|
| 1323 |
|
|
end mul47_arch;
|
| 1324 |
|
|
|
| 1325 |
|
|
|
| 1326 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1327 |
|
|
-- --
|
| 1328 |
|
|
-- new component --
|
| 1329 |
|
|
-- --
|
| 1330 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1331 |
|
|
|
| 1332 |
|
|
--
|
| 1333 |
|
|
-- multiplier by ae
|
| 1334 |
|
|
--
|
| 1335 |
|
|
|
| 1336 |
|
|
library ieee;
|
| 1337 |
|
|
use ieee.std_logic_1164.all;
|
| 1338 |
|
|
|
| 1339 |
|
|
entity mulae is
|
| 1340 |
|
|
port (
|
| 1341 |
|
|
in_mulae : in std_logic_vector(7 downto 0);
|
| 1342 |
|
|
out_mulae : out std_logic_vector(7 downto 0)
|
| 1343 |
|
|
);
|
| 1344 |
|
|
end mulae;
|
| 1345 |
|
|
|
| 1346 |
|
|
architecture mulae_arch of mulae is
|
| 1347 |
|
|
begin
|
| 1348 |
|
|
out_mulae(0) <= in_mulae(7) xor in_mulae(5) xor in_mulae(1);
|
| 1349 |
|
|
out_mulae(1) <= in_mulae(6) xor in_mulae(2) xor in_mulae(0);
|
| 1350 |
|
|
out_mulae(2) <= in_mulae(5) xor in_mulae(3) xor in_mulae(0);
|
| 1351 |
|
|
out_mulae(3) <= in_mulae(7) xor in_mulae(6) xor in_mulae(5) xor in_mulae(4) xor in_mulae(0);
|
| 1352 |
|
|
out_mulae(4) <= in_mulae(7) xor in_mulae(6) xor in_mulae(5) xor in_mulae(1);
|
| 1353 |
|
|
out_mulae(5) <= in_mulae(7) xor in_mulae(6) xor in_mulae(2) xor in_mulae(0);
|
| 1354 |
|
|
out_mulae(6) <= in_mulae(5) xor in_mulae(3);
|
| 1355 |
|
|
out_mulae(7) <= in_mulae(6) xor in_mulae(4) xor in_mulae(0);
|
| 1356 |
|
|
end mulae_arch;
|
| 1357 |
|
|
|
| 1358 |
|
|
|
| 1359 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1360 |
|
|
-- --
|
| 1361 |
|
|
-- new component --
|
| 1362 |
|
|
-- --
|
| 1363 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1364 |
|
|
|
| 1365 |
|
|
--
|
| 1366 |
|
|
-- multiplier by 3d
|
| 1367 |
|
|
--
|
| 1368 |
|
|
|
| 1369 |
|
|
library ieee;
|
| 1370 |
|
|
use ieee.std_logic_1164.all;
|
| 1371 |
|
|
|
| 1372 |
|
|
entity mul3d is
|
| 1373 |
|
|
port (
|
| 1374 |
|
|
in_mul3d : in std_logic_vector(7 downto 0);
|
| 1375 |
|
|
out_mul3d : out std_logic_vector(7 downto 0)
|
| 1376 |
|
|
);
|
| 1377 |
|
|
end mul3d;
|
| 1378 |
|
|
|
| 1379 |
|
|
architecture mul3d_arch of mul3d is
|
| 1380 |
|
|
begin
|
| 1381 |
|
|
out_mul3d(0) <= in_mul3d(4) xor in_mul3d(3) xor in_mul3d(0);
|
| 1382 |
|
|
out_mul3d(1) <= in_mul3d(5) xor in_mul3d(4) xor in_mul3d(1);
|
| 1383 |
|
|
out_mul3d(2) <= in_mul3d(6) xor in_mul3d(5) xor in_mul3d(4) xor in_mul3d(3) xor in_mul3d(2) xor in_mul3d(0);
|
| 1384 |
|
|
out_mul3d(3) <= in_mul3d(7) xor in_mul3d(6) xor in_mul3d(5) xor in_mul3d(1) xor in_mul3d(0);
|
| 1385 |
|
|
out_mul3d(4) <= in_mul3d(7) xor in_mul3d(6) xor in_mul3d(2) xor in_mul3d(1) xor in_mul3d(0);
|
| 1386 |
|
|
out_mul3d(5) <= in_mul3d(7) xor in_mul3d(3) xor in_mul3d(2) xor in_mul3d(1) xor in_mul3d(0);
|
| 1387 |
|
|
out_mul3d(6) <= in_mul3d(2) xor in_mul3d(1);
|
| 1388 |
|
|
out_mul3d(7) <= in_mul3d(3) xor in_mul3d(2);
|
| 1389 |
|
|
end mul3d_arch;
|
| 1390 |
|
|
|
| 1391 |
|
|
|
| 1392 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1393 |
|
|
-- --
|
| 1394 |
|
|
-- new component --
|
| 1395 |
|
|
-- --
|
| 1396 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1397 |
|
|
|
| 1398 |
|
|
--
|
| 1399 |
|
|
-- multiplier by 19
|
| 1400 |
|
|
--
|
| 1401 |
|
|
|
| 1402 |
|
|
library ieee;
|
| 1403 |
|
|
use ieee.std_logic_1164.all;
|
| 1404 |
|
|
|
| 1405 |
|
|
entity mul19 is
|
| 1406 |
|
|
port (
|
| 1407 |
|
|
in_mul19 : in std_logic_vector(7 downto 0);
|
| 1408 |
|
|
out_mul19 : out std_logic_vector(7 downto 0)
|
| 1409 |
|
|
);
|
| 1410 |
|
|
end mul19;
|
| 1411 |
|
|
|
| 1412 |
|
|
architecture mul19_arch of mul19 is
|
| 1413 |
|
|
begin
|
| 1414 |
|
|
out_mul19(0) <= in_mul19(7) xor in_mul19(6) xor in_mul19(5) xor in_mul19(4) xor in_mul19(0);
|
| 1415 |
|
|
out_mul19(1) <= in_mul19(7) xor in_mul19(6) xor in_mul19(5) xor in_mul19(1);
|
| 1416 |
|
|
out_mul19(2) <= in_mul19(5) xor in_mul19(4) xor in_mul19(2);
|
| 1417 |
|
|
out_mul19(3) <= in_mul19(7) xor in_mul19(4) xor in_mul19(3) xor in_mul19(0);
|
| 1418 |
|
|
out_mul19(4) <= in_mul19(5) xor in_mul19(4) xor in_mul19(1) xor in_mul19(0);
|
| 1419 |
|
|
out_mul19(5) <= in_mul19(6) xor in_mul19(5) xor in_mul19(2) xor in_mul19(1);
|
| 1420 |
|
|
out_mul19(6) <= in_mul19(5) xor in_mul19(4) xor in_mul19(3) xor in_mul19(2);
|
| 1421 |
|
|
out_mul19(7) <= in_mul19(6) xor in_mul19(5) xor in_mul19(4) xor in_mul19(3);
|
| 1422 |
|
|
end mul19_arch;
|
| 1423 |
|
|
|
| 1424 |
|
|
|
| 1425 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1426 |
|
|
-- --
|
| 1427 |
|
|
-- new component --
|
| 1428 |
|
|
-- --
|
| 1429 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1430 |
|
|
|
| 1431 |
|
|
--
|
| 1432 |
|
|
-- multiplier by 03
|
| 1433 |
|
|
--
|
| 1434 |
|
|
|
| 1435 |
|
|
library ieee;
|
| 1436 |
|
|
use ieee.std_logic_1164.all;
|
| 1437 |
|
|
|
| 1438 |
|
|
entity mul03 is
|
| 1439 |
|
|
port (
|
| 1440 |
|
|
in_mul03 : in std_logic_vector(7 downto 0);
|
| 1441 |
|
|
out_mul03 : out std_logic_vector(7 downto 0)
|
| 1442 |
|
|
);
|
| 1443 |
|
|
end mul03;
|
| 1444 |
|
|
|
| 1445 |
|
|
architecture mul03_arch of mul03 is
|
| 1446 |
|
|
begin
|
| 1447 |
|
|
out_mul03(0) <= in_mul03(7) xor in_mul03(0);
|
| 1448 |
|
|
out_mul03(1) <= in_mul03(1) xor in_mul03(0);
|
| 1449 |
|
|
out_mul03(2) <= in_mul03(7) xor in_mul03(2) xor in_mul03(1);
|
| 1450 |
|
|
out_mul03(3) <= in_mul03(7) xor in_mul03(3) xor in_mul03(2);
|
| 1451 |
|
|
out_mul03(4) <= in_mul03(4) xor in_mul03(3);
|
| 1452 |
|
|
out_mul03(5) <= in_mul03(5) xor in_mul03(4);
|
| 1453 |
|
|
out_mul03(6) <= in_mul03(7) xor in_mul03(6) xor in_mul03(5);
|
| 1454 |
|
|
out_mul03(7) <= in_mul03(7) xor in_mul03(6);
|
| 1455 |
|
|
end mul03_arch;
|
| 1456 |
|
|
|
| 1457 |
|
|
|
| 1458 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1459 |
|
|
-- --
|
| 1460 |
|
|
-- new component --
|
| 1461 |
|
|
-- --
|
| 1462 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1463 |
|
|
|
| 1464 |
|
|
--
|
| 1465 |
|
|
-- twofish data input is the component
|
| 1466 |
|
|
-- that transforms the data input to the
|
| 1467 |
|
|
-- first round to the wanted form as is
|
| 1468 |
|
|
-- described in the twofish prototype
|
| 1469 |
|
|
--
|
| 1470 |
|
|
|
| 1471 |
|
|
library ieee;
|
| 1472 |
|
|
use ieee.std_logic_1164.all;
|
| 1473 |
|
|
|
| 1474 |
|
|
entity twofish_data_input is
|
| 1475 |
|
|
port (
|
| 1476 |
|
|
in_tdi : in std_logic_vector(127 downto 0);
|
| 1477 |
|
|
out_tdi : out std_logic_vector(127 downto 0)
|
| 1478 |
|
|
);
|
| 1479 |
|
|
end twofish_data_input;
|
| 1480 |
|
|
|
| 1481 |
|
|
architecture twofish_data_input_arch of twofish_data_input is
|
| 1482 |
|
|
|
| 1483 |
|
|
-- we declare internal signals
|
| 1484 |
|
|
signal byte0, byte1, byte2, byte3,
|
| 1485 |
|
|
byte4, byte5, byte6,
|
| 1486 |
|
|
byte7, byte8, byte9,
|
| 1487 |
|
|
byte10, byte11, byte12,
|
| 1488 |
|
|
byte13, byte14, byte15 : std_logic_vector(7 downto 0);
|
| 1489 |
|
|
signal P0, P1, P2, P3 : std_logic_vector(31 downto 0);
|
| 1490 |
|
|
|
| 1491 |
|
|
begin
|
| 1492 |
|
|
|
| 1493 |
|
|
-- we assign the input signal to the respective
|
| 1494 |
|
|
-- bytes as is described in the prototype
|
| 1495 |
|
|
byte15 <= in_tdi(7 downto 0);
|
| 1496 |
|
|
byte14 <= in_tdi(15 downto 8);
|
| 1497 |
|
|
byte13 <= in_tdi(23 downto 16);
|
| 1498 |
|
|
byte12 <= in_tdi(31 downto 24);
|
| 1499 |
|
|
byte11 <= in_tdi(39 downto 32);
|
| 1500 |
|
|
byte10 <= in_tdi(47 downto 40);
|
| 1501 |
|
|
byte9 <= in_tdi(55 downto 48);
|
| 1502 |
|
|
byte8 <= in_tdi(63 downto 56);
|
| 1503 |
|
|
byte7 <= in_tdi(71 downto 64);
|
| 1504 |
|
|
byte6 <= in_tdi(79 downto 72);
|
| 1505 |
|
|
byte5 <= in_tdi(87 downto 80);
|
| 1506 |
|
|
byte4 <= in_tdi(95 downto 88);
|
| 1507 |
|
|
byte3 <= in_tdi(103 downto 96);
|
| 1508 |
|
|
byte2 <= in_tdi(111 downto 104);
|
| 1509 |
|
|
byte1 <= in_tdi(119 downto 112);
|
| 1510 |
|
|
byte0 <= in_tdi(127 downto 120);
|
| 1511 |
|
|
|
| 1512 |
|
|
-- we rearrange the bytes and send them to exit
|
| 1513 |
|
|
P0 <= byte3 & byte2 & byte1 & byte0;
|
| 1514 |
|
|
P1 <= byte7 & byte6 & byte5 & byte4;
|
| 1515 |
|
|
P2 <= byte11 & byte10 & byte9 & byte8;
|
| 1516 |
|
|
P3 <= byte15 & byte14 & byte13 & byte12;
|
| 1517 |
|
|
|
| 1518 |
|
|
out_tdi <= P0 & P1 & P2 & P3;
|
| 1519 |
|
|
|
| 1520 |
|
|
end twofish_data_input_arch;
|
| 1521 |
|
|
|
| 1522 |
|
|
|
| 1523 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1524 |
|
|
-- --
|
| 1525 |
|
|
-- new component --
|
| 1526 |
|
|
-- --
|
| 1527 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 1528 |
|
|
|
| 1529 |
|
|
|
| 1530 |
|
|
--
|
| 1531 |
|
|
-- twofish data output is the component
|
| 1532 |
|
|
-- that transforms the data output from the
|
| 1533 |
|
|
-- 16th round to the wanted form as is
|
| 1534 |
|
|
-- described in the twofish prototype
|
| 1535 |
|
|
--
|
| 1536 |
|
|
|
| 1537 |
|
|
library ieee;
|
| 1538 |
|
|
use ieee.std_logic_1164.all;
|
| 1539 |
|
|
|
| 1540 |
|
|
entity twofish_data_output is
|
| 1541 |
|
|
port (
|
| 1542 |
|
|
in_tdo : in std_logic_vector(127 downto 0);
|
| 1543 |
|
|
out_tdo : out std_logic_vector(127 downto 0)
|
| 1544 |
|
|
);
|
| 1545 |
|
|
end twofish_data_output;
|
| 1546 |
|
|
|
| 1547 |
|
|
architecture twofish_data_output_arch of twofish_data_output is
|
| 1548 |
|
|
|
| 1549 |
|
|
-- we declare internal signals
|
| 1550 |
|
|
signal byte0, byte1, byte2, byte3,
|
| 1551 |
|
|
byte4, byte5, byte6,
|
| 1552 |
|
|
byte7, byte8, byte9,
|
| 1553 |
|
|
byte10, byte11, byte12,
|
| 1554 |
|
|
byte13, byte14, byte15 : std_logic_vector(7 downto 0);
|
| 1555 |
|
|
signal C0, C1, C2, C3 : std_logic_vector(31 downto 0);
|
| 1556 |
|
|
|
| 1557 |
|
|
begin
|
| 1558 |
|
|
|
| 1559 |
|
|
-- we assign the input signal to the respective
|
| 1560 |
|
|
-- bytes as is described in the prototype
|
| 1561 |
|
|
byte15 <= in_tdo(7 downto 0);
|
| 1562 |
|
|
byte14 <= in_tdo(15 downto 8);
|
| 1563 |
|
|
byte13 <= in_tdo(23 downto 16);
|
| 1564 |
|
|
byte12 <= in_tdo(31 downto 24);
|
| 1565 |
|
|
byte11 <= in_tdo(39 downto 32);
|
| 1566 |
|
|
byte10 <= in_tdo(47 downto 40);
|
| 1567 |
|
|
byte9 <= in_tdo(55 downto 48);
|
| 1568 |
|
|
byte8 <= in_tdo(63 downto 56);
|
| 1569 |
|
|
byte7 <= in_tdo(71 downto 64);
|
| 1570 |
|
|
byte6 <= in_tdo(79 downto 72);
|
| 1571 |
|
|
byte5 <= in_tdo(87 downto 80);
|
| 1572 |
|
|
byte4 <= in_tdo(95 downto 88);
|
| 1573 |
|
|
byte3 <= in_tdo(103 downto 96);
|
| 1574 |
|
|
byte2 <= in_tdo(111 downto 104);
|
| 1575 |
|
|
byte1 <= in_tdo(119 downto 112);
|
| 1576 |
|
|
byte0 <= in_tdo(127 downto 120);
|
| 1577 |
|
|
|
| 1578 |
|
|
-- we rearrange the bytes and send them to exit
|
| 1579 |
|
|
C0 <= byte3 & byte2 & byte1 & byte0;
|
| 1580 |
|
|
C1 <= byte7 & byte6 & byte5 & byte4;
|
| 1581 |
|
|
C2 <= byte11 & byte10 & byte9 & byte8;
|
| 1582 |
|
|
C3 <= byte15 & byte14 & byte13 & byte12;
|
| 1583 |
|
|
|
| 1584 |
|
|
out_tdo <= C0 & C1 & C2 & C3;
|
| 1585 |
|
|
|
| 1586 |
|
|
end twofish_data_output_arch;
|
| 1587 |
|
|
|
| 1588 |
|
|
-- =======-======================================= --
|
| 1589 |
|
|
-- =============================================== --
|
| 1590 |
|
|
-- --
|
| 1591 |
|
|
-- second part: 128 key input dependent components --
|
| 1592 |
|
|
-- --
|
| 1593 |
|
|
-- =============================================== --
|
| 1594 |
|
|
-- =============================================== --
|
| 1595 |
|
|
|
| 1596 |
|
|
|
| 1597 |
|
|
--
|
| 1598 |
|
|
-- reed solomon for 128bits key
|
| 1599 |
|
|
--
|
| 1600 |
|
|
|
| 1601 |
|
|
library ieee;
|
| 1602 |
|
|
use ieee.std_logic_1164.all;
|
| 1603 |
|
|
|
| 1604 |
|
|
entity reed_solomon128 is
|
| 1605 |
|
|
port (
|
| 1606 |
|
|
in_rs128 : in std_logic_vector(127 downto 0);
|
| 1607 |
|
|
out_Sfirst_rs128,
|
| 1608 |
|
|
out_Ssecond_rs128 : out std_logic_vector(31 downto 0)
|
| 1609 |
|
|
);
|
| 1610 |
|
|
end reed_solomon128;
|
| 1611 |
|
|
|
| 1612 |
|
|
architecture rs_128_arch of reed_solomon128 is
|
| 1613 |
|
|
|
| 1614 |
|
|
-- declaring all components necessary for reed solomon
|
| 1615 |
|
|
-- 01
|
| 1616 |
|
|
component mul01
|
| 1617 |
|
|
port (
|
| 1618 |
|
|
in_mul01 : in std_logic_vector(7 downto 0);
|
| 1619 |
|
|
out_mul01 : out std_logic_vector(7 downto 0)
|
| 1620 |
|
|
);
|
| 1621 |
|
|
end component;
|
| 1622 |
|
|
|
| 1623 |
|
|
-- a4
|
| 1624 |
|
|
component mula4
|
| 1625 |
|
|
port (
|
| 1626 |
|
|
in_mula4 : in std_logic_vector(7 downto 0);
|
| 1627 |
|
|
out_mula4 : out std_logic_vector(7 downto 0)
|
| 1628 |
|
|
);
|
| 1629 |
|
|
end component;
|
| 1630 |
|
|
|
| 1631 |
|
|
-- 55
|
| 1632 |
|
|
component mul55
|
| 1633 |
|
|
port (
|
| 1634 |
|
|
in_mul55 : in std_logic_vector(7 downto 0);
|
| 1635 |
|
|
out_mul55 : out std_logic_vector(7 downto 0)
|
| 1636 |
|
|
);
|
| 1637 |
|
|
end component;
|
| 1638 |
|
|
|
| 1639 |
|
|
-- 87
|
| 1640 |
|
|
component mul87
|
| 1641 |
|
|
port (
|
| 1642 |
|
|
in_mul87 : in std_logic_vector(7 downto 0);
|
| 1643 |
|
|
out_mul87 : out std_logic_vector(7 downto 0)
|
| 1644 |
|
|
);
|
| 1645 |
|
|
end component;
|
| 1646 |
|
|
|
| 1647 |
|
|
-- 5a
|
| 1648 |
|
|
component mul5a
|
| 1649 |
|
|
port (
|
| 1650 |
|
|
in_mul5a : in std_logic_vector(7 downto 0);
|
| 1651 |
|
|
out_mul5a : out std_logic_vector(7 downto 0)
|
| 1652 |
|
|
);
|
| 1653 |
|
|
end component;
|
| 1654 |
|
|
|
| 1655 |
|
|
-- 58
|
| 1656 |
|
|
component mul58
|
| 1657 |
|
|
port (
|
| 1658 |
|
|
in_mul58 : in std_logic_vector(7 downto 0);
|
| 1659 |
|
|
out_mul58 : out std_logic_vector(7 downto 0)
|
| 1660 |
|
|
);
|
| 1661 |
|
|
end component;
|
| 1662 |
|
|
|
| 1663 |
|
|
|
| 1664 |
|
|
-- db
|
| 1665 |
|
|
component muldb
|
| 1666 |
|
|
port (
|
| 1667 |
|
|
in_muldb : in std_logic_vector(7 downto 0);
|
| 1668 |
|
|
out_muldb : out std_logic_vector(7 downto 0)
|
| 1669 |
|
|
);
|
| 1670 |
|
|
end component;
|
| 1671 |
|
|
|
| 1672 |
|
|
|
| 1673 |
|
|
-- 9e
|
| 1674 |
|
|
component mul9e
|
| 1675 |
|
|
port (
|
| 1676 |
|
|
in_mul9e : in std_logic_vector(7 downto 0);
|
| 1677 |
|
|
out_mul9e : out std_logic_vector(7 downto 0)
|
| 1678 |
|
|
);
|
| 1679 |
|
|
end component;
|
| 1680 |
|
|
|
| 1681 |
|
|
|
| 1682 |
|
|
-- 56
|
| 1683 |
|
|
component mul56
|
| 1684 |
|
|
port (
|
| 1685 |
|
|
in_mul56 : in std_logic_vector(7 downto 0);
|
| 1686 |
|
|
out_mul56 : out std_logic_vector(7 downto 0)
|
| 1687 |
|
|
);
|
| 1688 |
|
|
end component;
|
| 1689 |
|
|
|
| 1690 |
|
|
|
| 1691 |
|
|
-- 82
|
| 1692 |
|
|
component mul82
|
| 1693 |
|
|
port (
|
| 1694 |
|
|
in_mul82 : in std_logic_vector(7 downto 0);
|
| 1695 |
|
|
out_mul82 : out std_logic_vector(7 downto 0)
|
| 1696 |
|
|
);
|
| 1697 |
|
|
end component;
|
| 1698 |
|
|
|
| 1699 |
|
|
|
| 1700 |
|
|
-- f3
|
| 1701 |
|
|
component mulf3
|
| 1702 |
|
|
port (
|
| 1703 |
|
|
in_mulf3 : in std_logic_vector(7 downto 0);
|
| 1704 |
|
|
out_mulf3 : out std_logic_vector(7 downto 0)
|
| 1705 |
|
|
);
|
| 1706 |
|
|
end component;
|
| 1707 |
|
|
|
| 1708 |
|
|
|
| 1709 |
|
|
-- 1e
|
| 1710 |
|
|
component mul1e
|
| 1711 |
|
|
port (
|
| 1712 |
|
|
in_mul1e : in std_logic_vector(7 downto 0);
|
| 1713 |
|
|
out_mul1e : out std_logic_vector(7 downto 0)
|
| 1714 |
|
|
);
|
| 1715 |
|
|
end component;
|
| 1716 |
|
|
|
| 1717 |
|
|
|
| 1718 |
|
|
-- c6
|
| 1719 |
|
|
component mulc6
|
| 1720 |
|
|
port (
|
| 1721 |
|
|
in_mulc6 : in std_logic_vector(7 downto 0);
|
| 1722 |
|
|
out_mulc6 : out std_logic_vector(7 downto 0)
|
| 1723 |
|
|
);
|
| 1724 |
|
|
end component;
|
| 1725 |
|
|
|
| 1726 |
|
|
|
| 1727 |
|
|
-- 68
|
| 1728 |
|
|
component mul68
|
| 1729 |
|
|
port (
|
| 1730 |
|
|
in_mul68 : in std_logic_vector(7 downto 0);
|
| 1731 |
|
|
out_mul68 : out std_logic_vector(7 downto 0)
|
| 1732 |
|
|
);
|
| 1733 |
|
|
end component;
|
| 1734 |
|
|
|
| 1735 |
|
|
|
| 1736 |
|
|
-- e5
|
| 1737 |
|
|
component mule5
|
| 1738 |
|
|
port (
|
| 1739 |
|
|
in_mule5 : in std_logic_vector(7 downto 0);
|
| 1740 |
|
|
out_mule5 : out std_logic_vector(7 downto 0)
|
| 1741 |
|
|
);
|
| 1742 |
|
|
end component;
|
| 1743 |
|
|
|
| 1744 |
|
|
|
| 1745 |
|
|
-- 02
|
| 1746 |
|
|
component mul02
|
| 1747 |
|
|
port (
|
| 1748 |
|
|
in_mul02 : in std_logic_vector(7 downto 0);
|
| 1749 |
|
|
out_mul02 : out std_logic_vector(7 downto 0)
|
| 1750 |
|
|
);
|
| 1751 |
|
|
end component;
|
| 1752 |
|
|
|
| 1753 |
|
|
|
| 1754 |
|
|
-- a1
|
| 1755 |
|
|
component mula1
|
| 1756 |
|
|
port (
|
| 1757 |
|
|
in_mula1 : in std_logic_vector(7 downto 0);
|
| 1758 |
|
|
out_mula1 : out std_logic_vector(7 downto 0)
|
| 1759 |
|
|
);
|
| 1760 |
|
|
end component;
|
| 1761 |
|
|
|
| 1762 |
|
|
|
| 1763 |
|
|
-- fc
|
| 1764 |
|
|
component mulfc
|
| 1765 |
|
|
port (
|
| 1766 |
|
|
in_mulfc : in std_logic_vector(7 downto 0);
|
| 1767 |
|
|
out_mulfc : out std_logic_vector(7 downto 0)
|
| 1768 |
|
|
);
|
| 1769 |
|
|
end component;
|
| 1770 |
|
|
|
| 1771 |
|
|
|
| 1772 |
|
|
-- c1
|
| 1773 |
|
|
component mulc1
|
| 1774 |
|
|
port (
|
| 1775 |
|
|
in_mulc1 : in std_logic_vector(7 downto 0);
|
| 1776 |
|
|
out_mulc1 : out std_logic_vector(7 downto 0)
|
| 1777 |
|
|
);
|
| 1778 |
|
|
end component;
|
| 1779 |
|
|
|
| 1780 |
|
|
|
| 1781 |
|
|
-- 47
|
| 1782 |
|
|
component mul47
|
| 1783 |
|
|
port (
|
| 1784 |
|
|
in_mul47 : in std_logic_vector(7 downto 0);
|
| 1785 |
|
|
out_mul47 : out std_logic_vector(7 downto 0)
|
| 1786 |
|
|
);
|
| 1787 |
|
|
end component;
|
| 1788 |
|
|
|
| 1789 |
|
|
|
| 1790 |
|
|
|
| 1791 |
|
|
-- ae
|
| 1792 |
|
|
component mulae
|
| 1793 |
|
|
port (
|
| 1794 |
|
|
in_mulae : in std_logic_vector(7 downto 0);
|
| 1795 |
|
|
out_mulae : out std_logic_vector(7 downto 0)
|
| 1796 |
|
|
);
|
| 1797 |
|
|
end component;
|
| 1798 |
|
|
|
| 1799 |
|
|
|
| 1800 |
|
|
|
| 1801 |
|
|
-- 3d
|
| 1802 |
|
|
component mul3d
|
| 1803 |
|
|
port (
|
| 1804 |
|
|
in_mul3d : in std_logic_vector(7 downto 0);
|
| 1805 |
|
|
out_mul3d : out std_logic_vector(7 downto 0)
|
| 1806 |
|
|
);
|
| 1807 |
|
|
end component;
|
| 1808 |
|
|
|
| 1809 |
|
|
|
| 1810 |
|
|
|
| 1811 |
|
|
-- 19
|
| 1812 |
|
|
component mul19
|
| 1813 |
|
|
port (
|
| 1814 |
|
|
in_mul19 : in std_logic_vector(7 downto 0);
|
| 1815 |
|
|
out_mul19 : out std_logic_vector(7 downto 0)
|
| 1816 |
|
|
);
|
| 1817 |
|
|
end component;
|
| 1818 |
|
|
|
| 1819 |
|
|
|
| 1820 |
|
|
-- 03
|
| 1821 |
|
|
component mul03
|
| 1822 |
|
|
port (
|
| 1823 |
|
|
in_mul03 : in std_logic_vector(7 downto 0);
|
| 1824 |
|
|
out_mul03 : out std_logic_vector(7 downto 0)
|
| 1825 |
|
|
);
|
| 1826 |
|
|
end component;
|
| 1827 |
|
|
|
| 1828 |
|
|
|
| 1829 |
|
|
-- declaring internal signals
|
| 1830 |
|
|
signal m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15 : std_logic_vector(7 downto 0);
|
| 1831 |
|
|
signal s00,s01,s02,s03,s10,s11,s12,s13 : std_logic_vector(7 downto 0);
|
| 1832 |
|
|
signal m0_01,m1_a4,m2_55,m3_87,m4_5a,m5_58,m6_db,m7_9e,
|
| 1833 |
|
|
m0_a4,m1_56,m2_82,m3_f3,m4_1e,m5_c6,m6_68,m7_e5,
|
| 1834 |
|
|
m0_02,m1_a1,m2_fc,m3_c1,m4_47,m5_ae,m6_3d,m7_19,
|
| 1835 |
|
|
m0_a4_1,m1_55,m2_87,m3_5a,m4_58,m5_db,m6_9e,m7_03 : std_logic_vector(7 downto 0);
|
| 1836 |
|
|
signal m8_01,m9_a4,m10_55,m11_87,m12_5a,m13_58,m14_db,m15_9e,
|
| 1837 |
|
|
m8_a4,m9_56,m10_82,m11_f3,m12_1e,m13_c6,m14_68,m15_e5,
|
| 1838 |
|
|
m8_02,m9_a1,m10_fc,m11_c1,m12_47,m13_ae,m14_3d,m15_19,
|
| 1839 |
|
|
m8_a4_1,m9_55,m10_87,m11_5a,m12_58,m13_db,m14_9e,m15_03 : std_logic_vector(7 downto 0);
|
| 1840 |
|
|
|
| 1841 |
|
|
-- begin architecture description
|
| 1842 |
|
|
begin
|
| 1843 |
|
|
|
| 1844 |
|
|
-- first, we separate the input to the respective m
|
| 1845 |
|
|
-- for s1,j j=0..3
|
| 1846 |
|
|
m0 <= in_rs128(7 downto 0);
|
| 1847 |
|
|
m1 <= in_rs128(15 downto 8);
|
| 1848 |
|
|
m2 <= in_rs128(23 downto 16);
|
| 1849 |
|
|
m3 <= in_rs128(31 downto 24);
|
| 1850 |
|
|
m4 <= in_rs128(39 downto 32);
|
| 1851 |
|
|
m5 <= in_rs128(47 downto 40);
|
| 1852 |
|
|
m6 <= in_rs128(55 downto 48);
|
| 1853 |
|
|
m7 <= in_rs128(63 downto 56);
|
| 1854 |
|
|
|
| 1855 |
|
|
-- for s0,j j=0..3
|
| 1856 |
|
|
m8 <= in_rs128(71 downto 64);
|
| 1857 |
|
|
m9 <= in_rs128(79 downto 72);
|
| 1858 |
|
|
m10 <= in_rs128(87 downto 80);
|
| 1859 |
|
|
m11 <= in_rs128(95 downto 88);
|
| 1860 |
|
|
m12 <= in_rs128(103 downto 96);
|
| 1861 |
|
|
m13 <= in_rs128(111 downto 104);
|
| 1862 |
|
|
m14 <= in_rs128(119 downto 112);
|
| 1863 |
|
|
m15 <= in_rs128(127 downto 120);
|
| 1864 |
|
|
|
| 1865 |
|
|
|
| 1866 |
|
|
-- after separating signals, we drive them to multipliers
|
| 1867 |
|
|
-- the first line of m0..7 forms s00
|
| 1868 |
|
|
m0_with_01: mul01
|
| 1869 |
|
|
port map (
|
| 1870 |
|
|
in_mul01 => m0,
|
| 1871 |
|
|
out_mul01 => m0_01
|
| 1872 |
|
|
);
|
| 1873 |
|
|
|
| 1874 |
|
|
m1_with_a4: mula4
|
| 1875 |
|
|
port map (
|
| 1876 |
|
|
in_mula4 => m1,
|
| 1877 |
|
|
out_mula4 => m1_a4
|
| 1878 |
|
|
);
|
| 1879 |
|
|
|
| 1880 |
|
|
m2_with_55: mul55
|
| 1881 |
|
|
port map (
|
| 1882 |
|
|
in_mul55 => m2,
|
| 1883 |
|
|
out_mul55 => m2_55
|
| 1884 |
|
|
);
|
| 1885 |
|
|
|
| 1886 |
|
|
m3_with_87: mul87
|
| 1887 |
|
|
port map (
|
| 1888 |
|
|
in_mul87 => m3,
|
| 1889 |
|
|
out_mul87 => m3_87
|
| 1890 |
|
|
);
|
| 1891 |
|
|
|
| 1892 |
|
|
m4_with_5a: mul5a
|
| 1893 |
|
|
port map (
|
| 1894 |
|
|
in_mul5a => m4,
|
| 1895 |
|
|
out_mul5a => m4_5a
|
| 1896 |
|
|
);
|
| 1897 |
|
|
|
| 1898 |
|
|
m5_with_58: mul58
|
| 1899 |
|
|
port map (
|
| 1900 |
|
|
in_mul58 => m5,
|
| 1901 |
|
|
out_mul58 => m5_58
|
| 1902 |
|
|
);
|
| 1903 |
|
|
|
| 1904 |
|
|
m6_with_db: muldb
|
| 1905 |
|
|
port map (
|
| 1906 |
|
|
in_muldb => m6,
|
| 1907 |
|
|
out_muldb => m6_db
|
| 1908 |
|
|
);
|
| 1909 |
|
|
|
| 1910 |
|
|
m7_with_9e: mul9e
|
| 1911 |
|
|
port map (
|
| 1912 |
|
|
in_mul9e => m7,
|
| 1913 |
|
|
out_mul9e => m7_9e
|
| 1914 |
|
|
);
|
| 1915 |
|
|
|
| 1916 |
|
|
-- the second row creates s01
|
| 1917 |
|
|
m0_with_a4: mula4
|
| 1918 |
|
|
port map (
|
| 1919 |
|
|
in_mula4 => m0,
|
| 1920 |
|
|
out_mula4 => m0_a4
|
| 1921 |
|
|
);
|
| 1922 |
|
|
|
| 1923 |
|
|
m1_with_56: mul56
|
| 1924 |
|
|
port map (
|
| 1925 |
|
|
in_mul56 => m1,
|
| 1926 |
|
|
out_mul56 => m1_56
|
| 1927 |
|
|
);
|
| 1928 |
|
|
|
| 1929 |
|
|
m2_with_82: mul82
|
| 1930 |
|
|
port map (
|
| 1931 |
|
|
in_mul82 => m2,
|
| 1932 |
|
|
out_mul82 => m2_82
|
| 1933 |
|
|
);
|
| 1934 |
|
|
|
| 1935 |
|
|
m3_with_f3: mulf3
|
| 1936 |
|
|
port map (
|
| 1937 |
|
|
in_mulf3 => m3,
|
| 1938 |
|
|
out_mulf3 => m3_f3
|
| 1939 |
|
|
);
|
| 1940 |
|
|
|
| 1941 |
|
|
m4_with_1e: mul1e
|
| 1942 |
|
|
port map (
|
| 1943 |
|
|
in_mul1e => m4,
|
| 1944 |
|
|
out_mul1e => m4_1e
|
| 1945 |
|
|
);
|
| 1946 |
|
|
|
| 1947 |
|
|
m5_with_c6: mulc6
|
| 1948 |
|
|
port map (
|
| 1949 |
|
|
in_mulc6 => m5,
|
| 1950 |
|
|
out_mulc6 => m5_c6
|
| 1951 |
|
|
);
|
| 1952 |
|
|
|
| 1953 |
|
|
m6_with_68: mul68
|
| 1954 |
|
|
port map (
|
| 1955 |
|
|
in_mul68 => m6,
|
| 1956 |
|
|
out_mul68 => m6_68
|
| 1957 |
|
|
);
|
| 1958 |
|
|
|
| 1959 |
|
|
m7_with_e5: mule5
|
| 1960 |
|
|
port map (
|
| 1961 |
|
|
in_mule5 => m7,
|
| 1962 |
|
|
out_mule5 => m7_e5
|
| 1963 |
|
|
);
|
| 1964 |
|
|
|
| 1965 |
|
|
-- the third row creates s02
|
| 1966 |
|
|
m0_with_02: mul02
|
| 1967 |
|
|
port map (
|
| 1968 |
|
|
in_mul02 => m0,
|
| 1969 |
|
|
out_mul02 => m0_02
|
| 1970 |
|
|
);
|
| 1971 |
|
|
|
| 1972 |
|
|
m1_with_a1: mula1
|
| 1973 |
|
|
port map (
|
| 1974 |
|
|
in_mula1 => m1,
|
| 1975 |
|
|
out_mula1 => m1_a1
|
| 1976 |
|
|
);
|
| 1977 |
|
|
|
| 1978 |
|
|
m2_with_fc: mulfc
|
| 1979 |
|
|
port map (
|
| 1980 |
|
|
in_mulfc => m2,
|
| 1981 |
|
|
out_mulfc => m2_fc
|
| 1982 |
|
|
);
|
| 1983 |
|
|
|
| 1984 |
|
|
m3_with_c1: mulc1
|
| 1985 |
|
|
port map (
|
| 1986 |
|
|
in_mulc1 => m3,
|
| 1987 |
|
|
out_mulc1 => m3_c1
|
| 1988 |
|
|
);
|
| 1989 |
|
|
|
| 1990 |
|
|
m4_with_47: mul47
|
| 1991 |
|
|
port map (
|
| 1992 |
|
|
in_mul47 => m4,
|
| 1993 |
|
|
out_mul47 => m4_47
|
| 1994 |
|
|
);
|
| 1995 |
|
|
|
| 1996 |
|
|
m5_with_ae: mulae
|
| 1997 |
|
|
port map (
|
| 1998 |
|
|
in_mulae => m5,
|
| 1999 |
|
|
out_mulae => m5_ae
|
| 2000 |
|
|
);
|
| 2001 |
|
|
|
| 2002 |
|
|
m6_with_3d: mul3d
|
| 2003 |
|
|
port map (
|
| 2004 |
|
|
in_mul3d => m6,
|
| 2005 |
|
|
out_mul3d => m6_3d
|
| 2006 |
|
|
);
|
| 2007 |
|
|
|
| 2008 |
|
|
m7_with_19: mul19
|
| 2009 |
|
|
port map (
|
| 2010 |
|
|
in_mul19 => m7,
|
| 2011 |
|
|
out_mul19 => m7_19
|
| 2012 |
|
|
);
|
| 2013 |
|
|
|
| 2014 |
|
|
-- the fourth row creates s03
|
| 2015 |
|
|
m0_with_a4_1: mula4
|
| 2016 |
|
|
port map (
|
| 2017 |
|
|
in_mula4 => m0,
|
| 2018 |
|
|
out_mula4 => m0_a4_1
|
| 2019 |
|
|
);
|
| 2020 |
|
|
|
| 2021 |
|
|
m1_with_55: mul55
|
| 2022 |
|
|
port map (
|
| 2023 |
|
|
in_mul55 => m1,
|
| 2024 |
|
|
out_mul55 => m1_55
|
| 2025 |
|
|
);
|
| 2026 |
|
|
|
| 2027 |
|
|
m2_with_87: mul87
|
| 2028 |
|
|
port map (
|
| 2029 |
|
|
in_mul87 => m2,
|
| 2030 |
|
|
out_mul87 => m2_87
|
| 2031 |
|
|
);
|
| 2032 |
|
|
|
| 2033 |
|
|
m3_with_5a: mul5a
|
| 2034 |
|
|
port map (
|
| 2035 |
|
|
in_mul5a => m3,
|
| 2036 |
|
|
out_mul5a => m3_5a
|
| 2037 |
|
|
);
|
| 2038 |
|
|
|
| 2039 |
|
|
m4_with_58: mul58
|
| 2040 |
|
|
port map (
|
| 2041 |
|
|
in_mul58 => m4,
|
| 2042 |
|
|
out_mul58 => m4_58
|
| 2043 |
|
|
);
|
| 2044 |
|
|
|
| 2045 |
|
|
m5_with_db: muldb
|
| 2046 |
|
|
port map (
|
| 2047 |
|
|
in_muldb => m5,
|
| 2048 |
|
|
out_muldb => m5_db
|
| 2049 |
|
|
);
|
| 2050 |
|
|
|
| 2051 |
|
|
m6_with_9e: mul9e
|
| 2052 |
|
|
port map (
|
| 2053 |
|
|
in_mul9e => m6,
|
| 2054 |
|
|
out_mul9e => m6_9e
|
| 2055 |
|
|
);
|
| 2056 |
|
|
|
| 2057 |
|
|
m7_with_03: mul03
|
| 2058 |
|
|
port map (
|
| 2059 |
|
|
in_mul03 => m7,
|
| 2060 |
|
|
out_mul03 => m7_03
|
| 2061 |
|
|
);
|
| 2062 |
|
|
|
| 2063 |
|
|
|
| 2064 |
|
|
-- we create the s1,j j=0..3
|
| 2065 |
|
|
-- the first row of m0..7 creates the s10
|
| 2066 |
|
|
m8_with_01: mul01
|
| 2067 |
|
|
port map (
|
| 2068 |
|
|
in_mul01 => m8,
|
| 2069 |
|
|
out_mul01 => m8_01
|
| 2070 |
|
|
);
|
| 2071 |
|
|
|
| 2072 |
|
|
m9_with_a4: mula4
|
| 2073 |
|
|
port map (
|
| 2074 |
|
|
in_mula4 => m9,
|
| 2075 |
|
|
out_mula4 => m9_a4
|
| 2076 |
|
|
);
|
| 2077 |
|
|
|
| 2078 |
|
|
m10_with_55: mul55
|
| 2079 |
|
|
port map (
|
| 2080 |
|
|
in_mul55 => m10,
|
| 2081 |
|
|
out_mul55 => m10_55
|
| 2082 |
|
|
);
|
| 2083 |
|
|
|
| 2084 |
|
|
m11_with_87: mul87
|
| 2085 |
|
|
port map (
|
| 2086 |
|
|
in_mul87 => m11,
|
| 2087 |
|
|
out_mul87 => m11_87
|
| 2088 |
|
|
);
|
| 2089 |
|
|
|
| 2090 |
|
|
m12_with_5a: mul5a
|
| 2091 |
|
|
port map (
|
| 2092 |
|
|
in_mul5a => m12,
|
| 2093 |
|
|
out_mul5a => m12_5a
|
| 2094 |
|
|
);
|
| 2095 |
|
|
|
| 2096 |
|
|
m13_with_58: mul58
|
| 2097 |
|
|
port map (
|
| 2098 |
|
|
in_mul58 => m13,
|
| 2099 |
|
|
out_mul58 => m13_58
|
| 2100 |
|
|
);
|
| 2101 |
|
|
|
| 2102 |
|
|
m14_with_db: muldb
|
| 2103 |
|
|
port map (
|
| 2104 |
|
|
in_muldb => m14,
|
| 2105 |
|
|
out_muldb => m14_db
|
| 2106 |
|
|
);
|
| 2107 |
|
|
|
| 2108 |
|
|
m15_with_9e: mul9e
|
| 2109 |
|
|
port map (
|
| 2110 |
|
|
in_mul9e => m15,
|
| 2111 |
|
|
out_mul9e => m15_9e
|
| 2112 |
|
|
);
|
| 2113 |
|
|
|
| 2114 |
|
|
-- the second row creates s11
|
| 2115 |
|
|
m8_with_a4: mula4
|
| 2116 |
|
|
port map (
|
| 2117 |
|
|
in_mula4 => m8,
|
| 2118 |
|
|
out_mula4 => m8_a4
|
| 2119 |
|
|
);
|
| 2120 |
|
|
|
| 2121 |
|
|
m9_with_56: mul56
|
| 2122 |
|
|
port map (
|
| 2123 |
|
|
in_mul56 => m9,
|
| 2124 |
|
|
out_mul56 => m9_56
|
| 2125 |
|
|
);
|
| 2126 |
|
|
|
| 2127 |
|
|
m10_with_82: mul82
|
| 2128 |
|
|
port map (
|
| 2129 |
|
|
in_mul82 => m10,
|
| 2130 |
|
|
out_mul82 => m10_82
|
| 2131 |
|
|
);
|
| 2132 |
|
|
|
| 2133 |
|
|
m11_with_f3: mulf3
|
| 2134 |
|
|
port map (
|
| 2135 |
|
|
in_mulf3 => m11,
|
| 2136 |
|
|
out_mulf3 => m11_f3
|
| 2137 |
|
|
);
|
| 2138 |
|
|
|
| 2139 |
|
|
m12_with_1e: mul1e
|
| 2140 |
|
|
port map (
|
| 2141 |
|
|
in_mul1e => m12,
|
| 2142 |
|
|
out_mul1e => m12_1e
|
| 2143 |
|
|
);
|
| 2144 |
|
|
|
| 2145 |
|
|
m13_with_c6: mulc6
|
| 2146 |
|
|
port map (
|
| 2147 |
|
|
in_mulc6 => m13,
|
| 2148 |
|
|
out_mulc6 => m13_c6
|
| 2149 |
|
|
);
|
| 2150 |
|
|
|
| 2151 |
|
|
m14_with_68: mul68
|
| 2152 |
|
|
port map (
|
| 2153 |
|
|
in_mul68 => m14,
|
| 2154 |
|
|
out_mul68 => m14_68
|
| 2155 |
|
|
);
|
| 2156 |
|
|
|
| 2157 |
|
|
m15_with_e5: mule5
|
| 2158 |
|
|
port map (
|
| 2159 |
|
|
in_mule5 => m15,
|
| 2160 |
|
|
out_mule5 => m15_e5
|
| 2161 |
|
|
);
|
| 2162 |
|
|
|
| 2163 |
|
|
-- the third row creates s12
|
| 2164 |
|
|
m8_with_02: mul02
|
| 2165 |
|
|
port map (
|
| 2166 |
|
|
in_mul02 => m8,
|
| 2167 |
|
|
out_mul02 => m8_02
|
| 2168 |
|
|
);
|
| 2169 |
|
|
|
| 2170 |
|
|
m9_with_a1: mula1
|
| 2171 |
|
|
port map (
|
| 2172 |
|
|
in_mula1 => m9,
|
| 2173 |
|
|
out_mula1 => m9_a1
|
| 2174 |
|
|
);
|
| 2175 |
|
|
|
| 2176 |
|
|
m10_with_fc: mulfc
|
| 2177 |
|
|
port map (
|
| 2178 |
|
|
in_mulfc => m10,
|
| 2179 |
|
|
out_mulfc => m10_fc
|
| 2180 |
|
|
);
|
| 2181 |
|
|
|
| 2182 |
|
|
m11_with_c1: mulc1
|
| 2183 |
|
|
port map (
|
| 2184 |
|
|
in_mulc1 => m11,
|
| 2185 |
|
|
out_mulc1 => m11_c1
|
| 2186 |
|
|
);
|
| 2187 |
|
|
|
| 2188 |
|
|
m12_with_47: mul47
|
| 2189 |
|
|
port map (
|
| 2190 |
|
|
in_mul47 => m12,
|
| 2191 |
|
|
out_mul47 => m12_47
|
| 2192 |
|
|
);
|
| 2193 |
|
|
|
| 2194 |
|
|
m13_with_ae: mulae
|
| 2195 |
|
|
port map (
|
| 2196 |
|
|
in_mulae => m13,
|
| 2197 |
|
|
out_mulae => m13_ae
|
| 2198 |
|
|
);
|
| 2199 |
|
|
|
| 2200 |
|
|
m14_with_3d: mul3d
|
| 2201 |
|
|
port map (
|
| 2202 |
|
|
in_mul3d => m14,
|
| 2203 |
|
|
out_mul3d => m14_3d
|
| 2204 |
|
|
);
|
| 2205 |
|
|
|
| 2206 |
|
|
m15_with_19: mul19
|
| 2207 |
|
|
port map (
|
| 2208 |
|
|
in_mul19 => m15,
|
| 2209 |
|
|
out_mul19 => m15_19
|
| 2210 |
|
|
);
|
| 2211 |
|
|
|
| 2212 |
|
|
-- the fourth row creates s13
|
| 2213 |
|
|
m8_with_a4_1: mula4
|
| 2214 |
|
|
port map (
|
| 2215 |
|
|
in_mula4 => m8,
|
| 2216 |
|
|
out_mula4 => m8_a4_1
|
| 2217 |
|
|
);
|
| 2218 |
|
|
|
| 2219 |
|
|
m9_with_55: mul55
|
| 2220 |
|
|
port map (
|
| 2221 |
|
|
in_mul55 => m9,
|
| 2222 |
|
|
out_mul55 => m9_55
|
| 2223 |
|
|
);
|
| 2224 |
|
|
|
| 2225 |
|
|
m10_with_87: mul87
|
| 2226 |
|
|
port map (
|
| 2227 |
|
|
in_mul87 => m10,
|
| 2228 |
|
|
out_mul87 => m10_87
|
| 2229 |
|
|
);
|
| 2230 |
|
|
|
| 2231 |
|
|
m11_with_5a: mul5a
|
| 2232 |
|
|
port map (
|
| 2233 |
|
|
in_mul5a => m11,
|
| 2234 |
|
|
out_mul5a => m11_5a
|
| 2235 |
|
|
);
|
| 2236 |
|
|
|
| 2237 |
|
|
m12_with_58: mul58
|
| 2238 |
|
|
port map (
|
| 2239 |
|
|
in_mul58 => m12,
|
| 2240 |
|
|
out_mul58 => m12_58
|
| 2241 |
|
|
);
|
| 2242 |
|
|
|
| 2243 |
|
|
m13_with_db: muldb
|
| 2244 |
|
|
port map (
|
| 2245 |
|
|
in_muldb => m13,
|
| 2246 |
|
|
out_muldb => m13_db
|
| 2247 |
|
|
);
|
| 2248 |
|
|
|
| 2249 |
|
|
m14_with_9e: mul9e
|
| 2250 |
|
|
port map (
|
| 2251 |
|
|
in_mul9e => m14,
|
| 2252 |
|
|
out_mul9e => m14_9e
|
| 2253 |
|
|
);
|
| 2254 |
|
|
|
| 2255 |
|
|
m15_with_03: mul03
|
| 2256 |
|
|
port map (
|
| 2257 |
|
|
in_mul03 => m15,
|
| 2258 |
|
|
out_mul03 => m15_03
|
| 2259 |
|
|
);
|
| 2260 |
|
|
|
| 2261 |
|
|
|
| 2262 |
|
|
-- after getting the results from multipliers
|
| 2263 |
|
|
-- we combine them in order to get the additions
|
| 2264 |
|
|
s00 <= m0_01 XOR m1_a4 XOR m2_55 XOR m3_87 XOR m4_5a XOR m5_58 XOR m6_db XOR m7_9e;
|
| 2265 |
|
|
s01 <= m0_a4 XOR m1_56 XOR m2_82 XOR m3_f3 XOR m4_1e XOR m5_c6 XOR m6_68 XOR m7_e5;
|
| 2266 |
|
|
s02 <= m0_02 XOR m1_a1 XOR m2_fc XOR m3_c1 XOR m4_47 XOR m5_ae XOR m6_3d XOR m7_19;
|
| 2267 |
|
|
s03 <= m0_a4_1 XOR m1_55 XOR m2_87 XOR m3_5a XOR m4_58 XOR m5_db XOR m6_9e XOR m7_03;
|
| 2268 |
|
|
|
| 2269 |
|
|
-- after creating s0,j j=0...3 we form the S0
|
| 2270 |
|
|
-- little endian
|
| 2271 |
|
|
out_Sfirst_rs128 <= s03 & s02 & s01 & s00;
|
| 2272 |
|
|
|
| 2273 |
|
|
s10 <= m8_01 XOR m9_a4 XOR m10_55 XOR m11_87 XOR m12_5a XOR m13_58 XOR m14_db XOR m15_9e;
|
| 2274 |
|
|
s11 <= m8_a4 XOR m9_56 XOR m10_82 XOR m11_f3 XOR m12_1e XOR m13_c6 XOR m14_68 XOR m15_e5;
|
| 2275 |
|
|
s12 <= m8_02 XOR m9_a1 XOR m10_fc XOR m11_c1 XOR m12_47 XOR m13_ae XOR m14_3d XOR m15_19;
|
| 2276 |
|
|
s13 <= m8_a4_1 XOR m9_55 XOR m10_87 XOR m11_5a XOR m12_58 XOR m13_db XOR m14_9e XOR m15_03;
|
| 2277 |
|
|
|
| 2278 |
|
|
-- after creating s1,j j=0...3 we form the S1
|
| 2279 |
|
|
-- little endian
|
| 2280 |
|
|
out_Ssecond_rs128 <= s13 & s12 & s11 & s10;
|
| 2281 |
|
|
|
| 2282 |
|
|
end rs_128_arch;
|
| 2283 |
|
|
|
| 2284 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2285 |
|
|
-- --
|
| 2286 |
|
|
-- new component --
|
| 2287 |
|
|
-- --
|
| 2288 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2289 |
|
|
|
| 2290 |
|
|
--
|
| 2291 |
|
|
-- h function for 128 bits key
|
| 2292 |
|
|
--
|
| 2293 |
|
|
|
| 2294 |
|
|
library ieee;
|
| 2295 |
|
|
use ieee.std_logic_1164.all;
|
| 2296 |
|
|
|
| 2297 |
|
|
entity h_128 is
|
| 2298 |
|
|
port (
|
| 2299 |
|
|
in_h128 : in std_logic_vector(7 downto 0);
|
| 2300 |
|
|
Mfirst_h128,
|
| 2301 |
|
|
Msecond_h128 : in std_logic_vector(31 downto 0);
|
| 2302 |
|
|
out_h128 : out std_logic_vector(31 downto 0)
|
| 2303 |
|
|
);
|
| 2304 |
|
|
end h_128;
|
| 2305 |
|
|
|
| 2306 |
|
|
architecture h128_arch of h_128 is
|
| 2307 |
|
|
|
| 2308 |
|
|
-- we declare internal signals
|
| 2309 |
|
|
signal from_first_row,
|
| 2310 |
|
|
to_second_row,
|
| 2311 |
|
|
from_second_row,
|
| 2312 |
|
|
to_third_row,
|
| 2313 |
|
|
to_mds : std_logic_vector(31 downto 0);
|
| 2314 |
|
|
|
| 2315 |
|
|
-- we declare all components needed
|
| 2316 |
|
|
component q0
|
| 2317 |
|
|
port (
|
| 2318 |
|
|
in_q0 : in std_logic_vector(7 downto 0);
|
| 2319 |
|
|
out_q0 : out std_logic_vector(7 downto 0)
|
| 2320 |
|
|
);
|
| 2321 |
|
|
end component;
|
| 2322 |
|
|
|
| 2323 |
|
|
component q1
|
| 2324 |
|
|
port (
|
| 2325 |
|
|
in_q1 : in std_logic_vector(7 downto 0);
|
| 2326 |
|
|
out_q1 : out std_logic_vector(7 downto 0)
|
| 2327 |
|
|
);
|
| 2328 |
|
|
end component;
|
| 2329 |
|
|
|
| 2330 |
|
|
component mds
|
| 2331 |
|
|
port (
|
| 2332 |
|
|
y0,
|
| 2333 |
|
|
y1,
|
| 2334 |
|
|
y2,
|
| 2335 |
|
|
y3 : in std_logic_vector(7 downto 0);
|
| 2336 |
|
|
z0,
|
| 2337 |
|
|
z1,
|
| 2338 |
|
|
z2,
|
| 2339 |
|
|
z3 : out std_logic_vector(7 downto 0)
|
| 2340 |
|
|
);
|
| 2341 |
|
|
end component;
|
| 2342 |
|
|
|
| 2343 |
|
|
-- begin architecture description
|
| 2344 |
|
|
begin
|
| 2345 |
|
|
|
| 2346 |
|
|
-- first row of q
|
| 2347 |
|
|
first_q0_1: q0
|
| 2348 |
|
|
port map (
|
| 2349 |
|
|
in_q0 => in_h128,
|
| 2350 |
|
|
out_q0 => from_first_row(7 downto 0)
|
| 2351 |
|
|
);
|
| 2352 |
|
|
first_q1_1: q1
|
| 2353 |
|
|
port map (
|
| 2354 |
|
|
in_q1 => in_h128,
|
| 2355 |
|
|
out_q1 => from_first_row(15 downto 8)
|
| 2356 |
|
|
);
|
| 2357 |
|
|
first_q0_2: q0
|
| 2358 |
|
|
port map (
|
| 2359 |
|
|
in_q0 => in_h128,
|
| 2360 |
|
|
out_q0 => from_first_row(23 downto 16)
|
| 2361 |
|
|
);
|
| 2362 |
|
|
first_q1_2: q1
|
| 2363 |
|
|
port map (
|
| 2364 |
|
|
in_q1 => in_h128,
|
| 2365 |
|
|
out_q1 => from_first_row(31 downto 24)
|
| 2366 |
|
|
);
|
| 2367 |
|
|
|
| 2368 |
|
|
-- we perform the XOR of the results of the first row
|
| 2369 |
|
|
-- with first M of h (Mfist_h128)
|
| 2370 |
|
|
to_second_row <= from_first_row XOR Mfirst_h128;
|
| 2371 |
|
|
|
| 2372 |
|
|
-- second row of q
|
| 2373 |
|
|
second_q0_1: q0
|
| 2374 |
|
|
port map (
|
| 2375 |
|
|
in_q0 => to_second_row(7 downto 0),
|
| 2376 |
|
|
out_q0 => from_second_row(7 downto 0)
|
| 2377 |
|
|
);
|
| 2378 |
|
|
second_q0_2: q0
|
| 2379 |
|
|
port map (
|
| 2380 |
|
|
in_q0 => to_second_row(15 downto 8),
|
| 2381 |
|
|
out_q0 => from_second_row(15 downto 8)
|
| 2382 |
|
|
);
|
| 2383 |
|
|
second_q1_1: q1
|
| 2384 |
|
|
port map (
|
| 2385 |
|
|
in_q1 => to_second_row(23 downto 16),
|
| 2386 |
|
|
out_q1 => from_second_row(23 downto 16)
|
| 2387 |
|
|
);
|
| 2388 |
|
|
second_q1_2: q1
|
| 2389 |
|
|
port map (
|
| 2390 |
|
|
in_q1 => to_second_row(31 downto 24),
|
| 2391 |
|
|
out_q1 => from_second_row(31 downto 24)
|
| 2392 |
|
|
);
|
| 2393 |
|
|
|
| 2394 |
|
|
-- we perform the second XOR
|
| 2395 |
|
|
to_third_row <= from_second_row XOR Msecond_h128;
|
| 2396 |
|
|
|
| 2397 |
|
|
-- the third row of q
|
| 2398 |
|
|
third_q1_1: q1
|
| 2399 |
|
|
port map (
|
| 2400 |
|
|
in_q1 => to_third_row(7 downto 0),
|
| 2401 |
|
|
out_q1 => to_mds(7 downto 0)
|
| 2402 |
|
|
);
|
| 2403 |
|
|
third_q0_1: q0
|
| 2404 |
|
|
port map (
|
| 2405 |
|
|
in_q0 => to_third_row(15 downto 8),
|
| 2406 |
|
|
out_q0 => to_mds(15 downto 8)
|
| 2407 |
|
|
);
|
| 2408 |
|
|
third_q1_2: q1
|
| 2409 |
|
|
port map (
|
| 2410 |
|
|
in_q1 => to_third_row(23 downto 16),
|
| 2411 |
|
|
out_q1 => to_mds(23 downto 16)
|
| 2412 |
|
|
);
|
| 2413 |
|
|
third_q0_2: q0
|
| 2414 |
|
|
port map (
|
| 2415 |
|
|
in_q0 => to_third_row(31 downto 24),
|
| 2416 |
|
|
out_q0 => to_mds(31 downto 24)
|
| 2417 |
|
|
);
|
| 2418 |
|
|
|
| 2419 |
|
|
-- mds table
|
| 2420 |
|
|
mds_table: mds
|
| 2421 |
|
|
port map (
|
| 2422 |
|
|
y0 => to_mds(7 downto 0),
|
| 2423 |
|
|
y1 => to_mds(15 downto 8),
|
| 2424 |
|
|
y2 => to_mds(23 downto 16),
|
| 2425 |
|
|
y3 => to_mds(31 downto 24),
|
| 2426 |
|
|
z0 => out_h128(7 downto 0),
|
| 2427 |
|
|
z1 => out_h128(15 downto 8),
|
| 2428 |
|
|
z2 => out_h128(23 downto 16),
|
| 2429 |
|
|
z3 => out_h128(31 downto 24)
|
| 2430 |
|
|
);
|
| 2431 |
|
|
|
| 2432 |
|
|
end h128_arch;
|
| 2433 |
|
|
|
| 2434 |
|
|
|
| 2435 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2436 |
|
|
-- --
|
| 2437 |
|
|
-- new component --
|
| 2438 |
|
|
-- --
|
| 2439 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2440 |
|
|
|
| 2441 |
|
|
|
| 2442 |
|
|
--
|
| 2443 |
|
|
-- g function for 128 bits key
|
| 2444 |
|
|
--
|
| 2445 |
|
|
|
| 2446 |
|
|
library ieee;
|
| 2447 |
|
|
use ieee.std_logic_1164.all;
|
| 2448 |
|
|
|
| 2449 |
|
|
entity g_128 is
|
| 2450 |
|
|
port (
|
| 2451 |
|
|
in_g128,
|
| 2452 |
|
|
in_S0_g128,
|
| 2453 |
|
|
in_S1_g128 : in std_logic_vector(31 downto 0);
|
| 2454 |
|
|
out_g128 : out std_logic_vector(31 downto 0)
|
| 2455 |
|
|
);
|
| 2456 |
|
|
end g_128;
|
| 2457 |
|
|
|
| 2458 |
|
|
architecture g128_arch of g_128 is
|
| 2459 |
|
|
|
| 2460 |
|
|
-- we declare the internal signals
|
| 2461 |
|
|
signal from_first_row,
|
| 2462 |
|
|
to_second_row,
|
| 2463 |
|
|
from_second_row,
|
| 2464 |
|
|
to_third_row,
|
| 2465 |
|
|
to_mds : std_logic_vector(31 downto 0);
|
| 2466 |
|
|
|
| 2467 |
|
|
component q0
|
| 2468 |
|
|
port (
|
| 2469 |
|
|
in_q0 : in std_logic_vector(7 downto 0);
|
| 2470 |
|
|
out_q0 : out std_logic_vector(7 downto 0)
|
| 2471 |
|
|
);
|
| 2472 |
|
|
end component;
|
| 2473 |
|
|
|
| 2474 |
|
|
component q1
|
| 2475 |
|
|
port (
|
| 2476 |
|
|
in_q1 : in std_logic_vector(7 downto 0);
|
| 2477 |
|
|
out_q1 : out std_logic_vector(7 downto 0)
|
| 2478 |
|
|
);
|
| 2479 |
|
|
end component;
|
| 2480 |
|
|
|
| 2481 |
|
|
component mds
|
| 2482 |
|
|
port (
|
| 2483 |
|
|
y0,
|
| 2484 |
|
|
y1,
|
| 2485 |
|
|
y2,
|
| 2486 |
|
|
y3 : in std_logic_vector(7 downto 0);
|
| 2487 |
|
|
z0,
|
| 2488 |
|
|
z1,
|
| 2489 |
|
|
z2,
|
| 2490 |
|
|
z3 : out std_logic_vector(7 downto 0)
|
| 2491 |
|
|
);
|
| 2492 |
|
|
end component;
|
| 2493 |
|
|
|
| 2494 |
|
|
-- begin architecture description
|
| 2495 |
|
|
begin
|
| 2496 |
|
|
|
| 2497 |
|
|
-- first row of q
|
| 2498 |
|
|
first_q0_1: q0
|
| 2499 |
|
|
port map (
|
| 2500 |
|
|
in_q0 => in_g128(7 downto 0),
|
| 2501 |
|
|
out_q0 => from_first_row(7 downto 0)
|
| 2502 |
|
|
);
|
| 2503 |
|
|
first_q1_1: q1
|
| 2504 |
|
|
port map (
|
| 2505 |
|
|
in_q1 => in_g128(15 downto 8),
|
| 2506 |
|
|
out_q1 => from_first_row(15 downto 8)
|
| 2507 |
|
|
);
|
| 2508 |
|
|
first_q0_2: q0
|
| 2509 |
|
|
port map (
|
| 2510 |
|
|
in_q0 => in_g128(23 downto 16),
|
| 2511 |
|
|
out_q0 => from_first_row(23 downto 16)
|
| 2512 |
|
|
);
|
| 2513 |
|
|
first_q1_2: q1
|
| 2514 |
|
|
port map (
|
| 2515 |
|
|
in_q1 => in_g128(31 downto 24),
|
| 2516 |
|
|
out_q1 => from_first_row(31 downto 24)
|
| 2517 |
|
|
);
|
| 2518 |
|
|
|
| 2519 |
|
|
-- we XOR the result of the first row
|
| 2520 |
|
|
-- with the S0
|
| 2521 |
|
|
to_second_row <= from_first_row XOR in_S0_g128;
|
| 2522 |
|
|
|
| 2523 |
|
|
-- second row of q
|
| 2524 |
|
|
second_q0_1: q0
|
| 2525 |
|
|
port map (
|
| 2526 |
|
|
in_q0 => to_second_row(7 downto 0),
|
| 2527 |
|
|
out_q0 => from_second_row(7 downto 0)
|
| 2528 |
|
|
);
|
| 2529 |
|
|
second_q0_2: q0
|
| 2530 |
|
|
port map (
|
| 2531 |
|
|
in_q0 => to_second_row(15 downto 8),
|
| 2532 |
|
|
out_q0 => from_second_row(15 downto 8)
|
| 2533 |
|
|
);
|
| 2534 |
|
|
second_q1_1: q1
|
| 2535 |
|
|
port map (
|
| 2536 |
|
|
in_q1 => to_second_row(23 downto 16),
|
| 2537 |
|
|
out_q1 => from_second_row(23 downto 16)
|
| 2538 |
|
|
);
|
| 2539 |
|
|
second_q1_2: q1
|
| 2540 |
|
|
port map (
|
| 2541 |
|
|
in_q1 => to_second_row(31 downto 24),
|
| 2542 |
|
|
out_q1 => from_second_row(31 downto 24)
|
| 2543 |
|
|
);
|
| 2544 |
|
|
|
| 2545 |
|
|
-- we perform the XOR
|
| 2546 |
|
|
to_third_row <= from_second_row XOR in_S1_g128;
|
| 2547 |
|
|
|
| 2548 |
|
|
-- third row of q
|
| 2549 |
|
|
third_q1_1: q1
|
| 2550 |
|
|
port map (
|
| 2551 |
|
|
in_q1 => to_third_row(7 downto 0),
|
| 2552 |
|
|
out_q1 => to_mds(7 downto 0)
|
| 2553 |
|
|
);
|
| 2554 |
|
|
third_q0_1: q0
|
| 2555 |
|
|
port map (
|
| 2556 |
|
|
in_q0 => to_third_row(15 downto 8),
|
| 2557 |
|
|
out_q0 => to_mds(15 downto 8)
|
| 2558 |
|
|
);
|
| 2559 |
|
|
third_q1_2: q1
|
| 2560 |
|
|
port map (
|
| 2561 |
|
|
in_q1 => to_third_row(23 downto 16),
|
| 2562 |
|
|
out_q1 => to_mds(23 downto 16)
|
| 2563 |
|
|
);
|
| 2564 |
|
|
third_q0_2: q0
|
| 2565 |
|
|
port map (
|
| 2566 |
|
|
in_q0 => to_third_row(31 downto 24),
|
| 2567 |
|
|
out_q0 => to_mds(31 downto 24)
|
| 2568 |
|
|
);
|
| 2569 |
|
|
|
| 2570 |
|
|
-- mds table
|
| 2571 |
|
|
mds_table: mds
|
| 2572 |
|
|
port map (
|
| 2573 |
|
|
y0 => to_mds(7 downto 0),
|
| 2574 |
|
|
y1 => to_mds(15 downto 8),
|
| 2575 |
|
|
y2 => to_mds(23 downto 16),
|
| 2576 |
|
|
y3 => to_mds(31 downto 24),
|
| 2577 |
|
|
z0 => out_g128(7 downto 0),
|
| 2578 |
|
|
z1 => out_g128(15 downto 8),
|
| 2579 |
|
|
z2 => out_g128(23 downto 16),
|
| 2580 |
|
|
z3 => out_g128(31 downto 24)
|
| 2581 |
|
|
);
|
| 2582 |
|
|
|
| 2583 |
|
|
end g128_arch;
|
| 2584 |
|
|
|
| 2585 |
|
|
|
| 2586 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2587 |
|
|
-- --
|
| 2588 |
|
|
-- new component --
|
| 2589 |
|
|
-- --
|
| 2590 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2591 |
|
|
|
| 2592 |
|
|
|
| 2593 |
|
|
--
|
| 2594 |
|
|
-- f function with 128 bits key
|
| 2595 |
|
|
--
|
| 2596 |
|
|
|
| 2597 |
|
|
library ieee;
|
| 2598 |
|
|
use ieee.std_logic_1164.all;
|
| 2599 |
|
|
|
| 2600 |
|
|
entity f_128 is
|
| 2601 |
|
|
port (
|
| 2602 |
|
|
up_in_f128,
|
| 2603 |
|
|
low_in_f128,
|
| 2604 |
|
|
S0_in_f128,
|
| 2605 |
|
|
S1_in_f128,
|
| 2606 |
|
|
up_key_f128,
|
| 2607 |
|
|
low_key_f128 : in std_logic_vector(31 downto 0);
|
| 2608 |
|
|
up_out_f128,
|
| 2609 |
|
|
low_out_f128 : out std_logic_vector(31 downto 0)
|
| 2610 |
|
|
);
|
| 2611 |
|
|
end f_128;
|
| 2612 |
|
|
|
| 2613 |
|
|
architecture f128_arch of f_128 is
|
| 2614 |
|
|
|
| 2615 |
|
|
-- we declare the internal signals
|
| 2616 |
|
|
signal from_shift_8,
|
| 2617 |
|
|
to_up_pht,
|
| 2618 |
|
|
to_low_pht,
|
| 2619 |
|
|
to_up_key,
|
| 2620 |
|
|
to_low_key,
|
| 2621 |
|
|
intermediate_carry1,
|
| 2622 |
|
|
intermediate_carry2 : std_logic_vector(31 downto 0);
|
| 2623 |
|
|
signal zero : std_logic;
|
| 2624 |
|
|
|
| 2625 |
|
|
|
| 2626 |
|
|
component g_128
|
| 2627 |
|
|
port (
|
| 2628 |
|
|
in_g128,
|
| 2629 |
|
|
in_S0_g128,
|
| 2630 |
|
|
in_S1_g128 : in std_logic_vector(31 downto 0);
|
| 2631 |
|
|
out_g128 : out std_logic_vector(31 downto 0)
|
| 2632 |
|
|
);
|
| 2633 |
|
|
end component;
|
| 2634 |
|
|
|
| 2635 |
|
|
component pht
|
| 2636 |
|
|
port (
|
| 2637 |
|
|
up_in_pht,
|
| 2638 |
|
|
down_in_pht : in std_logic_vector(31 downto 0);
|
| 2639 |
|
|
up_out_pht,
|
| 2640 |
|
|
down_out_pht : out std_logic_vector(31 downto 0)
|
| 2641 |
|
|
);
|
| 2642 |
|
|
end component;
|
| 2643 |
|
|
|
| 2644 |
|
|
component adder
|
| 2645 |
|
|
port (
|
| 2646 |
|
|
in1_adder,
|
| 2647 |
|
|
in2_adder,
|
| 2648 |
|
|
in_carry_adder : in std_logic;
|
| 2649 |
|
|
out_adder,
|
| 2650 |
|
|
out_carry_adder : out std_logic
|
| 2651 |
|
|
);
|
| 2652 |
|
|
end component;
|
| 2653 |
|
|
|
| 2654 |
|
|
-- begin architecture description
|
| 2655 |
|
|
begin
|
| 2656 |
|
|
|
| 2657 |
|
|
-- we initialize zero
|
| 2658 |
|
|
zero <= '0';
|
| 2659 |
|
|
|
| 2660 |
|
|
-- upper g_128
|
| 2661 |
|
|
upper_g128: g_128
|
| 2662 |
|
|
port map (
|
| 2663 |
|
|
in_g128 => up_in_f128,
|
| 2664 |
|
|
in_S0_g128 => S0_in_f128,
|
| 2665 |
|
|
in_S1_g128 => S1_in_f128,
|
| 2666 |
|
|
out_g128 => to_up_pht
|
| 2667 |
|
|
);
|
| 2668 |
|
|
|
| 2669 |
|
|
-- left rotation by 8
|
| 2670 |
|
|
from_shift_8(31 downto 8) <= low_in_f128(23 downto 0);
|
| 2671 |
|
|
from_shift_8(7 downto 0) <= low_in_f128(31 downto 24);
|
| 2672 |
|
|
|
| 2673 |
|
|
-- lower g128
|
| 2674 |
|
|
lower_g128: g_128
|
| 2675 |
|
|
port map (
|
| 2676 |
|
|
in_g128 => from_shift_8,
|
| 2677 |
|
|
in_S0_g128 => S0_in_f128,
|
| 2678 |
|
|
in_S1_g128 => S1_in_f128,
|
| 2679 |
|
|
out_g128 => to_low_pht
|
| 2680 |
|
|
);
|
| 2681 |
|
|
|
| 2682 |
|
|
-- pht
|
| 2683 |
|
|
pht_transform: pht
|
| 2684 |
|
|
port map (
|
| 2685 |
|
|
up_in_pht => to_up_pht,
|
| 2686 |
|
|
down_in_pht => to_low_pht,
|
| 2687 |
|
|
up_out_pht => to_up_key,
|
| 2688 |
|
|
down_out_pht => to_low_key
|
| 2689 |
|
|
);
|
| 2690 |
|
|
|
| 2691 |
|
|
-- upper adder of 32 bits
|
| 2692 |
|
|
up_adder: for i in 0 to 31 generate
|
| 2693 |
|
|
first: if (i=0) generate
|
| 2694 |
|
|
the_adder: adder
|
| 2695 |
|
|
port map (
|
| 2696 |
|
|
in1_adder => to_up_key(0),
|
| 2697 |
|
|
in2_adder => up_key_f128(0),
|
| 2698 |
|
|
in_carry_adder => zero,
|
| 2699 |
|
|
out_adder => up_out_f128(0),
|
| 2700 |
|
|
out_carry_adder => intermediate_carry1(0)
|
| 2701 |
|
|
);
|
| 2702 |
|
|
end generate first;
|
| 2703 |
|
|
the_rest: if (i>0) generate
|
| 2704 |
|
|
the_adders: adder
|
| 2705 |
|
|
port map (
|
| 2706 |
|
|
in1_adder => to_up_key(i),
|
| 2707 |
|
|
in2_adder => up_key_f128(i),
|
| 2708 |
|
|
in_carry_adder => intermediate_carry1(i-1),
|
| 2709 |
|
|
out_adder => up_out_f128(i),
|
| 2710 |
|
|
out_carry_adder => intermediate_carry1(i)
|
| 2711 |
|
|
);
|
| 2712 |
|
|
end generate the_rest;
|
| 2713 |
|
|
end generate up_adder;
|
| 2714 |
|
|
|
| 2715 |
|
|
-- lower adder of 32 bits
|
| 2716 |
|
|
low_adder: for i in 0 to 31 generate
|
| 2717 |
|
|
first1: if (i=0) generate
|
| 2718 |
|
|
the_adder1:adder
|
| 2719 |
|
|
port map (
|
| 2720 |
|
|
in1_adder => to_low_key(0),
|
| 2721 |
|
|
in2_adder => low_key_f128(0),
|
| 2722 |
|
|
in_carry_adder => zero,
|
| 2723 |
|
|
out_adder => low_out_f128(0),
|
| 2724 |
|
|
out_carry_adder => intermediate_carry2(0)
|
| 2725 |
|
|
);
|
| 2726 |
|
|
end generate first1;
|
| 2727 |
|
|
the_rest1: if (i>0) generate
|
| 2728 |
|
|
the_adders1: adder
|
| 2729 |
|
|
port map (
|
| 2730 |
|
|
in1_adder => to_low_key(i),
|
| 2731 |
|
|
in2_adder => low_key_f128(i),
|
| 2732 |
|
|
in_carry_adder => intermediate_carry2(i-1),
|
| 2733 |
|
|
out_adder => low_out_f128(i),
|
| 2734 |
|
|
out_carry_adder => intermediate_carry2(i)
|
| 2735 |
|
|
);
|
| 2736 |
|
|
end generate the_rest1;
|
| 2737 |
|
|
end generate low_adder;
|
| 2738 |
|
|
|
| 2739 |
|
|
end f128_arch;
|
| 2740 |
|
|
|
| 2741 |
|
|
|
| 2742 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2743 |
|
|
-- --
|
| 2744 |
|
|
-- new component --
|
| 2745 |
|
|
-- --
|
| 2746 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2747 |
|
|
|
| 2748 |
|
|
--
|
| 2749 |
|
|
-- twofish key scheduler for 128 bits key input
|
| 2750 |
|
|
--
|
| 2751 |
|
|
|
| 2752 |
|
|
library ieee;
|
| 2753 |
|
|
use ieee.std_logic_1164.all;
|
| 2754 |
|
|
|
| 2755 |
|
|
entity twofish_keysched128 is
|
| 2756 |
|
|
port (
|
| 2757 |
|
|
odd_in_tk128,
|
| 2758 |
|
|
even_in_tk128 : in std_logic_vector(7 downto 0);
|
| 2759 |
|
|
in_key_tk128 : in std_logic_vector(127 downto 0);
|
| 2760 |
|
|
out_key_up_tk128,
|
| 2761 |
|
|
out_key_down_tk128 : out std_logic_vector(31 downto 0)
|
| 2762 |
|
|
);
|
| 2763 |
|
|
end twofish_keysched128;
|
| 2764 |
|
|
|
| 2765 |
|
|
architecture twofish_keysched128_arch of twofish_keysched128 is
|
| 2766 |
|
|
|
| 2767 |
|
|
-- we declare internal signals
|
| 2768 |
|
|
signal to_up_pht,
|
| 2769 |
|
|
to_shift_8,
|
| 2770 |
|
|
from_shift_8,
|
| 2771 |
|
|
to_shift_9,
|
| 2772 |
|
|
M0, M1, M2, M3 : std_logic_vector(31 downto 0);
|
| 2773 |
|
|
|
| 2774 |
|
|
signal byte0, byte1, byte2, byte3,
|
| 2775 |
|
|
byte4, byte5, byte6, byte7,
|
| 2776 |
|
|
byte8, byte9, byte10, byte11,
|
| 2777 |
|
|
byte12, byte13, byte14, byte15 : std_logic_vector(7 downto 0);
|
| 2778 |
|
|
|
| 2779 |
|
|
-- we declare the components to be used
|
| 2780 |
|
|
component pht
|
| 2781 |
|
|
port (
|
| 2782 |
|
|
up_in_pht,
|
| 2783 |
|
|
down_in_pht : in std_logic_vector(31 downto 0);
|
| 2784 |
|
|
up_out_pht,
|
| 2785 |
|
|
down_out_pht : out std_logic_vector(31 downto 0)
|
| 2786 |
|
|
);
|
| 2787 |
|
|
end component;
|
| 2788 |
|
|
|
| 2789 |
|
|
component h_128
|
| 2790 |
|
|
port (
|
| 2791 |
|
|
in_h128 : in std_logic_vector(7 downto 0);
|
| 2792 |
|
|
Mfirst_h128,
|
| 2793 |
|
|
Msecond_h128 : in std_logic_vector(31 downto 0);
|
| 2794 |
|
|
out_h128 : out std_logic_vector(31 downto 0)
|
| 2795 |
|
|
);
|
| 2796 |
|
|
end component;
|
| 2797 |
|
|
|
| 2798 |
|
|
-- begin architecture description
|
| 2799 |
|
|
begin
|
| 2800 |
|
|
|
| 2801 |
|
|
-- we assign the input signal to the respective
|
| 2802 |
|
|
-- bytes as is described in the prototype
|
| 2803 |
|
|
byte15 <= in_key_tk128(7 downto 0);
|
| 2804 |
|
|
byte14 <= in_key_tk128(15 downto 8);
|
| 2805 |
|
|
byte13 <= in_key_tk128(23 downto 16);
|
| 2806 |
|
|
byte12 <= in_key_tk128(31 downto 24);
|
| 2807 |
|
|
byte11 <= in_key_tk128(39 downto 32);
|
| 2808 |
|
|
byte10 <= in_key_tk128(47 downto 40);
|
| 2809 |
|
|
byte9 <= in_key_tk128(55 downto 48);
|
| 2810 |
|
|
byte8 <= in_key_tk128(63 downto 56);
|
| 2811 |
|
|
byte7 <= in_key_tk128(71 downto 64);
|
| 2812 |
|
|
byte6 <= in_key_tk128(79 downto 72);
|
| 2813 |
|
|
byte5 <= in_key_tk128(87 downto 80);
|
| 2814 |
|
|
byte4 <= in_key_tk128(95 downto 88);
|
| 2815 |
|
|
byte3 <= in_key_tk128(103 downto 96);
|
| 2816 |
|
|
byte2 <= in_key_tk128(111 downto 104);
|
| 2817 |
|
|
byte1 <= in_key_tk128(119 downto 112);
|
| 2818 |
|
|
byte0 <= in_key_tk128(127 downto 120);
|
| 2819 |
|
|
|
| 2820 |
|
|
-- we form the M{0..3}
|
| 2821 |
|
|
M0 <= byte3 & byte2 & byte1 & byte0;
|
| 2822 |
|
|
M1 <= byte7 & byte6 & byte5 & byte4;
|
| 2823 |
|
|
M2 <= byte11 & byte10 & byte9 & byte8;
|
| 2824 |
|
|
M3 <= byte15 & byte14 & byte13 & byte12;
|
| 2825 |
|
|
|
| 2826 |
|
|
-- upper h
|
| 2827 |
|
|
upper_h: h_128
|
| 2828 |
|
|
port map (
|
| 2829 |
|
|
in_h128 => even_in_tk128,
|
| 2830 |
|
|
Mfirst_h128 => M2,
|
| 2831 |
|
|
Msecond_h128 => M0,
|
| 2832 |
|
|
out_h128 => to_up_pht
|
| 2833 |
|
|
);
|
| 2834 |
|
|
|
| 2835 |
|
|
-- lower h
|
| 2836 |
|
|
lower_h: h_128
|
| 2837 |
|
|
port map (
|
| 2838 |
|
|
in_h128 => odd_in_tk128,
|
| 2839 |
|
|
Mfirst_h128 => M3,
|
| 2840 |
|
|
Msecond_h128 => M1,
|
| 2841 |
|
|
out_h128 => to_shift_8
|
| 2842 |
|
|
);
|
| 2843 |
|
|
|
| 2844 |
|
|
-- left rotate by 8
|
| 2845 |
|
|
from_shift_8(31 downto 8) <= to_shift_8(23 downto 0);
|
| 2846 |
|
|
from_shift_8(7 downto 0) <= to_shift_8(31 downto 24);
|
| 2847 |
|
|
|
| 2848 |
|
|
-- pht transformation
|
| 2849 |
|
|
pht_transform: pht
|
| 2850 |
|
|
port map (
|
| 2851 |
|
|
up_in_pht => to_up_pht,
|
| 2852 |
|
|
down_in_pht => from_shift_8,
|
| 2853 |
|
|
up_out_pht => out_key_up_tk128,
|
| 2854 |
|
|
down_out_pht => to_shift_9
|
| 2855 |
|
|
);
|
| 2856 |
|
|
|
| 2857 |
|
|
-- left rotate by 9
|
| 2858 |
|
|
out_key_down_tk128(31 downto 9) <= to_shift_9(22 downto 0);
|
| 2859 |
|
|
out_key_down_tk128(8 downto 0) <= to_shift_9(31 downto 23);
|
| 2860 |
|
|
|
| 2861 |
|
|
end twofish_keysched128_arch;
|
| 2862 |
|
|
|
| 2863 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2864 |
|
|
-- --
|
| 2865 |
|
|
-- new component --
|
| 2866 |
|
|
-- --
|
| 2867 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2868 |
|
|
|
| 2869 |
|
|
--
|
| 2870 |
|
|
-- twofish S key component for 128 bits key
|
| 2871 |
|
|
--
|
| 2872 |
|
|
|
| 2873 |
|
|
library ieee;
|
| 2874 |
|
|
use ieee.std_logic_1164.all;
|
| 2875 |
|
|
|
| 2876 |
|
|
entity twofish_S128 is
|
| 2877 |
|
|
port (
|
| 2878 |
|
|
in_key_ts128 : in std_logic_vector(127 downto 0);
|
| 2879 |
|
|
out_Sfirst_ts128,
|
| 2880 |
|
|
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
|
| 2881 |
|
|
);
|
| 2882 |
|
|
end twofish_S128;
|
| 2883 |
|
|
|
| 2884 |
|
|
architecture twofish_S128_arch of twofish_S128 is
|
| 2885 |
|
|
|
| 2886 |
|
|
-- we declare the components to be used
|
| 2887 |
|
|
component reed_solomon128
|
| 2888 |
|
|
port (
|
| 2889 |
|
|
in_rs128 : in std_logic_vector(127 downto 0);
|
| 2890 |
|
|
out_Sfirst_rs128,
|
| 2891 |
|
|
out_Ssecond_rs128 : out std_logic_vector(31 downto 0)
|
| 2892 |
|
|
);
|
| 2893 |
|
|
end component;
|
| 2894 |
|
|
|
| 2895 |
|
|
signal twofish_key : std_logic_vector(127 downto 0);
|
| 2896 |
|
|
signal byte15, byte14, byte13, byte12, byte11, byte10,
|
| 2897 |
|
|
byte9, byte8, byte7, byte6, byte5, byte4,
|
| 2898 |
|
|
byte3, byte2, byte1, byte0 : std_logic_vector(7 downto 0);
|
| 2899 |
|
|
|
| 2900 |
|
|
-- begin architecture description
|
| 2901 |
|
|
begin
|
| 2902 |
|
|
|
| 2903 |
|
|
-- splitting the input
|
| 2904 |
|
|
byte15 <= in_key_ts128(7 downto 0);
|
| 2905 |
|
|
byte14 <= in_key_ts128(15 downto 8);
|
| 2906 |
|
|
byte13 <= in_key_ts128(23 downto 16);
|
| 2907 |
|
|
byte12 <= in_key_ts128(31 downto 24);
|
| 2908 |
|
|
byte11 <= in_key_ts128(39 downto 32);
|
| 2909 |
|
|
byte10 <= in_key_ts128(47 downto 40);
|
| 2910 |
|
|
byte9 <= in_key_ts128(55 downto 48);
|
| 2911 |
|
|
byte8 <= in_key_ts128(63 downto 56);
|
| 2912 |
|
|
byte7 <= in_key_ts128(71 downto 64);
|
| 2913 |
|
|
byte6 <= in_key_ts128(79 downto 72);
|
| 2914 |
|
|
byte5 <= in_key_ts128(87 downto 80);
|
| 2915 |
|
|
byte4 <= in_key_ts128(95 downto 88);
|
| 2916 |
|
|
byte3 <= in_key_ts128(103 downto 96);
|
| 2917 |
|
|
byte2 <= in_key_ts128(111 downto 104);
|
| 2918 |
|
|
byte1 <= in_key_ts128(119 downto 112);
|
| 2919 |
|
|
byte0 <= in_key_ts128(127 downto 120);
|
| 2920 |
|
|
|
| 2921 |
|
|
-- forming the key
|
| 2922 |
|
|
twofish_key <= byte15 & byte14 & byte13 & byte12 & byte11 & byte10 & byte9 & byte8 & byte7 &
|
| 2923 |
|
|
byte6 & byte5 & byte4 & byte3 & byte2 & byte1 & byte0;
|
| 2924 |
|
|
|
| 2925 |
|
|
|
| 2926 |
|
|
-- the keys S0,1
|
| 2927 |
|
|
produce_S0_S1: reed_solomon128
|
| 2928 |
|
|
port map (
|
| 2929 |
|
|
in_rs128 => twofish_key,
|
| 2930 |
|
|
out_Sfirst_rs128 => out_Sfirst_ts128,
|
| 2931 |
|
|
out_Ssecond_rs128 => out_Ssecond_ts128
|
| 2932 |
|
|
);
|
| 2933 |
|
|
|
| 2934 |
|
|
|
| 2935 |
|
|
end twofish_S128_arch;
|
| 2936 |
|
|
|
| 2937 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2938 |
|
|
-- --
|
| 2939 |
|
|
-- new component --
|
| 2940 |
|
|
-- --
|
| 2941 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 2942 |
|
|
|
| 2943 |
|
|
--
|
| 2944 |
|
|
-- twofish whitening key scheduler for 128 bits key input
|
| 2945 |
|
|
--
|
| 2946 |
|
|
|
| 2947 |
|
|
library ieee;
|
| 2948 |
|
|
use ieee.std_logic_1164.all;
|
| 2949 |
|
|
|
| 2950 |
|
|
entity twofish_whit_keysched128 is
|
| 2951 |
|
|
port (
|
| 2952 |
|
|
in_key_twk128 : in std_logic_vector(127 downto 0);
|
| 2953 |
|
|
out_K0_twk128,
|
| 2954 |
|
|
out_K1_twk128,
|
| 2955 |
|
|
out_K2_twk128,
|
| 2956 |
|
|
out_K3_twk128,
|
| 2957 |
|
|
out_K4_twk128,
|
| 2958 |
|
|
out_K5_twk128,
|
| 2959 |
|
|
out_K6_twk128,
|
| 2960 |
|
|
out_K7_twk128 : out std_logic_vector(31 downto 0)
|
| 2961 |
|
|
);
|
| 2962 |
|
|
end twofish_whit_keysched128;
|
| 2963 |
|
|
|
| 2964 |
|
|
architecture twofish_whit_keysched128_arch of twofish_whit_keysched128 is
|
| 2965 |
|
|
|
| 2966 |
|
|
-- we declare internal signals
|
| 2967 |
|
|
signal to_up_pht_1,
|
| 2968 |
|
|
to_shift_8_1,
|
| 2969 |
|
|
from_shift_8_1,
|
| 2970 |
|
|
to_shift_9_1,
|
| 2971 |
|
|
to_up_pht_2,
|
| 2972 |
|
|
to_shift_8_2,
|
| 2973 |
|
|
from_shift_8_2,
|
| 2974 |
|
|
to_shift_9_2,
|
| 2975 |
|
|
to_up_pht_3,
|
| 2976 |
|
|
to_shift_8_3,
|
| 2977 |
|
|
from_shift_8_3,
|
| 2978 |
|
|
to_shift_9_3,
|
| 2979 |
|
|
to_up_pht_4,
|
| 2980 |
|
|
to_shift_8_4,
|
| 2981 |
|
|
from_shift_8_4,
|
| 2982 |
|
|
to_shift_9_4,
|
| 2983 |
|
|
M0, M1, M2, M3 : std_logic_vector(31 downto 0);
|
| 2984 |
|
|
|
| 2985 |
|
|
signal byte0, byte1, byte2, byte3,
|
| 2986 |
|
|
byte4, byte5, byte6, byte7,
|
| 2987 |
|
|
byte8, byte9, byte10, byte11,
|
| 2988 |
|
|
byte12, byte13, byte14, byte15 : std_logic_vector(7 downto 0);
|
| 2989 |
|
|
|
| 2990 |
|
|
signal zero, one, two, three, four, five, six, seven : std_logic_vector(7 downto 0);
|
| 2991 |
|
|
|
| 2992 |
|
|
-- we declare the components to be used
|
| 2993 |
|
|
component pht
|
| 2994 |
|
|
port (
|
| 2995 |
|
|
up_in_pht,
|
| 2996 |
|
|
down_in_pht : in std_logic_vector(31 downto 0);
|
| 2997 |
|
|
up_out_pht,
|
| 2998 |
|
|
down_out_pht : out std_logic_vector(31 downto 0)
|
| 2999 |
|
|
);
|
| 3000 |
|
|
end component;
|
| 3001 |
|
|
|
| 3002 |
|
|
component h_128
|
| 3003 |
|
|
port (
|
| 3004 |
|
|
in_h128 : in std_logic_vector(7 downto 0);
|
| 3005 |
|
|
Mfirst_h128,
|
| 3006 |
|
|
Msecond_h128 : in std_logic_vector(31 downto 0);
|
| 3007 |
|
|
out_h128 : out std_logic_vector(31 downto 0)
|
| 3008 |
|
|
);
|
| 3009 |
|
|
end component;
|
| 3010 |
|
|
|
| 3011 |
|
|
-- begin architecture description
|
| 3012 |
|
|
begin
|
| 3013 |
|
|
|
| 3014 |
|
|
-- we produce the first eight numbers
|
| 3015 |
|
|
zero <= "00000000";
|
| 3016 |
|
|
one <= "00000001";
|
| 3017 |
|
|
two <= "00000010";
|
| 3018 |
|
|
three <= "00000011";
|
| 3019 |
|
|
four <= "00000100";
|
| 3020 |
|
|
five <= "00000101";
|
| 3021 |
|
|
six <= "00000110";
|
| 3022 |
|
|
seven <= "00000111";
|
| 3023 |
|
|
|
| 3024 |
|
|
-- we assign the input signal to the respective
|
| 3025 |
|
|
-- bytes as is described in the prototype
|
| 3026 |
|
|
byte15 <= in_key_twk128(7 downto 0);
|
| 3027 |
|
|
byte14 <= in_key_twk128(15 downto 8);
|
| 3028 |
|
|
byte13 <= in_key_twk128(23 downto 16);
|
| 3029 |
|
|
byte12 <= in_key_twk128(31 downto 24);
|
| 3030 |
|
|
byte11 <= in_key_twk128(39 downto 32);
|
| 3031 |
|
|
byte10 <= in_key_twk128(47 downto 40);
|
| 3032 |
|
|
byte9 <= in_key_twk128(55 downto 48);
|
| 3033 |
|
|
byte8 <= in_key_twk128(63 downto 56);
|
| 3034 |
|
|
byte7 <= in_key_twk128(71 downto 64);
|
| 3035 |
|
|
byte6 <= in_key_twk128(79 downto 72);
|
| 3036 |
|
|
byte5 <= in_key_twk128(87 downto 80);
|
| 3037 |
|
|
byte4 <= in_key_twk128(95 downto 88);
|
| 3038 |
|
|
byte3 <= in_key_twk128(103 downto 96);
|
| 3039 |
|
|
byte2 <= in_key_twk128(111 downto 104);
|
| 3040 |
|
|
byte1 <= in_key_twk128(119 downto 112);
|
| 3041 |
|
|
byte0 <= in_key_twk128(127 downto 120);
|
| 3042 |
|
|
|
| 3043 |
|
|
-- we form the M{0..3}
|
| 3044 |
|
|
M0 <= byte3 & byte2 & byte1 & byte0;
|
| 3045 |
|
|
M1 <= byte7 & byte6 & byte5 & byte4;
|
| 3046 |
|
|
M2 <= byte11 & byte10 & byte9 & byte8;
|
| 3047 |
|
|
M3 <= byte15 & byte14 & byte13 & byte12;
|
| 3048 |
|
|
|
| 3049 |
|
|
-- we produce the keys for the whitening steps
|
| 3050 |
|
|
-- keys K0,1
|
| 3051 |
|
|
-- upper h
|
| 3052 |
|
|
upper_h1: h_128
|
| 3053 |
|
|
port map (
|
| 3054 |
|
|
in_h128 => zero,
|
| 3055 |
|
|
Mfirst_h128 => M2,
|
| 3056 |
|
|
Msecond_h128 => M0,
|
| 3057 |
|
|
out_h128 => to_up_pht_1
|
| 3058 |
|
|
);
|
| 3059 |
|
|
|
| 3060 |
|
|
-- lower h
|
| 3061 |
|
|
lower_h1: h_128
|
| 3062 |
|
|
port map (
|
| 3063 |
|
|
in_h128 => one,
|
| 3064 |
|
|
Mfirst_h128 => M3,
|
| 3065 |
|
|
Msecond_h128 => M1,
|
| 3066 |
|
|
out_h128 => to_shift_8_1
|
| 3067 |
|
|
);
|
| 3068 |
|
|
|
| 3069 |
|
|
-- left rotate by 8
|
| 3070 |
|
|
from_shift_8_1(31 downto 8) <= to_shift_8_1(23 downto 0);
|
| 3071 |
|
|
from_shift_8_1(7 downto 0) <= to_shift_8_1(31 downto 24);
|
| 3072 |
|
|
|
| 3073 |
|
|
-- pht transformation
|
| 3074 |
|
|
pht_transform1: pht
|
| 3075 |
|
|
port map (
|
| 3076 |
|
|
up_in_pht => to_up_pht_1,
|
| 3077 |
|
|
down_in_pht => from_shift_8_1,
|
| 3078 |
|
|
up_out_pht => out_K0_twk128,
|
| 3079 |
|
|
down_out_pht => to_shift_9_1
|
| 3080 |
|
|
);
|
| 3081 |
|
|
|
| 3082 |
|
|
-- left rotate by 9
|
| 3083 |
|
|
out_K1_twk128(31 downto 9) <= to_shift_9_1(22 downto 0);
|
| 3084 |
|
|
out_K1_twk128(8 downto 0) <= to_shift_9_1(31 downto 23);
|
| 3085 |
|
|
|
| 3086 |
|
|
-- keys K2,3
|
| 3087 |
|
|
-- upper h
|
| 3088 |
|
|
upper_h2: h_128
|
| 3089 |
|
|
port map (
|
| 3090 |
|
|
in_h128 => two,
|
| 3091 |
|
|
Mfirst_h128 => M2,
|
| 3092 |
|
|
Msecond_h128 => M0,
|
| 3093 |
|
|
out_h128 => to_up_pht_2
|
| 3094 |
|
|
);
|
| 3095 |
|
|
|
| 3096 |
|
|
-- lower h
|
| 3097 |
|
|
lower_h2: h_128
|
| 3098 |
|
|
port map (
|
| 3099 |
|
|
in_h128 => three,
|
| 3100 |
|
|
Mfirst_h128 => M3,
|
| 3101 |
|
|
Msecond_h128 => M1,
|
| 3102 |
|
|
out_h128 => to_shift_8_2
|
| 3103 |
|
|
);
|
| 3104 |
|
|
|
| 3105 |
|
|
-- left rotate by 8
|
| 3106 |
|
|
from_shift_8_2(31 downto 8) <= to_shift_8_2(23 downto 0);
|
| 3107 |
|
|
from_shift_8_2(7 downto 0) <= to_shift_8_2(31 downto 24);
|
| 3108 |
|
|
|
| 3109 |
|
|
-- pht transformation
|
| 3110 |
|
|
pht_transform2: pht
|
| 3111 |
|
|
port map (
|
| 3112 |
|
|
up_in_pht => to_up_pht_2,
|
| 3113 |
|
|
down_in_pht => from_shift_8_2,
|
| 3114 |
|
|
up_out_pht => out_K2_twk128,
|
| 3115 |
|
|
down_out_pht => to_shift_9_2
|
| 3116 |
|
|
);
|
| 3117 |
|
|
|
| 3118 |
|
|
-- left rotate by 9
|
| 3119 |
|
|
out_K3_twk128(31 downto 9) <= to_shift_9_2(22 downto 0);
|
| 3120 |
|
|
out_K3_twk128(8 downto 0) <= to_shift_9_2(31 downto 23);
|
| 3121 |
|
|
|
| 3122 |
|
|
-- keys K4,5
|
| 3123 |
|
|
-- upper h
|
| 3124 |
|
|
upper_h3: h_128
|
| 3125 |
|
|
port map (
|
| 3126 |
|
|
in_h128 => four,
|
| 3127 |
|
|
Mfirst_h128 => M2,
|
| 3128 |
|
|
Msecond_h128 => M0,
|
| 3129 |
|
|
out_h128 => to_up_pht_3
|
| 3130 |
|
|
);
|
| 3131 |
|
|
|
| 3132 |
|
|
-- lower h
|
| 3133 |
|
|
lower_h3: h_128
|
| 3134 |
|
|
port map (
|
| 3135 |
|
|
in_h128 => five,
|
| 3136 |
|
|
Mfirst_h128 => M3,
|
| 3137 |
|
|
Msecond_h128 => M1,
|
| 3138 |
|
|
out_h128 => to_shift_8_3
|
| 3139 |
|
|
);
|
| 3140 |
|
|
|
| 3141 |
|
|
-- left rotate by 8
|
| 3142 |
|
|
from_shift_8_3(31 downto 8) <= to_shift_8_3(23 downto 0);
|
| 3143 |
|
|
from_shift_8_3(7 downto 0) <= to_shift_8_3(31 downto 24);
|
| 3144 |
|
|
|
| 3145 |
|
|
-- pht transformation
|
| 3146 |
|
|
pht_transform3: pht
|
| 3147 |
|
|
port map (
|
| 3148 |
|
|
up_in_pht => to_up_pht_3,
|
| 3149 |
|
|
down_in_pht => from_shift_8_3,
|
| 3150 |
|
|
up_out_pht => out_K4_twk128,
|
| 3151 |
|
|
down_out_pht => to_shift_9_3
|
| 3152 |
|
|
);
|
| 3153 |
|
|
|
| 3154 |
|
|
-- left rotate by 9
|
| 3155 |
|
|
out_K5_twk128(31 downto 9) <= to_shift_9_3(22 downto 0);
|
| 3156 |
|
|
out_K5_twk128(8 downto 0) <= to_shift_9_3(31 downto 23);
|
| 3157 |
|
|
|
| 3158 |
|
|
-- keys K6,7
|
| 3159 |
|
|
-- upper h
|
| 3160 |
|
|
upper_h4: h_128
|
| 3161 |
|
|
port map (
|
| 3162 |
|
|
in_h128 => six,
|
| 3163 |
|
|
Mfirst_h128 => M2,
|
| 3164 |
|
|
Msecond_h128 => M0,
|
| 3165 |
|
|
out_h128 => to_up_pht_4
|
| 3166 |
|
|
);
|
| 3167 |
|
|
|
| 3168 |
|
|
-- lower h
|
| 3169 |
|
|
lower_h4: h_128
|
| 3170 |
|
|
port map (
|
| 3171 |
|
|
in_h128 => seven,
|
| 3172 |
|
|
Mfirst_h128 => M3,
|
| 3173 |
|
|
Msecond_h128 => M1,
|
| 3174 |
|
|
out_h128 => to_shift_8_4
|
| 3175 |
|
|
);
|
| 3176 |
|
|
|
| 3177 |
|
|
-- left rotate by 8
|
| 3178 |
|
|
from_shift_8_4(31 downto 8) <= to_shift_8_4(23 downto 0);
|
| 3179 |
|
|
from_shift_8_4(7 downto 0) <= to_shift_8_4(31 downto 24);
|
| 3180 |
|
|
|
| 3181 |
|
|
-- pht transformation
|
| 3182 |
|
|
pht_transform4: pht
|
| 3183 |
|
|
port map (
|
| 3184 |
|
|
up_in_pht => to_up_pht_4,
|
| 3185 |
|
|
down_in_pht => from_shift_8_4,
|
| 3186 |
|
|
up_out_pht => out_K6_twk128,
|
| 3187 |
|
|
down_out_pht => to_shift_9_4
|
| 3188 |
|
|
);
|
| 3189 |
|
|
|
| 3190 |
|
|
-- left rotate by 9
|
| 3191 |
|
|
out_K7_twk128(31 downto 9) <= to_shift_9_4(22 downto 0);
|
| 3192 |
|
|
out_K7_twk128(8 downto 0) <= to_shift_9_4(31 downto 23);
|
| 3193 |
|
|
|
| 3194 |
|
|
end twofish_whit_keysched128_arch;
|
| 3195 |
|
|
|
| 3196 |
|
|
|
| 3197 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 3198 |
|
|
-- --
|
| 3199 |
|
|
-- new component --
|
| 3200 |
|
|
-- --
|
| 3201 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 3202 |
|
|
|
| 3203 |
|
|
--
|
| 3204 |
|
|
-- twofish encryption round with 128 bit key input
|
| 3205 |
|
|
--
|
| 3206 |
|
|
|
| 3207 |
|
|
library ieee;
|
| 3208 |
|
|
use ieee.std_logic_1164.all;
|
| 3209 |
|
|
|
| 3210 |
|
|
entity twofish_encryption_round128 is
|
| 3211 |
|
|
port (
|
| 3212 |
|
|
in1_ter128,
|
| 3213 |
|
|
in2_ter128,
|
| 3214 |
|
|
in3_ter128,
|
| 3215 |
|
|
in4_ter128,
|
| 3216 |
|
|
in_Sfirst_ter128,
|
| 3217 |
|
|
in_Ssecond_ter128,
|
| 3218 |
|
|
in_key_up_ter128,
|
| 3219 |
|
|
in_key_down_ter128 : in std_logic_vector(31 downto 0);
|
| 3220 |
|
|
out1_ter128,
|
| 3221 |
|
|
out2_ter128,
|
| 3222 |
|
|
out3_ter128,
|
| 3223 |
|
|
out4_ter128 : out std_logic_vector(31 downto 0)
|
| 3224 |
|
|
);
|
| 3225 |
|
|
end twofish_encryption_round128;
|
| 3226 |
|
|
|
| 3227 |
|
|
architecture twofish_encryption_round128_arch of twofish_encryption_round128 is
|
| 3228 |
|
|
|
| 3229 |
|
|
-- we declare internal signals
|
| 3230 |
|
|
signal to_left_shift,
|
| 3231 |
|
|
from_right_shift,
|
| 3232 |
|
|
to_xor_with3,
|
| 3233 |
|
|
to_xor_with4 : std_logic_vector(31 downto 0);
|
| 3234 |
|
|
|
| 3235 |
|
|
component f_128
|
| 3236 |
|
|
port (
|
| 3237 |
|
|
up_in_f128,
|
| 3238 |
|
|
low_in_f128,
|
| 3239 |
|
|
S0_in_f128,
|
| 3240 |
|
|
S1_in_f128,
|
| 3241 |
|
|
up_key_f128,
|
| 3242 |
|
|
low_key_f128 : in std_logic_vector(31 downto 0);
|
| 3243 |
|
|
up_out_f128,
|
| 3244 |
|
|
low_out_f128 : out std_logic_vector(31 downto 0)
|
| 3245 |
|
|
);
|
| 3246 |
|
|
end component;
|
| 3247 |
|
|
|
| 3248 |
|
|
-- begin architecture description
|
| 3249 |
|
|
begin
|
| 3250 |
|
|
|
| 3251 |
|
|
-- we declare f_128
|
| 3252 |
|
|
function_f: f_128
|
| 3253 |
|
|
port map (
|
| 3254 |
|
|
up_in_f128 => in1_ter128,
|
| 3255 |
|
|
low_in_f128 => in2_ter128,
|
| 3256 |
|
|
S0_in_f128 => in_Sfirst_ter128,
|
| 3257 |
|
|
S1_in_f128 => in_Ssecond_ter128,
|
| 3258 |
|
|
up_key_f128 => in_key_up_ter128,
|
| 3259 |
|
|
low_key_f128 => in_key_down_ter128,
|
| 3260 |
|
|
up_out_f128 => to_xor_with3,
|
| 3261 |
|
|
low_out_f128 => to_xor_with4
|
| 3262 |
|
|
);
|
| 3263 |
|
|
|
| 3264 |
|
|
-- we perform the exchange
|
| 3265 |
|
|
-- in1_ter128 -> out3_ter128
|
| 3266 |
|
|
-- in2_ter128 -> out4_ter128
|
| 3267 |
|
|
-- in3_ter128 -> out1_ter128
|
| 3268 |
|
|
-- in4_ter128 -> out2_ter128
|
| 3269 |
|
|
|
| 3270 |
|
|
-- we perform the left xor between the upper f function and
|
| 3271 |
|
|
-- the third input (input 3)
|
| 3272 |
|
|
to_left_shift <= to_xor_with3 XOR in3_ter128;
|
| 3273 |
|
|
|
| 3274 |
|
|
-- we perform the left side rotation to the right by 1 and
|
| 3275 |
|
|
-- we perform the exchange too
|
| 3276 |
|
|
out1_ter128(30 downto 0) <= to_left_shift(31 downto 1);
|
| 3277 |
|
|
out1_ter128(31) <= to_left_shift(0);
|
| 3278 |
|
|
|
| 3279 |
|
|
-- we perform the right side rotation to the left by 1
|
| 3280 |
|
|
from_right_shift(0) <= in4_ter128(31);
|
| 3281 |
|
|
from_right_shift(31 downto 1) <= in4_ter128(30 downto 0);
|
| 3282 |
|
|
|
| 3283 |
|
|
-- we perform the right xor between the lower f function and
|
| 3284 |
|
|
-- the fourth input (input 4)
|
| 3285 |
|
|
out2_ter128 <= from_right_shift XOR to_xor_with4;
|
| 3286 |
|
|
|
| 3287 |
|
|
-- we perform the last exchanges
|
| 3288 |
|
|
out3_ter128 <= in1_ter128;
|
| 3289 |
|
|
out4_ter128 <= in2_ter128;
|
| 3290 |
|
|
|
| 3291 |
|
|
end twofish_encryption_round128_arch;
|
| 3292 |
|
|
|
| 3293 |
|
|
|
| 3294 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 3295 |
|
|
-- --
|
| 3296 |
|
|
-- new component --
|
| 3297 |
|
|
-- --
|
| 3298 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 3299 |
|
|
|
| 3300 |
|
|
--
|
| 3301 |
|
|
-- twofish decryption round with 128 bit key input
|
| 3302 |
|
|
--
|
| 3303 |
|
|
|
| 3304 |
|
|
library ieee;
|
| 3305 |
|
|
use ieee.std_logic_1164.all;
|
| 3306 |
|
|
|
| 3307 |
|
|
entity twofish_decryption_round128 is
|
| 3308 |
|
|
port (
|
| 3309 |
|
|
in1_tdr128,
|
| 3310 |
|
|
in2_tdr128,
|
| 3311 |
|
|
in3_tdr128,
|
| 3312 |
|
|
in4_tdr128,
|
| 3313 |
|
|
in_Sfirst_tdr128,
|
| 3314 |
|
|
in_Ssecond_tdr128,
|
| 3315 |
|
|
in_key_up_tdr128,
|
| 3316 |
|
|
in_key_down_tdr128 : in std_logic_vector(31 downto 0);
|
| 3317 |
|
|
out1_tdr128,
|
| 3318 |
|
|
out2_tdr128,
|
| 3319 |
|
|
out3_tdr128,
|
| 3320 |
|
|
out4_tdr128 : out std_logic_vector(31 downto 0)
|
| 3321 |
|
|
);
|
| 3322 |
|
|
end twofish_decryption_round128;
|
| 3323 |
|
|
|
| 3324 |
|
|
architecture twofish_decryption_round128_arch of twofish_decryption_round128 is
|
| 3325 |
|
|
|
| 3326 |
|
|
signal to_xor_with3,
|
| 3327 |
|
|
to_xor_with4,
|
| 3328 |
|
|
to_xor_with_up_f,
|
| 3329 |
|
|
from_xor_with_down_f : std_logic_vector(31 downto 0);
|
| 3330 |
|
|
|
| 3331 |
|
|
component f_128
|
| 3332 |
|
|
port (
|
| 3333 |
|
|
up_in_f128,
|
| 3334 |
|
|
low_in_f128,
|
| 3335 |
|
|
S0_in_f128,
|
| 3336 |
|
|
S1_in_f128,
|
| 3337 |
|
|
up_key_f128,
|
| 3338 |
|
|
low_key_f128 : in std_logic_vector(31 downto 0);
|
| 3339 |
|
|
up_out_f128,
|
| 3340 |
|
|
low_out_f128 : out std_logic_vector(31 downto 0)
|
| 3341 |
|
|
);
|
| 3342 |
|
|
end component;
|
| 3343 |
|
|
|
| 3344 |
|
|
begin
|
| 3345 |
|
|
|
| 3346 |
|
|
-- we instantiate f function
|
| 3347 |
|
|
function_f: f_128
|
| 3348 |
|
|
port map (
|
| 3349 |
|
|
up_in_f128 => in1_tdr128,
|
| 3350 |
|
|
low_in_f128 => in2_tdr128,
|
| 3351 |
|
|
S0_in_f128 => in_Sfirst_tdr128,
|
| 3352 |
|
|
S1_in_f128 => in_Ssecond_tdr128,
|
| 3353 |
|
|
up_key_f128 => in_key_up_tdr128,
|
| 3354 |
|
|
low_key_f128 => in_key_down_tdr128,
|
| 3355 |
|
|
up_out_f128 => to_xor_with3,
|
| 3356 |
|
|
low_out_f128 => to_xor_with4
|
| 3357 |
|
|
);
|
| 3358 |
|
|
|
| 3359 |
|
|
-- output 1: input3 with upper f
|
| 3360 |
|
|
-- we first rotate the input3 by 1 bit leftwise
|
| 3361 |
|
|
to_xor_with_up_f(0) <= in3_tdr128(31);
|
| 3362 |
|
|
to_xor_with_up_f(31 downto 1) <= in3_tdr128(30 downto 0);
|
| 3363 |
|
|
|
| 3364 |
|
|
-- we perform the XOR with the upper output of f and the result
|
| 3365 |
|
|
-- is ouput 1
|
| 3366 |
|
|
out1_tdr128 <= to_xor_with_up_f XOR to_xor_with3;
|
| 3367 |
|
|
|
| 3368 |
|
|
-- output 2: input4 with lower f
|
| 3369 |
|
|
-- we perform the XOR with the lower output of f
|
| 3370 |
|
|
from_xor_with_down_f <= in4_tdr128 XOR to_xor_with4;
|
| 3371 |
|
|
|
| 3372 |
|
|
-- we perform the rotation by 1 bit rightwise and the result
|
| 3373 |
|
|
-- is output2
|
| 3374 |
|
|
out2_tdr128(31) <= from_xor_with_down_f(0);
|
| 3375 |
|
|
out2_tdr128(30 downto 0) <= from_xor_with_down_f(31 downto 1);
|
| 3376 |
|
|
|
| 3377 |
|
|
-- we assign outputs 3 and 4
|
| 3378 |
|
|
out3_tdr128 <= in1_tdr128;
|
| 3379 |
|
|
out4_tdr128 <= in2_tdr128;
|
| 3380 |
|
|
|
| 3381 |
|
|
end twofish_decryption_round128_arch;
|
| 3382 |
|
|
|
| 3383 |
|
|
-- ============================================== --
|
| 3384 |
|
|
-- ============================================== --
|
| 3385 |
|
|
-- --
|
| 3386 |
|
|
-- third part: 192 key input dependent components --
|
| 3387 |
|
|
-- --
|
| 3388 |
|
|
-- ============================================== --
|
| 3389 |
|
|
-- ============================================== --
|
| 3390 |
|
|
|
| 3391 |
|
|
--
|
| 3392 |
|
|
-- reed solomon for 192bits key
|
| 3393 |
|
|
--
|
| 3394 |
|
|
|
| 3395 |
|
|
library ieee;
|
| 3396 |
|
|
use ieee.std_logic_1164.all;
|
| 3397 |
|
|
|
| 3398 |
|
|
entity reed_solomon192 is
|
| 3399 |
|
|
port (
|
| 3400 |
|
|
in_rs192 : in std_logic_vector(191 downto 0);
|
| 3401 |
|
|
out_Sfirst_rs192,
|
| 3402 |
|
|
out_Ssecond_rs192,
|
| 3403 |
|
|
out_Sthird_rs192 : out std_logic_vector(31 downto 0)
|
| 3404 |
|
|
);
|
| 3405 |
|
|
end reed_solomon192;
|
| 3406 |
|
|
|
| 3407 |
|
|
architecture rs_192_arch of reed_solomon192 is
|
| 3408 |
|
|
|
| 3409 |
|
|
-- declaring all components necessary for reed solomon
|
| 3410 |
|
|
-- 01
|
| 3411 |
|
|
component mul01
|
| 3412 |
|
|
port (
|
| 3413 |
|
|
in_mul01 : in std_logic_vector(7 downto 0);
|
| 3414 |
|
|
out_mul01 : out std_logic_vector(7 downto 0)
|
| 3415 |
|
|
);
|
| 3416 |
|
|
end component;
|
| 3417 |
|
|
|
| 3418 |
|
|
-- a4
|
| 3419 |
|
|
component mula4
|
| 3420 |
|
|
port (
|
| 3421 |
|
|
in_mula4 : in std_logic_vector(7 downto 0);
|
| 3422 |
|
|
out_mula4 : out std_logic_vector(7 downto 0)
|
| 3423 |
|
|
);
|
| 3424 |
|
|
end component;
|
| 3425 |
|
|
|
| 3426 |
|
|
-- 55
|
| 3427 |
|
|
component mul55
|
| 3428 |
|
|
port (
|
| 3429 |
|
|
in_mul55 : in std_logic_vector(7 downto 0);
|
| 3430 |
|
|
out_mul55 : out std_logic_vector(7 downto 0)
|
| 3431 |
|
|
);
|
| 3432 |
|
|
end component;
|
| 3433 |
|
|
|
| 3434 |
|
|
-- 87
|
| 3435 |
|
|
component mul87
|
| 3436 |
|
|
port (
|
| 3437 |
|
|
in_mul87 : in std_logic_vector(7 downto 0);
|
| 3438 |
|
|
out_mul87 : out std_logic_vector(7 downto 0)
|
| 3439 |
|
|
);
|
| 3440 |
|
|
end component;
|
| 3441 |
|
|
|
| 3442 |
|
|
-- 5a
|
| 3443 |
|
|
component mul5a
|
| 3444 |
|
|
port (
|
| 3445 |
|
|
in_mul5a : in std_logic_vector(7 downto 0);
|
| 3446 |
|
|
out_mul5a : out std_logic_vector(7 downto 0)
|
| 3447 |
|
|
);
|
| 3448 |
|
|
end component;
|
| 3449 |
|
|
|
| 3450 |
|
|
-- 58
|
| 3451 |
|
|
component mul58
|
| 3452 |
|
|
port (
|
| 3453 |
|
|
in_mul58 : in std_logic_vector(7 downto 0);
|
| 3454 |
|
|
out_mul58 : out std_logic_vector(7 downto 0)
|
| 3455 |
|
|
);
|
| 3456 |
|
|
end component;
|
| 3457 |
|
|
|
| 3458 |
|
|
|
| 3459 |
|
|
-- db
|
| 3460 |
|
|
component muldb
|
| 3461 |
|
|
port (
|
| 3462 |
|
|
in_muldb : in std_logic_vector(7 downto 0);
|
| 3463 |
|
|
out_muldb : out std_logic_vector(7 downto 0)
|
| 3464 |
|
|
);
|
| 3465 |
|
|
end component;
|
| 3466 |
|
|
|
| 3467 |
|
|
|
| 3468 |
|
|
-- 9e
|
| 3469 |
|
|
component mul9e
|
| 3470 |
|
|
port (
|
| 3471 |
|
|
in_mul9e : in std_logic_vector(7 downto 0);
|
| 3472 |
|
|
out_mul9e : out std_logic_vector(7 downto 0)
|
| 3473 |
|
|
);
|
| 3474 |
|
|
end component;
|
| 3475 |
|
|
|
| 3476 |
|
|
|
| 3477 |
|
|
-- 56
|
| 3478 |
|
|
component mul56
|
| 3479 |
|
|
port (
|
| 3480 |
|
|
in_mul56 : in std_logic_vector(7 downto 0);
|
| 3481 |
|
|
out_mul56 : out std_logic_vector(7 downto 0)
|
| 3482 |
|
|
);
|
| 3483 |
|
|
end component;
|
| 3484 |
|
|
|
| 3485 |
|
|
|
| 3486 |
|
|
-- 82
|
| 3487 |
|
|
component mul82
|
| 3488 |
|
|
port (
|
| 3489 |
|
|
in_mul82 : in std_logic_vector(7 downto 0);
|
| 3490 |
|
|
out_mul82 : out std_logic_vector(7 downto 0)
|
| 3491 |
|
|
);
|
| 3492 |
|
|
end component;
|
| 3493 |
|
|
|
| 3494 |
|
|
|
| 3495 |
|
|
-- f3
|
| 3496 |
|
|
component mulf3
|
| 3497 |
|
|
port (
|
| 3498 |
|
|
in_mulf3 : in std_logic_vector(7 downto 0);
|
| 3499 |
|
|
out_mulf3 : out std_logic_vector(7 downto 0)
|
| 3500 |
|
|
);
|
| 3501 |
|
|
end component;
|
| 3502 |
|
|
|
| 3503 |
|
|
|
| 3504 |
|
|
-- 1e
|
| 3505 |
|
|
component mul1e
|
| 3506 |
|
|
port (
|
| 3507 |
|
|
in_mul1e : in std_logic_vector(7 downto 0);
|
| 3508 |
|
|
out_mul1e : out std_logic_vector(7 downto 0)
|
| 3509 |
|
|
);
|
| 3510 |
|
|
end component;
|
| 3511 |
|
|
|
| 3512 |
|
|
|
| 3513 |
|
|
-- c6
|
| 3514 |
|
|
component mulc6
|
| 3515 |
|
|
port (
|
| 3516 |
|
|
in_mulc6 : in std_logic_vector(7 downto 0);
|
| 3517 |
|
|
out_mulc6 : out std_logic_vector(7 downto 0)
|
| 3518 |
|
|
);
|
| 3519 |
|
|
end component;
|
| 3520 |
|
|
|
| 3521 |
|
|
|
| 3522 |
|
|
-- 68
|
| 3523 |
|
|
component mul68
|
| 3524 |
|
|
port (
|
| 3525 |
|
|
in_mul68 : in std_logic_vector(7 downto 0);
|
| 3526 |
|
|
out_mul68 : out std_logic_vector(7 downto 0)
|
| 3527 |
|
|
);
|
| 3528 |
|
|
end component;
|
| 3529 |
|
|
|
| 3530 |
|
|
|
| 3531 |
|
|
-- e5
|
| 3532 |
|
|
component mule5
|
| 3533 |
|
|
port (
|
| 3534 |
|
|
in_mule5 : in std_logic_vector(7 downto 0);
|
| 3535 |
|
|
out_mule5 : out std_logic_vector(7 downto 0)
|
| 3536 |
|
|
);
|
| 3537 |
|
|
end component;
|
| 3538 |
|
|
|
| 3539 |
|
|
|
| 3540 |
|
|
-- 02
|
| 3541 |
|
|
component mul02
|
| 3542 |
|
|
port (
|
| 3543 |
|
|
in_mul02 : in std_logic_vector(7 downto 0);
|
| 3544 |
|
|
out_mul02 : out std_logic_vector(7 downto 0)
|
| 3545 |
|
|
);
|
| 3546 |
|
|
end component;
|
| 3547 |
|
|
|
| 3548 |
|
|
|
| 3549 |
|
|
-- a1
|
| 3550 |
|
|
component mula1
|
| 3551 |
|
|
port (
|
| 3552 |
|
|
in_mula1 : in std_logic_vector(7 downto 0);
|
| 3553 |
|
|
out_mula1 : out std_logic_vector(7 downto 0)
|
| 3554 |
|
|
);
|
| 3555 |
|
|
end component;
|
| 3556 |
|
|
|
| 3557 |
|
|
|
| 3558 |
|
|
-- fc
|
| 3559 |
|
|
component mulfc
|
| 3560 |
|
|
port (
|
| 3561 |
|
|
in_mulfc : in std_logic_vector(7 downto 0);
|
| 3562 |
|
|
out_mulfc : out std_logic_vector(7 downto 0)
|
| 3563 |
|
|
);
|
| 3564 |
|
|
end component;
|
| 3565 |
|
|
|
| 3566 |
|
|
|
| 3567 |
|
|
-- c1
|
| 3568 |
|
|
component mulc1
|
| 3569 |
|
|
port (
|
| 3570 |
|
|
in_mulc1 : in std_logic_vector(7 downto 0);
|
| 3571 |
|
|
out_mulc1 : out std_logic_vector(7 downto 0)
|
| 3572 |
|
|
);
|
| 3573 |
|
|
end component;
|
| 3574 |
|
|
|
| 3575 |
|
|
|
| 3576 |
|
|
-- 47
|
| 3577 |
|
|
component mul47
|
| 3578 |
|
|
port (
|
| 3579 |
|
|
in_mul47 : in std_logic_vector(7 downto 0);
|
| 3580 |
|
|
out_mul47 : out std_logic_vector(7 downto 0)
|
| 3581 |
|
|
);
|
| 3582 |
|
|
end component;
|
| 3583 |
|
|
|
| 3584 |
|
|
|
| 3585 |
|
|
|
| 3586 |
|
|
-- ae
|
| 3587 |
|
|
component mulae
|
| 3588 |
|
|
port (
|
| 3589 |
|
|
in_mulae : in std_logic_vector(7 downto 0);
|
| 3590 |
|
|
out_mulae : out std_logic_vector(7 downto 0)
|
| 3591 |
|
|
);
|
| 3592 |
|
|
end component;
|
| 3593 |
|
|
|
| 3594 |
|
|
|
| 3595 |
|
|
|
| 3596 |
|
|
-- 3d
|
| 3597 |
|
|
component mul3d
|
| 3598 |
|
|
port (
|
| 3599 |
|
|
in_mul3d : in std_logic_vector(7 downto 0);
|
| 3600 |
|
|
out_mul3d : out std_logic_vector(7 downto 0)
|
| 3601 |
|
|
);
|
| 3602 |
|
|
end component;
|
| 3603 |
|
|
|
| 3604 |
|
|
|
| 3605 |
|
|
|
| 3606 |
|
|
-- 19
|
| 3607 |
|
|
component mul19
|
| 3608 |
|
|
port (
|
| 3609 |
|
|
in_mul19 : in std_logic_vector(7 downto 0);
|
| 3610 |
|
|
out_mul19 : out std_logic_vector(7 downto 0)
|
| 3611 |
|
|
);
|
| 3612 |
|
|
end component;
|
| 3613 |
|
|
|
| 3614 |
|
|
|
| 3615 |
|
|
-- 03
|
| 3616 |
|
|
component mul03
|
| 3617 |
|
|
port (
|
| 3618 |
|
|
in_mul03 : in std_logic_vector(7 downto 0);
|
| 3619 |
|
|
out_mul03 : out std_logic_vector(7 downto 0)
|
| 3620 |
|
|
);
|
| 3621 |
|
|
end component;
|
| 3622 |
|
|
|
| 3623 |
|
|
|
| 3624 |
|
|
-- declaring internal signals
|
| 3625 |
|
|
signal m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15,
|
| 3626 |
|
|
m16, m17, m18, m19, m20, m21, m22, m23 : std_logic_vector(7 downto 0);
|
| 3627 |
|
|
signal s00,s01,s02,s03,s10,s11,s12,s13, s20, s21, s22, s23 : std_logic_vector(7 downto 0);
|
| 3628 |
|
|
signal m0_01,m1_a4,m2_55,m3_87,m4_5a,m5_58,m6_db,m7_9e,
|
| 3629 |
|
|
m0_a4,m1_56,m2_82,m3_f3,m4_1e,m5_c6,m6_68,m7_e5,
|
| 3630 |
|
|
m0_02,m1_a1,m2_fc,m3_c1,m4_47,m5_ae,m6_3d,m7_19,
|
| 3631 |
|
|
m0_a4_1,m1_55,m2_87,m3_5a,m4_58,m5_db,m6_9e,m7_03 : std_logic_vector(7 downto 0);
|
| 3632 |
|
|
signal m8_01,m9_a4,m10_55,m11_87,m12_5a,m13_58,m14_db,m15_9e,
|
| 3633 |
|
|
m8_a4,m9_56,m10_82,m11_f3,m12_1e,m13_c6,m14_68,m15_e5,
|
| 3634 |
|
|
m8_02,m9_a1,m10_fc,m11_c1,m12_47,m13_ae,m14_3d,m15_19,
|
| 3635 |
|
|
m8_a4_1,m9_55,m10_87,m11_5a,m12_58,m13_db,m14_9e,m15_03 : std_logic_vector(7 downto 0);
|
| 3636 |
|
|
signal m16_01,m17_a4,m18_55,m19_87,m20_5a,m21_58,m22_db,m23_9e,
|
| 3637 |
|
|
m16_a4,m17_56,m18_82,m19_f3,m20_1e,m21_c6,m22_68,m23_e5,
|
| 3638 |
|
|
m16_02,m17_a1,m18_fc,m19_c1,m20_47,m21_ae,m22_3d,m23_19,
|
| 3639 |
|
|
m16_a4_1,m17_55,m18_87,m19_5a,m20_58,m21_db,m22_9e,m23_03 : std_logic_vector(7 downto 0);
|
| 3640 |
|
|
|
| 3641 |
|
|
|
| 3642 |
|
|
-- begin architecture description
|
| 3643 |
|
|
begin
|
| 3644 |
|
|
|
| 3645 |
|
|
-- first, we separate the input to the respective m
|
| 3646 |
|
|
-- for s0j j=0..3
|
| 3647 |
|
|
m0 <= in_rs192(7 downto 0);
|
| 3648 |
|
|
m1 <= in_rs192(15 downto 8);
|
| 3649 |
|
|
m2 <= in_rs192(23 downto 16);
|
| 3650 |
|
|
m3 <= in_rs192(31 downto 24);
|
| 3651 |
|
|
m4 <= in_rs192(39 downto 32);
|
| 3652 |
|
|
m5 <= in_rs192(47 downto 40);
|
| 3653 |
|
|
m6 <= in_rs192(55 downto 48);
|
| 3654 |
|
|
m7 <= in_rs192(63 downto 56);
|
| 3655 |
|
|
|
| 3656 |
|
|
-- for s1j j=0..3
|
| 3657 |
|
|
m8 <= in_rs192(71 downto 64);
|
| 3658 |
|
|
m9 <= in_rs192(79 downto 72);
|
| 3659 |
|
|
m10 <= in_rs192(87 downto 80);
|
| 3660 |
|
|
m11 <= in_rs192(95 downto 88);
|
| 3661 |
|
|
m12 <= in_rs192(103 downto 96);
|
| 3662 |
|
|
m13 <= in_rs192(111 downto 104);
|
| 3663 |
|
|
m14 <= in_rs192(119 downto 112);
|
| 3664 |
|
|
m15 <= in_rs192(127 downto 120);
|
| 3665 |
|
|
|
| 3666 |
|
|
-- for s2j j=0..3
|
| 3667 |
|
|
m16 <= in_rs192(135 downto 128);
|
| 3668 |
|
|
m17 <= in_rs192(143 downto 136);
|
| 3669 |
|
|
m18 <= in_rs192(151 downto 144);
|
| 3670 |
|
|
m19 <= in_rs192(159 downto 152);
|
| 3671 |
|
|
m20 <= in_rs192(167 downto 160);
|
| 3672 |
|
|
m21 <= in_rs192(175 downto 168);
|
| 3673 |
|
|
m22 <= in_rs192(183 downto 176);
|
| 3674 |
|
|
m23 <= in_rs192(191 downto 184);
|
| 3675 |
|
|
|
| 3676 |
|
|
|
| 3677 |
|
|
-- after separating signals, we drive them to multipliers
|
| 3678 |
|
|
-- the first line of m0..7 forms s00
|
| 3679 |
|
|
m0_with_01: mul01
|
| 3680 |
|
|
port map (
|
| 3681 |
|
|
in_mul01 => m0,
|
| 3682 |
|
|
out_mul01 => m0_01
|
| 3683 |
|
|
);
|
| 3684 |
|
|
|
| 3685 |
|
|
m1_with_a4: mula4
|
| 3686 |
|
|
port map (
|
| 3687 |
|
|
in_mula4 => m1,
|
| 3688 |
|
|
out_mula4 => m1_a4
|
| 3689 |
|
|
);
|
| 3690 |
|
|
|
| 3691 |
|
|
m2_with_55: mul55
|
| 3692 |
|
|
port map (
|
| 3693 |
|
|
in_mul55 => m2,
|
| 3694 |
|
|
out_mul55 => m2_55
|
| 3695 |
|
|
);
|
| 3696 |
|
|
|
| 3697 |
|
|
m3_with_87: mul87
|
| 3698 |
|
|
port map (
|
| 3699 |
|
|
in_mul87 => m3,
|
| 3700 |
|
|
out_mul87 => m3_87
|
| 3701 |
|
|
);
|
| 3702 |
|
|
|
| 3703 |
|
|
m4_with_5a: mul5a
|
| 3704 |
|
|
port map (
|
| 3705 |
|
|
in_mul5a => m4,
|
| 3706 |
|
|
out_mul5a => m4_5a
|
| 3707 |
|
|
);
|
| 3708 |
|
|
|
| 3709 |
|
|
m5_with_58: mul58
|
| 3710 |
|
|
port map (
|
| 3711 |
|
|
in_mul58 => m5,
|
| 3712 |
|
|
out_mul58 => m5_58
|
| 3713 |
|
|
);
|
| 3714 |
|
|
|
| 3715 |
|
|
m6_with_db: muldb
|
| 3716 |
|
|
port map (
|
| 3717 |
|
|
in_muldb => m6,
|
| 3718 |
|
|
out_muldb => m6_db
|
| 3719 |
|
|
);
|
| 3720 |
|
|
|
| 3721 |
|
|
m7_with_9e: mul9e
|
| 3722 |
|
|
port map (
|
| 3723 |
|
|
in_mul9e => m7,
|
| 3724 |
|
|
out_mul9e => m7_9e
|
| 3725 |
|
|
);
|
| 3726 |
|
|
|
| 3727 |
|
|
-- the second row creates s01
|
| 3728 |
|
|
m0_with_a4: mula4
|
| 3729 |
|
|
port map (
|
| 3730 |
|
|
in_mula4 => m0,
|
| 3731 |
|
|
out_mula4 => m0_a4
|
| 3732 |
|
|
);
|
| 3733 |
|
|
|
| 3734 |
|
|
m1_with_56: mul56
|
| 3735 |
|
|
port map (
|
| 3736 |
|
|
in_mul56 => m1,
|
| 3737 |
|
|
out_mul56 => m1_56
|
| 3738 |
|
|
);
|
| 3739 |
|
|
|
| 3740 |
|
|
m2_with_82: mul82
|
| 3741 |
|
|
port map (
|
| 3742 |
|
|
in_mul82 => m2,
|
| 3743 |
|
|
out_mul82 => m2_82
|
| 3744 |
|
|
);
|
| 3745 |
|
|
|
| 3746 |
|
|
m3_with_f3: mulf3
|
| 3747 |
|
|
port map (
|
| 3748 |
|
|
in_mulf3 => m3,
|
| 3749 |
|
|
out_mulf3 => m3_f3
|
| 3750 |
|
|
);
|
| 3751 |
|
|
|
| 3752 |
|
|
m4_with_1e: mul1e
|
| 3753 |
|
|
port map (
|
| 3754 |
|
|
in_mul1e => m4,
|
| 3755 |
|
|
out_mul1e => m4_1e
|
| 3756 |
|
|
);
|
| 3757 |
|
|
|
| 3758 |
|
|
m5_with_c6: mulc6
|
| 3759 |
|
|
port map (
|
| 3760 |
|
|
in_mulc6 => m5,
|
| 3761 |
|
|
out_mulc6 => m5_c6
|
| 3762 |
|
|
);
|
| 3763 |
|
|
|
| 3764 |
|
|
m6_with_68: mul68
|
| 3765 |
|
|
port map (
|
| 3766 |
|
|
in_mul68 => m6,
|
| 3767 |
|
|
out_mul68 => m6_68
|
| 3768 |
|
|
);
|
| 3769 |
|
|
|
| 3770 |
|
|
m7_with_e5: mule5
|
| 3771 |
|
|
port map (
|
| 3772 |
|
|
in_mule5 => m7,
|
| 3773 |
|
|
out_mule5 => m7_e5
|
| 3774 |
|
|
);
|
| 3775 |
|
|
|
| 3776 |
|
|
-- the third row creates s02
|
| 3777 |
|
|
m0_with_02: mul02
|
| 3778 |
|
|
port map (
|
| 3779 |
|
|
in_mul02 => m0,
|
| 3780 |
|
|
out_mul02 => m0_02
|
| 3781 |
|
|
);
|
| 3782 |
|
|
|
| 3783 |
|
|
m1_with_a1: mula1
|
| 3784 |
|
|
port map (
|
| 3785 |
|
|
in_mula1 => m1,
|
| 3786 |
|
|
out_mula1 => m1_a1
|
| 3787 |
|
|
);
|
| 3788 |
|
|
|
| 3789 |
|
|
m2_with_fc: mulfc
|
| 3790 |
|
|
port map (
|
| 3791 |
|
|
in_mulfc => m2,
|
| 3792 |
|
|
out_mulfc => m2_fc
|
| 3793 |
|
|
);
|
| 3794 |
|
|
|
| 3795 |
|
|
m3_with_c1: mulc1
|
| 3796 |
|
|
port map (
|
| 3797 |
|
|
in_mulc1 => m3,
|
| 3798 |
|
|
out_mulc1 => m3_c1
|
| 3799 |
|
|
);
|
| 3800 |
|
|
|
| 3801 |
|
|
m4_with_47: mul47
|
| 3802 |
|
|
port map (
|
| 3803 |
|
|
in_mul47 => m4,
|
| 3804 |
|
|
out_mul47 => m4_47
|
| 3805 |
|
|
);
|
| 3806 |
|
|
|
| 3807 |
|
|
m5_with_ae: mulae
|
| 3808 |
|
|
port map (
|
| 3809 |
|
|
in_mulae => m5,
|
| 3810 |
|
|
out_mulae => m5_ae
|
| 3811 |
|
|
);
|
| 3812 |
|
|
|
| 3813 |
|
|
m6_with_3d: mul3d
|
| 3814 |
|
|
port map (
|
| 3815 |
|
|
in_mul3d => m6,
|
| 3816 |
|
|
out_mul3d => m6_3d
|
| 3817 |
|
|
);
|
| 3818 |
|
|
|
| 3819 |
|
|
m7_with_19: mul19
|
| 3820 |
|
|
port map (
|
| 3821 |
|
|
in_mul19 => m7,
|
| 3822 |
|
|
out_mul19 => m7_19
|
| 3823 |
|
|
);
|
| 3824 |
|
|
|
| 3825 |
|
|
-- the fourth row creates s03
|
| 3826 |
|
|
m0_with_a4_1: mula4
|
| 3827 |
|
|
port map (
|
| 3828 |
|
|
in_mula4 => m0,
|
| 3829 |
|
|
out_mula4 => m0_a4_1
|
| 3830 |
|
|
);
|
| 3831 |
|
|
|
| 3832 |
|
|
m1_with_55: mul55
|
| 3833 |
|
|
port map (
|
| 3834 |
|
|
in_mul55 => m1,
|
| 3835 |
|
|
out_mul55 => m1_55
|
| 3836 |
|
|
);
|
| 3837 |
|
|
|
| 3838 |
|
|
m2_with_87: mul87
|
| 3839 |
|
|
port map (
|
| 3840 |
|
|
in_mul87 => m2,
|
| 3841 |
|
|
out_mul87 => m2_87
|
| 3842 |
|
|
);
|
| 3843 |
|
|
|
| 3844 |
|
|
m3_with_5a: mul5a
|
| 3845 |
|
|
port map (
|
| 3846 |
|
|
in_mul5a => m3,
|
| 3847 |
|
|
out_mul5a => m3_5a
|
| 3848 |
|
|
);
|
| 3849 |
|
|
|
| 3850 |
|
|
m4_with_58: mul58
|
| 3851 |
|
|
port map (
|
| 3852 |
|
|
in_mul58 => m4,
|
| 3853 |
|
|
out_mul58 => m4_58
|
| 3854 |
|
|
);
|
| 3855 |
|
|
|
| 3856 |
|
|
m5_with_db: muldb
|
| 3857 |
|
|
port map (
|
| 3858 |
|
|
in_muldb => m5,
|
| 3859 |
|
|
out_muldb => m5_db
|
| 3860 |
|
|
);
|
| 3861 |
|
|
|
| 3862 |
|
|
m6_with_9e: mul9e
|
| 3863 |
|
|
port map (
|
| 3864 |
|
|
in_mul9e => m6,
|
| 3865 |
|
|
out_mul9e => m6_9e
|
| 3866 |
|
|
);
|
| 3867 |
|
|
|
| 3868 |
|
|
m7_with_03: mul03
|
| 3869 |
|
|
port map (
|
| 3870 |
|
|
in_mul03 => m7,
|
| 3871 |
|
|
out_mul03 => m7_03
|
| 3872 |
|
|
);
|
| 3873 |
|
|
|
| 3874 |
|
|
|
| 3875 |
|
|
-- we create the s1,j j=0..3
|
| 3876 |
|
|
-- the first row of m8..15 creates the s10
|
| 3877 |
|
|
m8_with_01: mul01
|
| 3878 |
|
|
port map (
|
| 3879 |
|
|
in_mul01 => m8,
|
| 3880 |
|
|
out_mul01 => m8_01
|
| 3881 |
|
|
);
|
| 3882 |
|
|
|
| 3883 |
|
|
m9_with_a4: mula4
|
| 3884 |
|
|
port map (
|
| 3885 |
|
|
in_mula4 => m9,
|
| 3886 |
|
|
out_mula4 => m9_a4
|
| 3887 |
|
|
);
|
| 3888 |
|
|
|
| 3889 |
|
|
m10_with_55: mul55
|
| 3890 |
|
|
port map (
|
| 3891 |
|
|
in_mul55 => m10,
|
| 3892 |
|
|
out_mul55 => m10_55
|
| 3893 |
|
|
);
|
| 3894 |
|
|
|
| 3895 |
|
|
m11_with_87: mul87
|
| 3896 |
|
|
port map (
|
| 3897 |
|
|
in_mul87 => m11,
|
| 3898 |
|
|
out_mul87 => m11_87
|
| 3899 |
|
|
);
|
| 3900 |
|
|
|
| 3901 |
|
|
m12_with_5a: mul5a
|
| 3902 |
|
|
port map (
|
| 3903 |
|
|
in_mul5a => m12,
|
| 3904 |
|
|
out_mul5a => m12_5a
|
| 3905 |
|
|
);
|
| 3906 |
|
|
|
| 3907 |
|
|
m13_with_58: mul58
|
| 3908 |
|
|
port map (
|
| 3909 |
|
|
in_mul58 => m13,
|
| 3910 |
|
|
out_mul58 => m13_58
|
| 3911 |
|
|
);
|
| 3912 |
|
|
|
| 3913 |
|
|
m14_with_db: muldb
|
| 3914 |
|
|
port map (
|
| 3915 |
|
|
in_muldb => m14,
|
| 3916 |
|
|
out_muldb => m14_db
|
| 3917 |
|
|
);
|
| 3918 |
|
|
|
| 3919 |
|
|
m15_with_9e: mul9e
|
| 3920 |
|
|
port map (
|
| 3921 |
|
|
in_mul9e => m15,
|
| 3922 |
|
|
out_mul9e => m15_9e
|
| 3923 |
|
|
);
|
| 3924 |
|
|
|
| 3925 |
|
|
-- the second row creates s11
|
| 3926 |
|
|
m8_with_a4: mula4
|
| 3927 |
|
|
port map (
|
| 3928 |
|
|
in_mula4 => m8,
|
| 3929 |
|
|
out_mula4 => m8_a4
|
| 3930 |
|
|
);
|
| 3931 |
|
|
|
| 3932 |
|
|
m9_with_56: mul56
|
| 3933 |
|
|
port map (
|
| 3934 |
|
|
in_mul56 => m9,
|
| 3935 |
|
|
out_mul56 => m9_56
|
| 3936 |
|
|
);
|
| 3937 |
|
|
|
| 3938 |
|
|
m10_with_82: mul82
|
| 3939 |
|
|
port map (
|
| 3940 |
|
|
in_mul82 => m10,
|
| 3941 |
|
|
out_mul82 => m10_82
|
| 3942 |
|
|
);
|
| 3943 |
|
|
|
| 3944 |
|
|
m11_with_f3: mulf3
|
| 3945 |
|
|
port map (
|
| 3946 |
|
|
in_mulf3 => m11,
|
| 3947 |
|
|
out_mulf3 => m11_f3
|
| 3948 |
|
|
);
|
| 3949 |
|
|
|
| 3950 |
|
|
m12_with_1e: mul1e
|
| 3951 |
|
|
port map (
|
| 3952 |
|
|
in_mul1e => m12,
|
| 3953 |
|
|
out_mul1e => m12_1e
|
| 3954 |
|
|
);
|
| 3955 |
|
|
|
| 3956 |
|
|
m13_with_c6: mulc6
|
| 3957 |
|
|
port map (
|
| 3958 |
|
|
in_mulc6 => m13,
|
| 3959 |
|
|
out_mulc6 => m13_c6
|
| 3960 |
|
|
);
|
| 3961 |
|
|
|
| 3962 |
|
|
m14_with_68: mul68
|
| 3963 |
|
|
port map (
|
| 3964 |
|
|
in_mul68 => m14,
|
| 3965 |
|
|
out_mul68 => m14_68
|
| 3966 |
|
|
);
|
| 3967 |
|
|
|
| 3968 |
|
|
m15_with_e5: mule5
|
| 3969 |
|
|
port map (
|
| 3970 |
|
|
in_mule5 => m15,
|
| 3971 |
|
|
out_mule5 => m15_e5
|
| 3972 |
|
|
);
|
| 3973 |
|
|
|
| 3974 |
|
|
-- the third row creates s12
|
| 3975 |
|
|
m8_with_02: mul02
|
| 3976 |
|
|
port map (
|
| 3977 |
|
|
in_mul02 => m8,
|
| 3978 |
|
|
out_mul02 => m8_02
|
| 3979 |
|
|
);
|
| 3980 |
|
|
|
| 3981 |
|
|
m9_with_a1: mula1
|
| 3982 |
|
|
port map (
|
| 3983 |
|
|
in_mula1 => m9,
|
| 3984 |
|
|
out_mula1 => m9_a1
|
| 3985 |
|
|
);
|
| 3986 |
|
|
|
| 3987 |
|
|
m10_with_fc: mulfc
|
| 3988 |
|
|
port map (
|
| 3989 |
|
|
in_mulfc => m10,
|
| 3990 |
|
|
out_mulfc => m10_fc
|
| 3991 |
|
|
);
|
| 3992 |
|
|
|
| 3993 |
|
|
m11_with_c1: mulc1
|
| 3994 |
|
|
port map (
|
| 3995 |
|
|
in_mulc1 => m11,
|
| 3996 |
|
|
out_mulc1 => m11_c1
|
| 3997 |
|
|
);
|
| 3998 |
|
|
|
| 3999 |
|
|
m12_with_47: mul47
|
| 4000 |
|
|
port map (
|
| 4001 |
|
|
in_mul47 => m12,
|
| 4002 |
|
|
out_mul47 => m12_47
|
| 4003 |
|
|
);
|
| 4004 |
|
|
|
| 4005 |
|
|
m13_with_ae: mulae
|
| 4006 |
|
|
port map (
|
| 4007 |
|
|
in_mulae => m13,
|
| 4008 |
|
|
out_mulae => m13_ae
|
| 4009 |
|
|
);
|
| 4010 |
|
|
|
| 4011 |
|
|
m14_with_3d: mul3d
|
| 4012 |
|
|
port map (
|
| 4013 |
|
|
in_mul3d => m14,
|
| 4014 |
|
|
out_mul3d => m14_3d
|
| 4015 |
|
|
);
|
| 4016 |
|
|
|
| 4017 |
|
|
m15_with_19: mul19
|
| 4018 |
|
|
port map (
|
| 4019 |
|
|
in_mul19 => m15,
|
| 4020 |
|
|
out_mul19 => m15_19
|
| 4021 |
|
|
);
|
| 4022 |
|
|
|
| 4023 |
|
|
-- the fourth row creates s13
|
| 4024 |
|
|
m8_with_a4_1: mula4
|
| 4025 |
|
|
port map (
|
| 4026 |
|
|
in_mula4 => m8,
|
| 4027 |
|
|
out_mula4 => m8_a4_1
|
| 4028 |
|
|
);
|
| 4029 |
|
|
|
| 4030 |
|
|
m9_with_55: mul55
|
| 4031 |
|
|
port map (
|
| 4032 |
|
|
in_mul55 => m9,
|
| 4033 |
|
|
out_mul55 => m9_55
|
| 4034 |
|
|
);
|
| 4035 |
|
|
|
| 4036 |
|
|
m10_with_87: mul87
|
| 4037 |
|
|
port map (
|
| 4038 |
|
|
in_mul87 => m10,
|
| 4039 |
|
|
out_mul87 => m10_87
|
| 4040 |
|
|
);
|
| 4041 |
|
|
|
| 4042 |
|
|
m11_with_5a: mul5a
|
| 4043 |
|
|
port map (
|
| 4044 |
|
|
in_mul5a => m11,
|
| 4045 |
|
|
out_mul5a => m11_5a
|
| 4046 |
|
|
);
|
| 4047 |
|
|
|
| 4048 |
|
|
m12_with_58: mul58
|
| 4049 |
|
|
port map (
|
| 4050 |
|
|
in_mul58 => m12,
|
| 4051 |
|
|
out_mul58 => m12_58
|
| 4052 |
|
|
);
|
| 4053 |
|
|
|
| 4054 |
|
|
m13_with_db: muldb
|
| 4055 |
|
|
port map (
|
| 4056 |
|
|
in_muldb => m13,
|
| 4057 |
|
|
out_muldb => m13_db
|
| 4058 |
|
|
);
|
| 4059 |
|
|
|
| 4060 |
|
|
m14_with_9e: mul9e
|
| 4061 |
|
|
port map (
|
| 4062 |
|
|
in_mul9e => m14,
|
| 4063 |
|
|
out_mul9e => m14_9e
|
| 4064 |
|
|
);
|
| 4065 |
|
|
|
| 4066 |
|
|
m15_with_03: mul03
|
| 4067 |
|
|
port map (
|
| 4068 |
|
|
in_mul03 => m15,
|
| 4069 |
|
|
out_mul03 => m15_03
|
| 4070 |
|
|
);
|
| 4071 |
|
|
|
| 4072 |
|
|
-- we create the s2,j j=0..3
|
| 4073 |
|
|
-- the first row of m16..23 creates the s20
|
| 4074 |
|
|
m16_with_01: mul01
|
| 4075 |
|
|
port map (
|
| 4076 |
|
|
in_mul01 => m16,
|
| 4077 |
|
|
out_mul01 => m16_01
|
| 4078 |
|
|
);
|
| 4079 |
|
|
|
| 4080 |
|
|
m17_with_a4: mula4
|
| 4081 |
|
|
port map (
|
| 4082 |
|
|
in_mula4 => m17,
|
| 4083 |
|
|
out_mula4 => m17_a4
|
| 4084 |
|
|
);
|
| 4085 |
|
|
|
| 4086 |
|
|
m18_with_55: mul55
|
| 4087 |
|
|
port map (
|
| 4088 |
|
|
in_mul55 => m18,
|
| 4089 |
|
|
out_mul55 => m18_55
|
| 4090 |
|
|
);
|
| 4091 |
|
|
|
| 4092 |
|
|
m19_with_87: mul87
|
| 4093 |
|
|
port map (
|
| 4094 |
|
|
in_mul87 => m19,
|
| 4095 |
|
|
out_mul87 => m19_87
|
| 4096 |
|
|
);
|
| 4097 |
|
|
|
| 4098 |
|
|
m20_with_5a: mul5a
|
| 4099 |
|
|
port map (
|
| 4100 |
|
|
in_mul5a => m20,
|
| 4101 |
|
|
out_mul5a => m20_5a
|
| 4102 |
|
|
);
|
| 4103 |
|
|
|
| 4104 |
|
|
m21_with_58: mul58
|
| 4105 |
|
|
port map (
|
| 4106 |
|
|
in_mul58 => m21,
|
| 4107 |
|
|
out_mul58 => m21_58
|
| 4108 |
|
|
);
|
| 4109 |
|
|
|
| 4110 |
|
|
m22_with_db: muldb
|
| 4111 |
|
|
port map (
|
| 4112 |
|
|
in_muldb => m22,
|
| 4113 |
|
|
out_muldb => m22_db
|
| 4114 |
|
|
);
|
| 4115 |
|
|
|
| 4116 |
|
|
m23_with_9e: mul9e
|
| 4117 |
|
|
port map (
|
| 4118 |
|
|
in_mul9e => m23,
|
| 4119 |
|
|
out_mul9e => m23_9e
|
| 4120 |
|
|
);
|
| 4121 |
|
|
|
| 4122 |
|
|
-- the second row creates s21
|
| 4123 |
|
|
m16_with_a4: mula4
|
| 4124 |
|
|
port map (
|
| 4125 |
|
|
in_mula4 => m16,
|
| 4126 |
|
|
out_mula4 => m16_a4
|
| 4127 |
|
|
);
|
| 4128 |
|
|
|
| 4129 |
|
|
m17_with_56: mul56
|
| 4130 |
|
|
port map (
|
| 4131 |
|
|
in_mul56 => m17,
|
| 4132 |
|
|
out_mul56 => m17_56
|
| 4133 |
|
|
);
|
| 4134 |
|
|
|
| 4135 |
|
|
m18_with_82: mul82
|
| 4136 |
|
|
port map (
|
| 4137 |
|
|
in_mul82 => m18,
|
| 4138 |
|
|
out_mul82 => m18_82
|
| 4139 |
|
|
);
|
| 4140 |
|
|
|
| 4141 |
|
|
m19_with_f3: mulf3
|
| 4142 |
|
|
port map (
|
| 4143 |
|
|
in_mulf3 => m19,
|
| 4144 |
|
|
out_mulf3 => m19_f3
|
| 4145 |
|
|
);
|
| 4146 |
|
|
|
| 4147 |
|
|
m20_with_1e: mul1e
|
| 4148 |
|
|
port map (
|
| 4149 |
|
|
in_mul1e => m20,
|
| 4150 |
|
|
out_mul1e => m20_1e
|
| 4151 |
|
|
);
|
| 4152 |
|
|
|
| 4153 |
|
|
m21_with_c6: mulc6
|
| 4154 |
|
|
port map (
|
| 4155 |
|
|
in_mulc6 => m21,
|
| 4156 |
|
|
out_mulc6 => m21_c6
|
| 4157 |
|
|
);
|
| 4158 |
|
|
|
| 4159 |
|
|
m22_with_68: mul68
|
| 4160 |
|
|
port map (
|
| 4161 |
|
|
in_mul68 => m22,
|
| 4162 |
|
|
out_mul68 => m22_68
|
| 4163 |
|
|
);
|
| 4164 |
|
|
|
| 4165 |
|
|
m23_with_e5: mule5
|
| 4166 |
|
|
port map (
|
| 4167 |
|
|
in_mule5 => m23,
|
| 4168 |
|
|
out_mule5 => m23_e5
|
| 4169 |
|
|
);
|
| 4170 |
|
|
|
| 4171 |
|
|
-- the third row creates s22
|
| 4172 |
|
|
m16_with_02: mul02
|
| 4173 |
|
|
port map (
|
| 4174 |
|
|
in_mul02 => m16,
|
| 4175 |
|
|
out_mul02 => m16_02
|
| 4176 |
|
|
);
|
| 4177 |
|
|
|
| 4178 |
|
|
m17_with_a1: mula1
|
| 4179 |
|
|
port map (
|
| 4180 |
|
|
in_mula1 => m17,
|
| 4181 |
|
|
out_mula1 => m17_a1
|
| 4182 |
|
|
);
|
| 4183 |
|
|
|
| 4184 |
|
|
m18_with_fc: mulfc
|
| 4185 |
|
|
port map (
|
| 4186 |
|
|
in_mulfc => m18,
|
| 4187 |
|
|
out_mulfc => m18_fc
|
| 4188 |
|
|
);
|
| 4189 |
|
|
|
| 4190 |
|
|
m19_with_c1: mulc1
|
| 4191 |
|
|
port map (
|
| 4192 |
|
|
in_mulc1 => m19,
|
| 4193 |
|
|
out_mulc1 => m19_c1
|
| 4194 |
|
|
);
|
| 4195 |
|
|
|
| 4196 |
|
|
m20_with_47: mul47
|
| 4197 |
|
|
port map (
|
| 4198 |
|
|
in_mul47 => m20,
|
| 4199 |
|
|
out_mul47 => m20_47
|
| 4200 |
|
|
);
|
| 4201 |
|
|
|
| 4202 |
|
|
m21_with_ae: mulae
|
| 4203 |
|
|
port map (
|
| 4204 |
|
|
in_mulae => m21,
|
| 4205 |
|
|
out_mulae => m21_ae
|
| 4206 |
|
|
);
|
| 4207 |
|
|
|
| 4208 |
|
|
m22_with_3d: mul3d
|
| 4209 |
|
|
port map (
|
| 4210 |
|
|
in_mul3d => m22,
|
| 4211 |
|
|
out_mul3d => m22_3d
|
| 4212 |
|
|
);
|
| 4213 |
|
|
|
| 4214 |
|
|
m23_with_19: mul19
|
| 4215 |
|
|
port map (
|
| 4216 |
|
|
in_mul19 => m23,
|
| 4217 |
|
|
out_mul19 => m23_19
|
| 4218 |
|
|
);
|
| 4219 |
|
|
|
| 4220 |
|
|
-- the fourth row creates s23
|
| 4221 |
|
|
m16_with_a4_1: mula4
|
| 4222 |
|
|
port map (
|
| 4223 |
|
|
in_mula4 => m16,
|
| 4224 |
|
|
out_mula4 => m16_a4_1
|
| 4225 |
|
|
);
|
| 4226 |
|
|
|
| 4227 |
|
|
m17_with_55: mul55
|
| 4228 |
|
|
port map (
|
| 4229 |
|
|
in_mul55 => m17,
|
| 4230 |
|
|
out_mul55 => m17_55
|
| 4231 |
|
|
);
|
| 4232 |
|
|
|
| 4233 |
|
|
m18_with_87: mul87
|
| 4234 |
|
|
port map (
|
| 4235 |
|
|
in_mul87 => m18,
|
| 4236 |
|
|
out_mul87 => m18_87
|
| 4237 |
|
|
);
|
| 4238 |
|
|
|
| 4239 |
|
|
m19_with_5a: mul5a
|
| 4240 |
|
|
port map (
|
| 4241 |
|
|
in_mul5a => m19,
|
| 4242 |
|
|
out_mul5a => m19_5a
|
| 4243 |
|
|
);
|
| 4244 |
|
|
|
| 4245 |
|
|
m20_with_58: mul58
|
| 4246 |
|
|
port map (
|
| 4247 |
|
|
in_mul58 => m20,
|
| 4248 |
|
|
out_mul58 => m20_58
|
| 4249 |
|
|
);
|
| 4250 |
|
|
|
| 4251 |
|
|
m21_with_db: muldb
|
| 4252 |
|
|
port map (
|
| 4253 |
|
|
in_muldb => m21,
|
| 4254 |
|
|
out_muldb => m21_db
|
| 4255 |
|
|
);
|
| 4256 |
|
|
|
| 4257 |
|
|
m22_with_9e: mul9e
|
| 4258 |
|
|
port map (
|
| 4259 |
|
|
in_mul9e => m22,
|
| 4260 |
|
|
out_mul9e => m22_9e
|
| 4261 |
|
|
);
|
| 4262 |
|
|
|
| 4263 |
|
|
m23_with_03: mul03
|
| 4264 |
|
|
port map (
|
| 4265 |
|
|
in_mul03 => m23,
|
| 4266 |
|
|
out_mul03 => m23_03
|
| 4267 |
|
|
);
|
| 4268 |
|
|
|
| 4269 |
|
|
-- after getting the results from multipliers
|
| 4270 |
|
|
-- we combine them in order to get the additions
|
| 4271 |
|
|
s00 <= m0_01 XOR m1_a4 XOR m2_55 XOR m3_87 XOR m4_5a XOR m5_58 XOR m6_db XOR m7_9e;
|
| 4272 |
|
|
s01 <= m0_a4 XOR m1_56 XOR m2_82 XOR m3_f3 XOR m4_1e XOR m5_c6 XOR m6_68 XOR m7_e5;
|
| 4273 |
|
|
s02 <= m0_02 XOR m1_a1 XOR m2_fc XOR m3_c1 XOR m4_47 XOR m5_ae XOR m6_3d XOR m7_19;
|
| 4274 |
|
|
s03 <= m0_a4_1 XOR m1_55 XOR m2_87 XOR m3_5a XOR m4_58 XOR m5_db XOR m6_9e XOR m7_03;
|
| 4275 |
|
|
|
| 4276 |
|
|
-- after creating s0,j j=0...3 we form the S0
|
| 4277 |
|
|
-- little endian
|
| 4278 |
|
|
out_Sfirst_rs192 <= s03 & s02 & s01 & s00;
|
| 4279 |
|
|
|
| 4280 |
|
|
s10 <= m8_01 XOR m9_a4 XOR m10_55 XOR m11_87 XOR m12_5a XOR m13_58 XOR m14_db XOR m15_9e;
|
| 4281 |
|
|
s11 <= m8_a4 XOR m9_56 XOR m10_82 XOR m11_f3 XOR m12_1e XOR m13_c6 XOR m14_68 XOR m15_e5;
|
| 4282 |
|
|
s12 <= m8_02 XOR m9_a1 XOR m10_fc XOR m11_c1 XOR m12_47 XOR m13_ae XOR m14_3d XOR m15_19;
|
| 4283 |
|
|
s13 <= m8_a4_1 XOR m9_55 XOR m10_87 XOR m11_5a XOR m12_58 XOR m13_db XOR m14_9e XOR m15_03;
|
| 4284 |
|
|
|
| 4285 |
|
|
-- after creating s1,j j=0...3 we form the S1
|
| 4286 |
|
|
-- little endian
|
| 4287 |
|
|
out_Ssecond_rs192 <= s13 & s12 & s11 & s10;
|
| 4288 |
|
|
|
| 4289 |
|
|
s20 <= m16_01 XOR m17_a4 XOR m18_55 XOR m19_87 XOR m20_5a XOR m21_58 XOR m22_db XOR m23_9e;
|
| 4290 |
|
|
s21 <= m16_a4 XOR m17_56 XOR m18_82 XOR m19_f3 XOR m20_1e XOR m21_c6 XOR m22_68 XOR m23_e5;
|
| 4291 |
|
|
s22 <= m16_02 XOR m17_a1 XOR m18_fc XOR m19_c1 XOR m20_47 XOR m21_ae XOR m22_3d XOR m23_19;
|
| 4292 |
|
|
s23 <= m16_a4_1 XOR m17_55 XOR m18_87 XOR m19_5a XOR m20_58 XOR m21_db XOR m22_9e XOR m23_03;
|
| 4293 |
|
|
|
| 4294 |
|
|
-- after creating s2j j=0...3 we form the S2
|
| 4295 |
|
|
-- little endian
|
| 4296 |
|
|
out_Sthird_rs192 <= s23 & s22 & s21 & s20;
|
| 4297 |
|
|
|
| 4298 |
|
|
|
| 4299 |
|
|
end rs_192_arch;
|
| 4300 |
|
|
|
| 4301 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4302 |
|
|
-- --
|
| 4303 |
|
|
-- new component --
|
| 4304 |
|
|
-- --
|
| 4305 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4306 |
|
|
|
| 4307 |
|
|
--
|
| 4308 |
|
|
-- h function for 192 bits key
|
| 4309 |
|
|
--
|
| 4310 |
|
|
|
| 4311 |
|
|
library ieee;
|
| 4312 |
|
|
use ieee.std_logic_1164.all;
|
| 4313 |
|
|
|
| 4314 |
|
|
entity h_192 is
|
| 4315 |
|
|
port (
|
| 4316 |
|
|
in_h192 : in std_logic_vector(7 downto 0);
|
| 4317 |
|
|
Mfirst_h192,
|
| 4318 |
|
|
Msecond_h192,
|
| 4319 |
|
|
Mthird_h192 : in std_logic_vector(31 downto 0);
|
| 4320 |
|
|
out_h192 : out std_logic_vector(31 downto 0)
|
| 4321 |
|
|
);
|
| 4322 |
|
|
end h_192;
|
| 4323 |
|
|
|
| 4324 |
|
|
architecture h192_arch of h_192 is
|
| 4325 |
|
|
|
| 4326 |
|
|
-- we declare internal signals
|
| 4327 |
|
|
signal from_first_row,
|
| 4328 |
|
|
to_second_row,
|
| 4329 |
|
|
from_second_row,
|
| 4330 |
|
|
to_third_row,
|
| 4331 |
|
|
from_third_row,
|
| 4332 |
|
|
to_fourth_row,
|
| 4333 |
|
|
to_mds : std_logic_vector(31 downto 0);
|
| 4334 |
|
|
|
| 4335 |
|
|
-- we declare all components needed
|
| 4336 |
|
|
component q0
|
| 4337 |
|
|
port (
|
| 4338 |
|
|
in_q0 : in std_logic_vector(7 downto 0);
|
| 4339 |
|
|
out_q0 : out std_logic_vector(7 downto 0)
|
| 4340 |
|
|
);
|
| 4341 |
|
|
end component;
|
| 4342 |
|
|
|
| 4343 |
|
|
component q1
|
| 4344 |
|
|
port (
|
| 4345 |
|
|
in_q1 : in std_logic_vector(7 downto 0);
|
| 4346 |
|
|
out_q1 : out std_logic_vector(7 downto 0)
|
| 4347 |
|
|
);
|
| 4348 |
|
|
end component;
|
| 4349 |
|
|
|
| 4350 |
|
|
component mds
|
| 4351 |
|
|
port (
|
| 4352 |
|
|
y0,
|
| 4353 |
|
|
y1,
|
| 4354 |
|
|
y2,
|
| 4355 |
|
|
y3 : in std_logic_vector(7 downto 0);
|
| 4356 |
|
|
z0,
|
| 4357 |
|
|
z1,
|
| 4358 |
|
|
z2,
|
| 4359 |
|
|
z3 : out std_logic_vector(7 downto 0)
|
| 4360 |
|
|
);
|
| 4361 |
|
|
end component;
|
| 4362 |
|
|
|
| 4363 |
|
|
-- begin architecture description
|
| 4364 |
|
|
begin
|
| 4365 |
|
|
|
| 4366 |
|
|
-- first row of q
|
| 4367 |
|
|
first_q1_1: q1
|
| 4368 |
|
|
port map (
|
| 4369 |
|
|
in_q1 => in_h192,
|
| 4370 |
|
|
out_q1 => from_first_row(7 downto 0)
|
| 4371 |
|
|
);
|
| 4372 |
|
|
|
| 4373 |
|
|
first_q1_2: q1
|
| 4374 |
|
|
port map (
|
| 4375 |
|
|
in_q1 => in_h192,
|
| 4376 |
|
|
out_q1 => from_first_row(15 downto 8)
|
| 4377 |
|
|
);
|
| 4378 |
|
|
|
| 4379 |
|
|
first_q0_1: q0
|
| 4380 |
|
|
port map (
|
| 4381 |
|
|
in_q0 => in_h192,
|
| 4382 |
|
|
out_q0 => from_first_row(23 downto 16)
|
| 4383 |
|
|
);
|
| 4384 |
|
|
|
| 4385 |
|
|
first_q0_2: q0
|
| 4386 |
|
|
port map (
|
| 4387 |
|
|
in_q0 => in_h192,
|
| 4388 |
|
|
out_q0 => from_first_row(31 downto 24)
|
| 4389 |
|
|
);
|
| 4390 |
|
|
|
| 4391 |
|
|
-- we perform the XOR of the results of the first row
|
| 4392 |
|
|
-- with first M of h (Mfirst_h128)
|
| 4393 |
|
|
to_second_row <= from_first_row XOR Mfirst_h192;
|
| 4394 |
|
|
|
| 4395 |
|
|
-- second row of q
|
| 4396 |
|
|
second_q0_1: q0
|
| 4397 |
|
|
port map (
|
| 4398 |
|
|
in_q0 => to_second_row(7 downto 0),
|
| 4399 |
|
|
out_q0 => from_second_row(7 downto 0)
|
| 4400 |
|
|
);
|
| 4401 |
|
|
second_q1_1: q1
|
| 4402 |
|
|
port map (
|
| 4403 |
|
|
in_q1 => to_second_row(15 downto 8),
|
| 4404 |
|
|
out_q1 => from_second_row(15 downto 8)
|
| 4405 |
|
|
);
|
| 4406 |
|
|
second_q0_2: q0
|
| 4407 |
|
|
port map (
|
| 4408 |
|
|
in_q0 => to_second_row(23 downto 16),
|
| 4409 |
|
|
out_q0 => from_second_row(23 downto 16)
|
| 4410 |
|
|
);
|
| 4411 |
|
|
second_q1_2: q1
|
| 4412 |
|
|
port map (
|
| 4413 |
|
|
in_q1 => to_second_row(31 downto 24),
|
| 4414 |
|
|
out_q1 => from_second_row(31 downto 24)
|
| 4415 |
|
|
);
|
| 4416 |
|
|
|
| 4417 |
|
|
-- we perform the XOR of the results of the second row
|
| 4418 |
|
|
-- with second M of h (Msecond_h128)
|
| 4419 |
|
|
to_third_row <= from_second_row XOR Msecond_h192;
|
| 4420 |
|
|
|
| 4421 |
|
|
-- third row of q
|
| 4422 |
|
|
third_q0_1: q0
|
| 4423 |
|
|
port map (
|
| 4424 |
|
|
in_q0 => to_third_row(7 downto 0),
|
| 4425 |
|
|
out_q0 => from_third_row(7 downto 0)
|
| 4426 |
|
|
);
|
| 4427 |
|
|
third_q0_2: q0
|
| 4428 |
|
|
port map (
|
| 4429 |
|
|
in_q0 => to_third_row(15 downto 8),
|
| 4430 |
|
|
out_q0 => from_third_row(15 downto 8)
|
| 4431 |
|
|
);
|
| 4432 |
|
|
third_q1_1: q1
|
| 4433 |
|
|
port map (
|
| 4434 |
|
|
in_q1 => to_third_row(23 downto 16),
|
| 4435 |
|
|
out_q1 => from_third_row(23 downto 16)
|
| 4436 |
|
|
);
|
| 4437 |
|
|
third_q1_2: q1
|
| 4438 |
|
|
port map (
|
| 4439 |
|
|
in_q1 => to_third_row(31 downto 24),
|
| 4440 |
|
|
out_q1 => from_third_row(31 downto 24)
|
| 4441 |
|
|
);
|
| 4442 |
|
|
|
| 4443 |
|
|
-- we perform the third XOR
|
| 4444 |
|
|
to_fourth_row <= from_third_row XOR Mthird_h192;
|
| 4445 |
|
|
|
| 4446 |
|
|
-- the fourth row of q
|
| 4447 |
|
|
fourth_q1_1: q1
|
| 4448 |
|
|
port map (
|
| 4449 |
|
|
in_q1 => to_fourth_row(7 downto 0),
|
| 4450 |
|
|
out_q1 => to_mds(7 downto 0)
|
| 4451 |
|
|
);
|
| 4452 |
|
|
fourth_q0_1: q0
|
| 4453 |
|
|
port map (
|
| 4454 |
|
|
in_q0 => to_fourth_row(15 downto 8),
|
| 4455 |
|
|
out_q0 => to_mds(15 downto 8)
|
| 4456 |
|
|
);
|
| 4457 |
|
|
fourth_q1_2: q1
|
| 4458 |
|
|
port map (
|
| 4459 |
|
|
in_q1 => to_fourth_row(23 downto 16),
|
| 4460 |
|
|
out_q1 => to_mds(23 downto 16)
|
| 4461 |
|
|
);
|
| 4462 |
|
|
fourth_q0_2: q0
|
| 4463 |
|
|
port map (
|
| 4464 |
|
|
in_q0 => to_fourth_row(31 downto 24),
|
| 4465 |
|
|
out_q0 => to_mds(31 downto 24)
|
| 4466 |
|
|
);
|
| 4467 |
|
|
|
| 4468 |
|
|
-- mds table
|
| 4469 |
|
|
mds_table: mds
|
| 4470 |
|
|
port map (
|
| 4471 |
|
|
y0 => to_mds(7 downto 0),
|
| 4472 |
|
|
y1 => to_mds(15 downto 8),
|
| 4473 |
|
|
y2 => to_mds(23 downto 16),
|
| 4474 |
|
|
y3 => to_mds(31 downto 24),
|
| 4475 |
|
|
z0 => out_h192(7 downto 0),
|
| 4476 |
|
|
z1 => out_h192(15 downto 8),
|
| 4477 |
|
|
z2 => out_h192(23 downto 16),
|
| 4478 |
|
|
z3 => out_h192(31 downto 24)
|
| 4479 |
|
|
);
|
| 4480 |
|
|
|
| 4481 |
|
|
end h192_arch;
|
| 4482 |
|
|
|
| 4483 |
|
|
|
| 4484 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4485 |
|
|
-- --
|
| 4486 |
|
|
-- new component --
|
| 4487 |
|
|
-- --
|
| 4488 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4489 |
|
|
|
| 4490 |
|
|
|
| 4491 |
|
|
--
|
| 4492 |
|
|
-- g function for 192 bits key
|
| 4493 |
|
|
--
|
| 4494 |
|
|
|
| 4495 |
|
|
library ieee;
|
| 4496 |
|
|
use ieee.std_logic_1164.all;
|
| 4497 |
|
|
|
| 4498 |
|
|
entity g_192 is
|
| 4499 |
|
|
port (
|
| 4500 |
|
|
in_g192,
|
| 4501 |
|
|
in_S0_g192,
|
| 4502 |
|
|
in_S1_g192,
|
| 4503 |
|
|
in_S2_g192 : in std_logic_vector(31 downto 0);
|
| 4504 |
|
|
out_g192 : out std_logic_vector(31 downto 0)
|
| 4505 |
|
|
);
|
| 4506 |
|
|
end g_192;
|
| 4507 |
|
|
|
| 4508 |
|
|
architecture g192_arch of g_192 is
|
| 4509 |
|
|
|
| 4510 |
|
|
-- we declare the internal signals
|
| 4511 |
|
|
signal from_first_row,
|
| 4512 |
|
|
to_second_row,
|
| 4513 |
|
|
from_second_row,
|
| 4514 |
|
|
to_third_row,
|
| 4515 |
|
|
from_third_row,
|
| 4516 |
|
|
to_fourth_row,
|
| 4517 |
|
|
to_mds : std_logic_vector(31 downto 0);
|
| 4518 |
|
|
|
| 4519 |
|
|
component q0
|
| 4520 |
|
|
port (
|
| 4521 |
|
|
in_q0 : in std_logic_vector(7 downto 0);
|
| 4522 |
|
|
out_q0 : out std_logic_vector(7 downto 0)
|
| 4523 |
|
|
);
|
| 4524 |
|
|
end component;
|
| 4525 |
|
|
|
| 4526 |
|
|
component q1
|
| 4527 |
|
|
port (
|
| 4528 |
|
|
in_q1 : in std_logic_vector(7 downto 0);
|
| 4529 |
|
|
out_q1 : out std_logic_vector(7 downto 0)
|
| 4530 |
|
|
);
|
| 4531 |
|
|
end component;
|
| 4532 |
|
|
|
| 4533 |
|
|
component mds
|
| 4534 |
|
|
port (
|
| 4535 |
|
|
y0,
|
| 4536 |
|
|
y1,
|
| 4537 |
|
|
y2,
|
| 4538 |
|
|
y3 : in std_logic_vector(7 downto 0);
|
| 4539 |
|
|
z0,
|
| 4540 |
|
|
z1,
|
| 4541 |
|
|
z2,
|
| 4542 |
|
|
z3 : out std_logic_vector(7 downto 0)
|
| 4543 |
|
|
);
|
| 4544 |
|
|
end component;
|
| 4545 |
|
|
|
| 4546 |
|
|
-- begin architecture description
|
| 4547 |
|
|
begin
|
| 4548 |
|
|
|
| 4549 |
|
|
-- first row of q
|
| 4550 |
|
|
first_q1_1: q1
|
| 4551 |
|
|
port map (
|
| 4552 |
|
|
in_q1 => in_g192(7 downto 0),
|
| 4553 |
|
|
out_q1 => from_first_row(7 downto 0)
|
| 4554 |
|
|
);
|
| 4555 |
|
|
first_q1_2: q1
|
| 4556 |
|
|
port map (
|
| 4557 |
|
|
in_q1 => in_g192(15 downto 8),
|
| 4558 |
|
|
out_q1 => from_first_row(15 downto 8)
|
| 4559 |
|
|
);
|
| 4560 |
|
|
first_q0_1: q0
|
| 4561 |
|
|
port map (
|
| 4562 |
|
|
in_q0 => in_g192(23 downto 16),
|
| 4563 |
|
|
out_q0 => from_first_row(23 downto 16)
|
| 4564 |
|
|
);
|
| 4565 |
|
|
first_q0_2: q0
|
| 4566 |
|
|
port map (
|
| 4567 |
|
|
in_q0 => in_g192(31 downto 24),
|
| 4568 |
|
|
out_q0 => from_first_row(31 downto 24)
|
| 4569 |
|
|
);
|
| 4570 |
|
|
|
| 4571 |
|
|
-- we XOR the result of the first row
|
| 4572 |
|
|
-- with the S0
|
| 4573 |
|
|
to_second_row <= from_first_row XOR in_S0_g192;
|
| 4574 |
|
|
|
| 4575 |
|
|
-- second row of q
|
| 4576 |
|
|
second_q0_1: q0
|
| 4577 |
|
|
port map (
|
| 4578 |
|
|
in_q0 => to_second_row(7 downto 0),
|
| 4579 |
|
|
out_q0 => from_second_row(7 downto 0)
|
| 4580 |
|
|
);
|
| 4581 |
|
|
second_q1_1: q1
|
| 4582 |
|
|
port map (
|
| 4583 |
|
|
in_q1 => to_second_row(15 downto 8),
|
| 4584 |
|
|
out_q1 => from_second_row(15 downto 8)
|
| 4585 |
|
|
);
|
| 4586 |
|
|
second_q0_2: q0
|
| 4587 |
|
|
port map (
|
| 4588 |
|
|
in_q0 => to_second_row(23 downto 16),
|
| 4589 |
|
|
out_q0 => from_second_row(23 downto 16)
|
| 4590 |
|
|
);
|
| 4591 |
|
|
second_q1_2: q1
|
| 4592 |
|
|
port map (
|
| 4593 |
|
|
in_q1 => to_second_row(31 downto 24),
|
| 4594 |
|
|
out_q1 => from_second_row(31 downto 24)
|
| 4595 |
|
|
);
|
| 4596 |
|
|
|
| 4597 |
|
|
-- we perform the XOR
|
| 4598 |
|
|
to_third_row <= from_second_row XOR in_S1_g192;
|
| 4599 |
|
|
|
| 4600 |
|
|
-- third row of q
|
| 4601 |
|
|
third_q0_1: q0
|
| 4602 |
|
|
port map (
|
| 4603 |
|
|
in_q0 => to_third_row(7 downto 0),
|
| 4604 |
|
|
out_q0 => from_third_row(7 downto 0)
|
| 4605 |
|
|
);
|
| 4606 |
|
|
third_q0_2: q0
|
| 4607 |
|
|
port map (
|
| 4608 |
|
|
in_q0 => to_third_row(15 downto 8),
|
| 4609 |
|
|
out_q0 => from_third_row(15 downto 8)
|
| 4610 |
|
|
);
|
| 4611 |
|
|
third_q1_1: q1
|
| 4612 |
|
|
port map (
|
| 4613 |
|
|
in_q1 => to_third_row(23 downto 16),
|
| 4614 |
|
|
out_q1 => from_third_row(23 downto 16)
|
| 4615 |
|
|
);
|
| 4616 |
|
|
third_q1_2: q1
|
| 4617 |
|
|
port map (
|
| 4618 |
|
|
in_q1 => to_third_row(31 downto 24),
|
| 4619 |
|
|
out_q1 => from_third_row(31 downto 24)
|
| 4620 |
|
|
);
|
| 4621 |
|
|
|
| 4622 |
|
|
-- we perform the XOR
|
| 4623 |
|
|
to_fourth_row <= from_third_row XOR in_S2_g192;
|
| 4624 |
|
|
|
| 4625 |
|
|
-- fourth row of q
|
| 4626 |
|
|
fourth_q1_1: q1
|
| 4627 |
|
|
port map (
|
| 4628 |
|
|
in_q1=> to_fourth_row(7 downto 0),
|
| 4629 |
|
|
out_q1 => to_mds(7 downto 0)
|
| 4630 |
|
|
);
|
| 4631 |
|
|
fourth_q0_1: q0
|
| 4632 |
|
|
port map (
|
| 4633 |
|
|
in_q0 => to_fourth_row(15 downto 8),
|
| 4634 |
|
|
out_q0 => to_mds(15 downto 8)
|
| 4635 |
|
|
);
|
| 4636 |
|
|
fourth_q1_2: q1
|
| 4637 |
|
|
port map (
|
| 4638 |
|
|
in_q1 => to_fourth_row(23 downto 16),
|
| 4639 |
|
|
out_q1 => to_mds(23 downto 16)
|
| 4640 |
|
|
);
|
| 4641 |
|
|
fourth_q0_2: q0
|
| 4642 |
|
|
port map (
|
| 4643 |
|
|
in_q0 => to_fourth_row(31 downto 24),
|
| 4644 |
|
|
out_q0 => to_mds(31 downto 24)
|
| 4645 |
|
|
);
|
| 4646 |
|
|
|
| 4647 |
|
|
-- mds table
|
| 4648 |
|
|
mds_table: mds
|
| 4649 |
|
|
port map (
|
| 4650 |
|
|
y0 => to_mds(7 downto 0),
|
| 4651 |
|
|
y1 => to_mds(15 downto 8),
|
| 4652 |
|
|
y2 => to_mds(23 downto 16),
|
| 4653 |
|
|
y3 => to_mds(31 downto 24),
|
| 4654 |
|
|
z0 => out_g192(7 downto 0),
|
| 4655 |
|
|
z1 => out_g192(15 downto 8),
|
| 4656 |
|
|
z2 => out_g192(23 downto 16),
|
| 4657 |
|
|
z3 => out_g192(31 downto 24)
|
| 4658 |
|
|
);
|
| 4659 |
|
|
|
| 4660 |
|
|
end g192_arch;
|
| 4661 |
|
|
|
| 4662 |
|
|
|
| 4663 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4664 |
|
|
-- --
|
| 4665 |
|
|
-- new component --
|
| 4666 |
|
|
-- --
|
| 4667 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4668 |
|
|
|
| 4669 |
|
|
|
| 4670 |
|
|
--
|
| 4671 |
|
|
-- f function with 192 bits key
|
| 4672 |
|
|
--
|
| 4673 |
|
|
|
| 4674 |
|
|
library ieee;
|
| 4675 |
|
|
use ieee.std_logic_1164.all;
|
| 4676 |
|
|
|
| 4677 |
|
|
entity f_192 is
|
| 4678 |
|
|
port (
|
| 4679 |
|
|
up_in_f192,
|
| 4680 |
|
|
low_in_f192,
|
| 4681 |
|
|
S0_in_f192,
|
| 4682 |
|
|
S1_in_f192,
|
| 4683 |
|
|
S2_in_f192,
|
| 4684 |
|
|
up_key_f192,
|
| 4685 |
|
|
low_key_f192 : in std_logic_vector(31 downto 0);
|
| 4686 |
|
|
up_out_f192,
|
| 4687 |
|
|
low_out_f192 : out std_logic_vector(31 downto 0)
|
| 4688 |
|
|
);
|
| 4689 |
|
|
end f_192;
|
| 4690 |
|
|
|
| 4691 |
|
|
architecture f192_arch of f_192 is
|
| 4692 |
|
|
|
| 4693 |
|
|
-- we declare the internal signals
|
| 4694 |
|
|
signal from_shift_8,
|
| 4695 |
|
|
to_up_pht,
|
| 4696 |
|
|
to_low_pht,
|
| 4697 |
|
|
to_up_key,
|
| 4698 |
|
|
to_low_key,
|
| 4699 |
|
|
intermediate_carry1,
|
| 4700 |
|
|
intermediate_carry2 : std_logic_vector(31 downto 0);
|
| 4701 |
|
|
signal zero : std_logic;
|
| 4702 |
|
|
|
| 4703 |
|
|
|
| 4704 |
|
|
component g_192
|
| 4705 |
|
|
port (
|
| 4706 |
|
|
in_g192,
|
| 4707 |
|
|
in_S0_g192,
|
| 4708 |
|
|
in_S1_g192,
|
| 4709 |
|
|
in_S2_g192 : in std_logic_vector(31 downto 0);
|
| 4710 |
|
|
out_g192 : out std_logic_vector(31 downto 0)
|
| 4711 |
|
|
);
|
| 4712 |
|
|
end component;
|
| 4713 |
|
|
|
| 4714 |
|
|
component pht
|
| 4715 |
|
|
port (
|
| 4716 |
|
|
up_in_pht,
|
| 4717 |
|
|
down_in_pht : in std_logic_vector(31 downto 0);
|
| 4718 |
|
|
up_out_pht,
|
| 4719 |
|
|
down_out_pht : out std_logic_vector(31 downto 0)
|
| 4720 |
|
|
);
|
| 4721 |
|
|
end component;
|
| 4722 |
|
|
|
| 4723 |
|
|
component adder
|
| 4724 |
|
|
port (
|
| 4725 |
|
|
in1_adder,
|
| 4726 |
|
|
in2_adder,
|
| 4727 |
|
|
in_carry_adder : in std_logic;
|
| 4728 |
|
|
out_adder,
|
| 4729 |
|
|
out_carry_adder : out std_logic
|
| 4730 |
|
|
);
|
| 4731 |
|
|
end component;
|
| 4732 |
|
|
|
| 4733 |
|
|
-- begin architecture description
|
| 4734 |
|
|
begin
|
| 4735 |
|
|
|
| 4736 |
|
|
-- we initialize zero
|
| 4737 |
|
|
zero <= '0';
|
| 4738 |
|
|
|
| 4739 |
|
|
-- upper g_192
|
| 4740 |
|
|
upper_g192: g_192
|
| 4741 |
|
|
port map (
|
| 4742 |
|
|
in_g192 => up_in_f192,
|
| 4743 |
|
|
in_S0_g192 => S0_in_f192,
|
| 4744 |
|
|
in_S1_g192 => S1_in_f192,
|
| 4745 |
|
|
in_S2_g192 => S2_in_f192,
|
| 4746 |
|
|
out_g192 => to_up_pht
|
| 4747 |
|
|
);
|
| 4748 |
|
|
|
| 4749 |
|
|
-- left rotation by 8
|
| 4750 |
|
|
from_shift_8(31 downto 8) <= low_in_f192(23 downto 0);
|
| 4751 |
|
|
from_shift_8(7 downto 0) <= low_in_f192(31 downto 24);
|
| 4752 |
|
|
|
| 4753 |
|
|
-- lower g192
|
| 4754 |
|
|
lower_g192: g_192
|
| 4755 |
|
|
port map (
|
| 4756 |
|
|
in_g192 => from_shift_8,
|
| 4757 |
|
|
in_S0_g192 => S0_in_f192,
|
| 4758 |
|
|
in_S1_g192 => S1_in_f192,
|
| 4759 |
|
|
in_S2_g192 => S2_in_f192,
|
| 4760 |
|
|
out_g192 => to_low_pht
|
| 4761 |
|
|
);
|
| 4762 |
|
|
|
| 4763 |
|
|
-- pht
|
| 4764 |
|
|
pht_transform: pht
|
| 4765 |
|
|
port map (
|
| 4766 |
|
|
up_in_pht => to_up_pht,
|
| 4767 |
|
|
down_in_pht => to_low_pht,
|
| 4768 |
|
|
up_out_pht => to_up_key,
|
| 4769 |
|
|
down_out_pht => to_low_key
|
| 4770 |
|
|
);
|
| 4771 |
|
|
|
| 4772 |
|
|
-- upper adder of 32 bits
|
| 4773 |
|
|
up_adder: for i in 0 to 31 generate
|
| 4774 |
|
|
first: if (i=0) generate
|
| 4775 |
|
|
the_adder: adder
|
| 4776 |
|
|
port map (
|
| 4777 |
|
|
in1_adder => to_up_key(0),
|
| 4778 |
|
|
in2_adder => up_key_f192(0),
|
| 4779 |
|
|
in_carry_adder => zero,
|
| 4780 |
|
|
out_adder => up_out_f192(0),
|
| 4781 |
|
|
out_carry_adder => intermediate_carry1(0)
|
| 4782 |
|
|
);
|
| 4783 |
|
|
end generate first;
|
| 4784 |
|
|
the_rest: if (i>0) generate
|
| 4785 |
|
|
the_adders: adder
|
| 4786 |
|
|
port map (
|
| 4787 |
|
|
in1_adder => to_up_key(i),
|
| 4788 |
|
|
in2_adder => up_key_f192(i),
|
| 4789 |
|
|
in_carry_adder => intermediate_carry1(i-1),
|
| 4790 |
|
|
out_adder => up_out_f192(i),
|
| 4791 |
|
|
out_carry_adder => intermediate_carry1(i)
|
| 4792 |
|
|
);
|
| 4793 |
|
|
end generate the_rest;
|
| 4794 |
|
|
end generate up_adder;
|
| 4795 |
|
|
|
| 4796 |
|
|
-- lower adder of 32 bits
|
| 4797 |
|
|
low_adder: for i in 0 to 31 generate
|
| 4798 |
|
|
first1: if (i=0) generate
|
| 4799 |
|
|
the_adder1:adder
|
| 4800 |
|
|
port map (
|
| 4801 |
|
|
in1_adder => to_low_key(0),
|
| 4802 |
|
|
in2_adder => low_key_f192(0),
|
| 4803 |
|
|
in_carry_adder => zero,
|
| 4804 |
|
|
out_adder => low_out_f192(0),
|
| 4805 |
|
|
out_carry_adder => intermediate_carry2(0)
|
| 4806 |
|
|
);
|
| 4807 |
|
|
end generate first1;
|
| 4808 |
|
|
the_rest1: if (i>0) generate
|
| 4809 |
|
|
the_adders1: adder
|
| 4810 |
|
|
port map (
|
| 4811 |
|
|
in1_adder => to_low_key(i),
|
| 4812 |
|
|
in2_adder => low_key_f192(i),
|
| 4813 |
|
|
in_carry_adder => intermediate_carry2(i-1),
|
| 4814 |
|
|
out_adder => low_out_f192(i),
|
| 4815 |
|
|
out_carry_adder => intermediate_carry2(i)
|
| 4816 |
|
|
);
|
| 4817 |
|
|
end generate the_rest1;
|
| 4818 |
|
|
end generate low_adder;
|
| 4819 |
|
|
|
| 4820 |
|
|
end f192_arch;
|
| 4821 |
|
|
|
| 4822 |
|
|
|
| 4823 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4824 |
|
|
-- --
|
| 4825 |
|
|
-- new component --
|
| 4826 |
|
|
-- --
|
| 4827 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4828 |
|
|
|
| 4829 |
|
|
--
|
| 4830 |
|
|
-- twofish key scheduler for 192 bits key input
|
| 4831 |
|
|
--
|
| 4832 |
|
|
|
| 4833 |
|
|
library ieee;
|
| 4834 |
|
|
use ieee.std_logic_1164.all;
|
| 4835 |
|
|
|
| 4836 |
|
|
entity twofish_keysched192 is
|
| 4837 |
|
|
port (
|
| 4838 |
|
|
odd_in_tk192,
|
| 4839 |
|
|
even_in_tk192 : in std_logic_vector(7 downto 0);
|
| 4840 |
|
|
in_key_tk192 : in std_logic_vector(191 downto 0);
|
| 4841 |
|
|
out_key_up_tk192,
|
| 4842 |
|
|
out_key_down_tk192 : out std_logic_vector(31 downto 0)
|
| 4843 |
|
|
);
|
| 4844 |
|
|
end twofish_keysched192;
|
| 4845 |
|
|
|
| 4846 |
|
|
architecture twofish_keysched192_arch of twofish_keysched192 is
|
| 4847 |
|
|
|
| 4848 |
|
|
-- we declare internal signals
|
| 4849 |
|
|
signal to_up_pht,
|
| 4850 |
|
|
to_shift_8,
|
| 4851 |
|
|
from_shift_8,
|
| 4852 |
|
|
to_shift_9,
|
| 4853 |
|
|
M0, M1, M2, M3, M4, M5 : std_logic_vector(31 downto 0);
|
| 4854 |
|
|
|
| 4855 |
|
|
signal byte0, byte1, byte2, byte3,
|
| 4856 |
|
|
byte4, byte5, byte6, byte7,
|
| 4857 |
|
|
byte8, byte9, byte10, byte11,
|
| 4858 |
|
|
byte12, byte13, byte14, byte15,
|
| 4859 |
|
|
byte16, byte17, byte18, byte19,
|
| 4860 |
|
|
byte20, byte21, byte22, byte23 : std_logic_vector(7 downto 0);
|
| 4861 |
|
|
|
| 4862 |
|
|
-- we declare the components to be used
|
| 4863 |
|
|
component pht
|
| 4864 |
|
|
port (
|
| 4865 |
|
|
up_in_pht,
|
| 4866 |
|
|
down_in_pht : in std_logic_vector(31 downto 0);
|
| 4867 |
|
|
up_out_pht,
|
| 4868 |
|
|
down_out_pht : out std_logic_vector(31 downto 0)
|
| 4869 |
|
|
);
|
| 4870 |
|
|
end component;
|
| 4871 |
|
|
|
| 4872 |
|
|
component h_192
|
| 4873 |
|
|
port (
|
| 4874 |
|
|
in_h192 : in std_logic_vector(7 downto 0);
|
| 4875 |
|
|
Mfirst_h192,
|
| 4876 |
|
|
Msecond_h192,
|
| 4877 |
|
|
Mthird_h192 : in std_logic_vector(31 downto 0);
|
| 4878 |
|
|
out_h192 : out std_logic_vector(31 downto 0)
|
| 4879 |
|
|
);
|
| 4880 |
|
|
end component;
|
| 4881 |
|
|
|
| 4882 |
|
|
-- begin architecture description
|
| 4883 |
|
|
begin
|
| 4884 |
|
|
|
| 4885 |
|
|
-- we assign the input signal to the respective
|
| 4886 |
|
|
-- bytes as is described in the prototype
|
| 4887 |
|
|
byte23 <= in_key_tk192(7 downto 0);
|
| 4888 |
|
|
byte22 <= in_key_tk192(15 downto 8);
|
| 4889 |
|
|
byte21 <= in_key_tk192(23 downto 16);
|
| 4890 |
|
|
byte20 <= in_key_tk192(31 downto 24);
|
| 4891 |
|
|
byte19 <= in_key_tk192(39 downto 32);
|
| 4892 |
|
|
byte18 <= in_key_tk192(47 downto 40);
|
| 4893 |
|
|
byte17 <= in_key_tk192(55 downto 48);
|
| 4894 |
|
|
byte16 <= in_key_tk192(63 downto 56);
|
| 4895 |
|
|
byte15 <= in_key_tk192(71 downto 64);
|
| 4896 |
|
|
byte14 <= in_key_tk192(79 downto 72);
|
| 4897 |
|
|
byte13 <= in_key_tk192(87 downto 80);
|
| 4898 |
|
|
byte12 <= in_key_tk192(95 downto 88);
|
| 4899 |
|
|
byte11 <= in_key_tk192(103 downto 96);
|
| 4900 |
|
|
byte10 <= in_key_tk192(111 downto 104);
|
| 4901 |
|
|
byte9 <= in_key_tk192(119 downto 112);
|
| 4902 |
|
|
byte8 <= in_key_tk192(127 downto 120);
|
| 4903 |
|
|
byte7 <= in_key_tk192(135 downto 128);
|
| 4904 |
|
|
byte6 <= in_key_tk192(143 downto 136);
|
| 4905 |
|
|
byte5 <= in_key_tk192(151 downto 144);
|
| 4906 |
|
|
byte4 <= in_key_tk192(159 downto 152);
|
| 4907 |
|
|
byte3 <= in_key_tk192(167 downto 160);
|
| 4908 |
|
|
byte2 <= in_key_tk192(175 downto 168);
|
| 4909 |
|
|
byte1 <= in_key_tk192(183 downto 176);
|
| 4910 |
|
|
byte0 <= in_key_tk192(191 downto 184);
|
| 4911 |
|
|
|
| 4912 |
|
|
-- we form the M{0..5}
|
| 4913 |
|
|
M0 <= byte3 & byte2 & byte1 & byte0;
|
| 4914 |
|
|
M1 <= byte7 & byte6 & byte5 & byte4;
|
| 4915 |
|
|
M2 <= byte11 & byte10 & byte9 & byte8;
|
| 4916 |
|
|
M3 <= byte15 & byte14 & byte13 & byte12;
|
| 4917 |
|
|
M4 <= byte19 & byte18 & byte17 & byte16;
|
| 4918 |
|
|
M5 <= byte23 & byte22 & byte21 & byte20;
|
| 4919 |
|
|
|
| 4920 |
|
|
-- upper h
|
| 4921 |
|
|
upper_h: h_192
|
| 4922 |
|
|
port map (
|
| 4923 |
|
|
in_h192 => even_in_tk192,
|
| 4924 |
|
|
Mfirst_h192 => M4,
|
| 4925 |
|
|
Msecond_h192 => M2,
|
| 4926 |
|
|
Mthird_h192 => M0,
|
| 4927 |
|
|
out_h192 => to_up_pht
|
| 4928 |
|
|
);
|
| 4929 |
|
|
|
| 4930 |
|
|
-- lower h
|
| 4931 |
|
|
lower_h: h_192
|
| 4932 |
|
|
port map (
|
| 4933 |
|
|
in_h192 => odd_in_tk192,
|
| 4934 |
|
|
Mfirst_h192 => M5,
|
| 4935 |
|
|
Msecond_h192 => M3,
|
| 4936 |
|
|
Mthird_h192 => M1,
|
| 4937 |
|
|
out_h192 => to_shift_8
|
| 4938 |
|
|
);
|
| 4939 |
|
|
|
| 4940 |
|
|
-- left rotate by 8
|
| 4941 |
|
|
from_shift_8(31 downto 8) <= to_shift_8(23 downto 0);
|
| 4942 |
|
|
from_shift_8(7 downto 0) <= to_shift_8(31 downto 24);
|
| 4943 |
|
|
|
| 4944 |
|
|
-- pht transformation
|
| 4945 |
|
|
pht_transform: pht
|
| 4946 |
|
|
port map (
|
| 4947 |
|
|
up_in_pht => to_up_pht,
|
| 4948 |
|
|
down_in_pht => from_shift_8,
|
| 4949 |
|
|
up_out_pht => out_key_up_tk192,
|
| 4950 |
|
|
down_out_pht => to_shift_9
|
| 4951 |
|
|
);
|
| 4952 |
|
|
|
| 4953 |
|
|
-- left rotate by 9
|
| 4954 |
|
|
out_key_down_tk192(31 downto 9) <= to_shift_9(22 downto 0);
|
| 4955 |
|
|
out_key_down_tk192(8 downto 0) <= to_shift_9(31 downto 23);
|
| 4956 |
|
|
|
| 4957 |
|
|
end twofish_keysched192_arch;
|
| 4958 |
|
|
|
| 4959 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4960 |
|
|
-- --
|
| 4961 |
|
|
-- new component --
|
| 4962 |
|
|
-- --
|
| 4963 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 4964 |
|
|
|
| 4965 |
|
|
--
|
| 4966 |
|
|
-- twofish S key component for 192 bits key
|
| 4967 |
|
|
--
|
| 4968 |
|
|
|
| 4969 |
|
|
library ieee;
|
| 4970 |
|
|
use ieee.std_logic_1164.all;
|
| 4971 |
|
|
|
| 4972 |
|
|
entity twofish_S192 is
|
| 4973 |
|
|
port (
|
| 4974 |
|
|
in_key_ts192 : in std_logic_vector(191 downto 0);
|
| 4975 |
|
|
out_Sfirst_ts192,
|
| 4976 |
|
|
out_Ssecond_ts192,
|
| 4977 |
|
|
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
|
| 4978 |
|
|
);
|
| 4979 |
|
|
end twofish_S192;
|
| 4980 |
|
|
|
| 4981 |
|
|
architecture twofish_S192_arch of twofish_S192 is
|
| 4982 |
|
|
|
| 4983 |
|
|
-- we declare the components to be used
|
| 4984 |
|
|
component reed_solomon192
|
| 4985 |
|
|
port (
|
| 4986 |
|
|
in_rs192 : in std_logic_vector(191 downto 0);
|
| 4987 |
|
|
out_Sfirst_rs192,
|
| 4988 |
|
|
out_Ssecond_rs192,
|
| 4989 |
|
|
out_Sthird_rs192 : out std_logic_vector(31 downto 0)
|
| 4990 |
|
|
);
|
| 4991 |
|
|
end component;
|
| 4992 |
|
|
|
| 4993 |
|
|
signal twofish_key : std_logic_vector(191 downto 0);
|
| 4994 |
|
|
signal byte15, byte14, byte13, byte12, byte11, byte10,
|
| 4995 |
|
|
byte9, byte8, byte7, byte6, byte5, byte4,
|
| 4996 |
|
|
byte3, byte2, byte1, byte0,
|
| 4997 |
|
|
byte16, byte17, byte18, byte19,
|
| 4998 |
|
|
byte20, byte21, byte22, byte23 : std_logic_vector(7 downto 0);
|
| 4999 |
|
|
|
| 5000 |
|
|
-- begin architecture description
|
| 5001 |
|
|
begin
|
| 5002 |
|
|
|
| 5003 |
|
|
-- splitting the input
|
| 5004 |
|
|
byte23 <= in_key_ts192(7 downto 0);
|
| 5005 |
|
|
byte22 <= in_key_ts192(15 downto 8);
|
| 5006 |
|
|
byte21 <= in_key_ts192(23 downto 16);
|
| 5007 |
|
|
byte20 <= in_key_ts192(31 downto 24);
|
| 5008 |
|
|
byte19 <= in_key_ts192(39 downto 32);
|
| 5009 |
|
|
byte18 <= in_key_ts192(47 downto 40);
|
| 5010 |
|
|
byte17 <= in_key_ts192(55 downto 48);
|
| 5011 |
|
|
byte16 <= in_key_ts192(63 downto 56);
|
| 5012 |
|
|
byte15 <= in_key_ts192(71 downto 64);
|
| 5013 |
|
|
byte14 <= in_key_ts192(79 downto 72);
|
| 5014 |
|
|
byte13 <= in_key_ts192(87 downto 80);
|
| 5015 |
|
|
byte12 <= in_key_ts192(95 downto 88);
|
| 5016 |
|
|
byte11 <= in_key_ts192(103 downto 96);
|
| 5017 |
|
|
byte10 <= in_key_ts192(111 downto 104);
|
| 5018 |
|
|
byte9 <= in_key_ts192(119 downto 112);
|
| 5019 |
|
|
byte8 <= in_key_ts192(127 downto 120);
|
| 5020 |
|
|
byte7 <= in_key_ts192(135 downto 128);
|
| 5021 |
|
|
byte6 <= in_key_ts192(143 downto 136);
|
| 5022 |
|
|
byte5 <= in_key_ts192(151 downto 144);
|
| 5023 |
|
|
byte4 <= in_key_ts192(159 downto 152);
|
| 5024 |
|
|
byte3 <= in_key_ts192(167 downto 160);
|
| 5025 |
|
|
byte2 <= in_key_ts192(175 downto 168);
|
| 5026 |
|
|
byte1 <= in_key_ts192(183 downto 176);
|
| 5027 |
|
|
byte0 <= in_key_ts192(191 downto 184);
|
| 5028 |
|
|
|
| 5029 |
|
|
-- forming the key
|
| 5030 |
|
|
twofish_key <= byte23 & byte22 & byte21 & byte20 & byte19 & byte18 & byte17 & byte16 &
|
| 5031 |
|
|
byte15 & byte14 & byte13 & byte12 & byte11 & byte10 & byte9 & byte8 & byte7 &
|
| 5032 |
|
|
byte6 & byte5 & byte4 & byte3 & byte2 & byte1 & byte0;
|
| 5033 |
|
|
|
| 5034 |
|
|
|
| 5035 |
|
|
-- the keys S0,1,2
|
| 5036 |
|
|
produce_S0_S1_S2: reed_solomon192
|
| 5037 |
|
|
port map (
|
| 5038 |
|
|
in_rs192 => twofish_key,
|
| 5039 |
|
|
out_Sfirst_rs192 => out_Sfirst_ts192,
|
| 5040 |
|
|
out_Ssecond_rs192 => out_Ssecond_ts192,
|
| 5041 |
|
|
out_Sthird_rs192 => out_Sthird_ts192
|
| 5042 |
|
|
);
|
| 5043 |
|
|
|
| 5044 |
|
|
|
| 5045 |
|
|
end twofish_S192_arch;
|
| 5046 |
|
|
|
| 5047 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 5048 |
|
|
-- --
|
| 5049 |
|
|
-- new component --
|
| 5050 |
|
|
-- --
|
| 5051 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 5052 |
|
|
|
| 5053 |
|
|
--
|
| 5054 |
|
|
-- twofish whitening key scheduler for 192 bits key input
|
| 5055 |
|
|
--
|
| 5056 |
|
|
|
| 5057 |
|
|
library ieee;
|
| 5058 |
|
|
use ieee.std_logic_1164.all;
|
| 5059 |
|
|
|
| 5060 |
|
|
entity twofish_whit_keysched192 is
|
| 5061 |
|
|
port (
|
| 5062 |
|
|
in_key_twk192 : in std_logic_vector(191 downto 0);
|
| 5063 |
|
|
out_K0_twk192,
|
| 5064 |
|
|
out_K1_twk192,
|
| 5065 |
|
|
out_K2_twk192,
|
| 5066 |
|
|
out_K3_twk192,
|
| 5067 |
|
|
out_K4_twk192,
|
| 5068 |
|
|
out_K5_twk192,
|
| 5069 |
|
|
out_K6_twk192,
|
| 5070 |
|
|
out_K7_twk192 : out std_logic_vector(31 downto 0)
|
| 5071 |
|
|
);
|
| 5072 |
|
|
end twofish_whit_keysched192;
|
| 5073 |
|
|
|
| 5074 |
|
|
architecture twofish_whit_keysched192_arch of twofish_whit_keysched192 is
|
| 5075 |
|
|
|
| 5076 |
|
|
-- we declare internal signals
|
| 5077 |
|
|
signal to_up_pht_1,
|
| 5078 |
|
|
to_shift_8_1,
|
| 5079 |
|
|
from_shift_8_1,
|
| 5080 |
|
|
to_shift_9_1,
|
| 5081 |
|
|
to_up_pht_2,
|
| 5082 |
|
|
to_shift_8_2,
|
| 5083 |
|
|
from_shift_8_2,
|
| 5084 |
|
|
to_shift_9_2,
|
| 5085 |
|
|
to_up_pht_3,
|
| 5086 |
|
|
to_shift_8_3,
|
| 5087 |
|
|
from_shift_8_3,
|
| 5088 |
|
|
to_shift_9_3,
|
| 5089 |
|
|
to_up_pht_4,
|
| 5090 |
|
|
to_shift_8_4,
|
| 5091 |
|
|
from_shift_8_4,
|
| 5092 |
|
|
to_shift_9_4,
|
| 5093 |
|
|
M0, M1, M2, M3, M4, M5 : std_logic_vector(31 downto 0);
|
| 5094 |
|
|
|
| 5095 |
|
|
signal byte0, byte1, byte2, byte3,
|
| 5096 |
|
|
byte4, byte5, byte6, byte7,
|
| 5097 |
|
|
byte8, byte9, byte10, byte11,
|
| 5098 |
|
|
byte12, byte13, byte14, byte15,
|
| 5099 |
|
|
byte16, byte17, byte18, byte19,
|
| 5100 |
|
|
byte20, byte21, byte22, byte23 : std_logic_vector(7 downto 0);
|
| 5101 |
|
|
|
| 5102 |
|
|
signal zero, one, two, three, four, five, six, seven : std_logic_vector(7 downto 0);
|
| 5103 |
|
|
|
| 5104 |
|
|
-- we declare the components to be used
|
| 5105 |
|
|
component pht
|
| 5106 |
|
|
port (
|
| 5107 |
|
|
up_in_pht,
|
| 5108 |
|
|
down_in_pht : in std_logic_vector(31 downto 0);
|
| 5109 |
|
|
up_out_pht,
|
| 5110 |
|
|
down_out_pht : out std_logic_vector(31 downto 0)
|
| 5111 |
|
|
);
|
| 5112 |
|
|
end component;
|
| 5113 |
|
|
|
| 5114 |
|
|
component h_192
|
| 5115 |
|
|
port (
|
| 5116 |
|
|
in_h192 : in std_logic_vector(7 downto 0);
|
| 5117 |
|
|
Mfirst_h192,
|
| 5118 |
|
|
Msecond_h192,
|
| 5119 |
|
|
Mthird_h192 : in std_logic_vector(31 downto 0);
|
| 5120 |
|
|
out_h192 : out std_logic_vector(31 downto 0)
|
| 5121 |
|
|
);
|
| 5122 |
|
|
end component;
|
| 5123 |
|
|
|
| 5124 |
|
|
-- begin architecture description
|
| 5125 |
|
|
begin
|
| 5126 |
|
|
|
| 5127 |
|
|
-- we produce the first eight numbers
|
| 5128 |
|
|
zero <= "00000000";
|
| 5129 |
|
|
one <= "00000001";
|
| 5130 |
|
|
two <= "00000010";
|
| 5131 |
|
|
three <= "00000011";
|
| 5132 |
|
|
four <= "00000100";
|
| 5133 |
|
|
five <= "00000101";
|
| 5134 |
|
|
six <= "00000110";
|
| 5135 |
|
|
seven <= "00000111";
|
| 5136 |
|
|
|
| 5137 |
|
|
-- we assign the input signal to the respective
|
| 5138 |
|
|
-- bytes as is described in the prototype
|
| 5139 |
|
|
byte23 <= in_key_twk192(7 downto 0);
|
| 5140 |
|
|
byte22 <= in_key_twk192(15 downto 8);
|
| 5141 |
|
|
byte21 <= in_key_twk192(23 downto 16);
|
| 5142 |
|
|
byte20 <= in_key_twk192(31 downto 24);
|
| 5143 |
|
|
byte19 <= in_key_twk192(39 downto 32);
|
| 5144 |
|
|
byte18 <= in_key_twk192(47 downto 40);
|
| 5145 |
|
|
byte17 <= in_key_twk192(55 downto 48);
|
| 5146 |
|
|
byte16 <= in_key_twk192(63 downto 56);
|
| 5147 |
|
|
byte15 <= in_key_twk192(71 downto 64);
|
| 5148 |
|
|
byte14 <= in_key_twk192(79 downto 72);
|
| 5149 |
|
|
byte13 <= in_key_twk192(87 downto 80);
|
| 5150 |
|
|
byte12 <= in_key_twk192(95 downto 88);
|
| 5151 |
|
|
byte11 <= in_key_twk192(103 downto 96);
|
| 5152 |
|
|
byte10 <= in_key_twk192(111 downto 104);
|
| 5153 |
|
|
byte9 <= in_key_twk192(119 downto 112);
|
| 5154 |
|
|
byte8 <= in_key_twk192(127 downto 120);
|
| 5155 |
|
|
byte7 <= in_key_twk192(135 downto 128);
|
| 5156 |
|
|
byte6 <= in_key_twk192(143 downto 136);
|
| 5157 |
|
|
byte5 <= in_key_twk192(151 downto 144);
|
| 5158 |
|
|
byte4 <= in_key_twk192(159 downto 152);
|
| 5159 |
|
|
byte3 <= in_key_twk192(167 downto 160);
|
| 5160 |
|
|
byte2 <= in_key_twk192(175 downto 168);
|
| 5161 |
|
|
byte1 <= in_key_twk192(183 downto 176);
|
| 5162 |
|
|
byte0 <= in_key_twk192(191 downto 184);
|
| 5163 |
|
|
|
| 5164 |
|
|
-- we form the M{0..5}
|
| 5165 |
|
|
M0 <= byte3 & byte2 & byte1 & byte0;
|
| 5166 |
|
|
M1 <= byte7 & byte6 & byte5 & byte4;
|
| 5167 |
|
|
M2 <= byte11 & byte10 & byte9 & byte8;
|
| 5168 |
|
|
M3 <= byte15 & byte14 & byte13 & byte12;
|
| 5169 |
|
|
M4 <= byte19 & byte18 & byte17 & byte16;
|
| 5170 |
|
|
M5 <= byte23 & byte22 & byte21 & byte20;
|
| 5171 |
|
|
|
| 5172 |
|
|
-- we produce the keys for the whitening steps
|
| 5173 |
|
|
-- keys K0,1
|
| 5174 |
|
|
-- upper h
|
| 5175 |
|
|
upper_h1: h_192
|
| 5176 |
|
|
port map (
|
| 5177 |
|
|
in_h192 => zero,
|
| 5178 |
|
|
Mfirst_h192 => M4,
|
| 5179 |
|
|
Msecond_h192 => M2,
|
| 5180 |
|
|
Mthird_h192 => M0,
|
| 5181 |
|
|
out_h192 => to_up_pht_1
|
| 5182 |
|
|
);
|
| 5183 |
|
|
|
| 5184 |
|
|
-- lower h
|
| 5185 |
|
|
lower_h1: h_192
|
| 5186 |
|
|
port map (
|
| 5187 |
|
|
in_h192 => one,
|
| 5188 |
|
|
Mfirst_h192 => M5,
|
| 5189 |
|
|
Msecond_h192 => M3,
|
| 5190 |
|
|
Mthird_h192 => M1,
|
| 5191 |
|
|
out_h192 => to_shift_8_1
|
| 5192 |
|
|
);
|
| 5193 |
|
|
|
| 5194 |
|
|
-- left rotate by 8
|
| 5195 |
|
|
from_shift_8_1(31 downto 8) <= to_shift_8_1(23 downto 0);
|
| 5196 |
|
|
from_shift_8_1(7 downto 0) <= to_shift_8_1(31 downto 24);
|
| 5197 |
|
|
|
| 5198 |
|
|
-- pht transformation
|
| 5199 |
|
|
pht_transform1: pht
|
| 5200 |
|
|
port map (
|
| 5201 |
|
|
up_in_pht => to_up_pht_1,
|
| 5202 |
|
|
down_in_pht => from_shift_8_1,
|
| 5203 |
|
|
up_out_pht => out_K0_twk192,
|
| 5204 |
|
|
down_out_pht => to_shift_9_1
|
| 5205 |
|
|
);
|
| 5206 |
|
|
|
| 5207 |
|
|
-- left rotate by 9
|
| 5208 |
|
|
out_K1_twk192(31 downto 9) <= to_shift_9_1(22 downto 0);
|
| 5209 |
|
|
out_K1_twk192(8 downto 0) <= to_shift_9_1(31 downto 23);
|
| 5210 |
|
|
|
| 5211 |
|
|
-- keys K2,3
|
| 5212 |
|
|
-- upper h
|
| 5213 |
|
|
upper_h2: h_192
|
| 5214 |
|
|
port map (
|
| 5215 |
|
|
in_h192 => two,
|
| 5216 |
|
|
Mfirst_h192 => M4,
|
| 5217 |
|
|
Msecond_h192 => M2,
|
| 5218 |
|
|
Mthird_h192 => M0,
|
| 5219 |
|
|
out_h192 => to_up_pht_2
|
| 5220 |
|
|
);
|
| 5221 |
|
|
|
| 5222 |
|
|
-- lower h
|
| 5223 |
|
|
lower_h2: h_192
|
| 5224 |
|
|
port map (
|
| 5225 |
|
|
in_h192 => three,
|
| 5226 |
|
|
Mfirst_h192 => M5,
|
| 5227 |
|
|
Msecond_h192 => M3,
|
| 5228 |
|
|
Mthird_h192 => M1,
|
| 5229 |
|
|
out_h192 => to_shift_8_2
|
| 5230 |
|
|
);
|
| 5231 |
|
|
|
| 5232 |
|
|
-- left rotate by 8
|
| 5233 |
|
|
from_shift_8_2(31 downto 8) <= to_shift_8_2(23 downto 0);
|
| 5234 |
|
|
from_shift_8_2(7 downto 0) <= to_shift_8_2(31 downto 24);
|
| 5235 |
|
|
|
| 5236 |
|
|
-- pht transformation
|
| 5237 |
|
|
pht_transform2: pht
|
| 5238 |
|
|
port map (
|
| 5239 |
|
|
up_in_pht => to_up_pht_2,
|
| 5240 |
|
|
down_in_pht => from_shift_8_2,
|
| 5241 |
|
|
up_out_pht => out_K2_twk192,
|
| 5242 |
|
|
down_out_pht => to_shift_9_2
|
| 5243 |
|
|
);
|
| 5244 |
|
|
|
| 5245 |
|
|
-- left rotate by 9
|
| 5246 |
|
|
out_K3_twk192(31 downto 9) <= to_shift_9_2(22 downto 0);
|
| 5247 |
|
|
out_K3_twk192(8 downto 0) <= to_shift_9_2(31 downto 23);
|
| 5248 |
|
|
|
| 5249 |
|
|
-- keys K4,5
|
| 5250 |
|
|
-- upper h
|
| 5251 |
|
|
upper_h3: h_192
|
| 5252 |
|
|
port map (
|
| 5253 |
|
|
in_h192 => four,
|
| 5254 |
|
|
Mfirst_h192 => M4,
|
| 5255 |
|
|
Msecond_h192 => M2,
|
| 5256 |
|
|
Mthird_h192 => M0,
|
| 5257 |
|
|
out_h192 => to_up_pht_3
|
| 5258 |
|
|
);
|
| 5259 |
|
|
|
| 5260 |
|
|
-- lower h
|
| 5261 |
|
|
lower_h3: h_192
|
| 5262 |
|
|
port map (
|
| 5263 |
|
|
in_h192 => five,
|
| 5264 |
|
|
Mfirst_h192 => M5,
|
| 5265 |
|
|
Msecond_h192 => M3,
|
| 5266 |
|
|
Mthird_h192 => M1,
|
| 5267 |
|
|
out_h192 => to_shift_8_3
|
| 5268 |
|
|
);
|
| 5269 |
|
|
|
| 5270 |
|
|
-- left rotate by 8
|
| 5271 |
|
|
from_shift_8_3(31 downto 8) <= to_shift_8_3(23 downto 0);
|
| 5272 |
|
|
from_shift_8_3(7 downto 0) <= to_shift_8_3(31 downto 24);
|
| 5273 |
|
|
|
| 5274 |
|
|
-- pht transformation
|
| 5275 |
|
|
pht_transform3: pht
|
| 5276 |
|
|
port map (
|
| 5277 |
|
|
up_in_pht => to_up_pht_3,
|
| 5278 |
|
|
down_in_pht => from_shift_8_3,
|
| 5279 |
|
|
up_out_pht => out_K4_twk192,
|
| 5280 |
|
|
down_out_pht => to_shift_9_3
|
| 5281 |
|
|
);
|
| 5282 |
|
|
|
| 5283 |
|
|
-- left rotate by 9
|
| 5284 |
|
|
out_K5_twk192(31 downto 9) <= to_shift_9_3(22 downto 0);
|
| 5285 |
|
|
out_K5_twk192(8 downto 0) <= to_shift_9_3(31 downto 23);
|
| 5286 |
|
|
|
| 5287 |
|
|
-- keys K6,7
|
| 5288 |
|
|
-- upper h
|
| 5289 |
|
|
upper_h4: h_192
|
| 5290 |
|
|
port map (
|
| 5291 |
|
|
in_h192 => six,
|
| 5292 |
|
|
Mfirst_h192 => M4,
|
| 5293 |
|
|
Msecond_h192 => M2,
|
| 5294 |
|
|
Mthird_h192 => M0,
|
| 5295 |
|
|
out_h192 => to_up_pht_4
|
| 5296 |
|
|
);
|
| 5297 |
|
|
|
| 5298 |
|
|
-- lower h
|
| 5299 |
|
|
lower_h4: h_192
|
| 5300 |
|
|
port map (
|
| 5301 |
|
|
in_h192 => seven,
|
| 5302 |
|
|
Mfirst_h192 => M5,
|
| 5303 |
|
|
Msecond_h192 => M3,
|
| 5304 |
|
|
Mthird_h192 => M1,
|
| 5305 |
|
|
out_h192 => to_shift_8_4
|
| 5306 |
|
|
);
|
| 5307 |
|
|
|
| 5308 |
|
|
-- left rotate by 8
|
| 5309 |
|
|
from_shift_8_4(31 downto 8) <= to_shift_8_4(23 downto 0);
|
| 5310 |
|
|
from_shift_8_4(7 downto 0) <= to_shift_8_4(31 downto 24);
|
| 5311 |
|
|
|
| 5312 |
|
|
-- pht transformation
|
| 5313 |
|
|
pht_transform4: pht
|
| 5314 |
|
|
port map (
|
| 5315 |
|
|
up_in_pht => to_up_pht_4,
|
| 5316 |
|
|
down_in_pht => from_shift_8_4,
|
| 5317 |
|
|
up_out_pht => out_K6_twk192,
|
| 5318 |
|
|
down_out_pht => to_shift_9_4
|
| 5319 |
|
|
);
|
| 5320 |
|
|
|
| 5321 |
|
|
-- left rotate by 9
|
| 5322 |
|
|
out_K7_twk192(31 downto 9) <= to_shift_9_4(22 downto 0);
|
| 5323 |
|
|
out_K7_twk192(8 downto 0) <= to_shift_9_4(31 downto 23);
|
| 5324 |
|
|
|
| 5325 |
|
|
end twofish_whit_keysched192_arch;
|
| 5326 |
|
|
|
| 5327 |
|
|
|
| 5328 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 5329 |
|
|
-- --
|
| 5330 |
|
|
-- new component --
|
| 5331 |
|
|
-- --
|
| 5332 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 5333 |
|
|
|
| 5334 |
|
|
--
|
| 5335 |
|
|
-- twofish encryption round with 128 bit key input
|
| 5336 |
|
|
--
|
| 5337 |
|
|
|
| 5338 |
|
|
library ieee;
|
| 5339 |
|
|
use ieee.std_logic_1164.all;
|
| 5340 |
|
|
|
| 5341 |
|
|
entity twofish_encryption_round192 is
|
| 5342 |
|
|
port (
|
| 5343 |
|
|
in1_ter192,
|
| 5344 |
|
|
in2_ter192,
|
| 5345 |
|
|
in3_ter192,
|
| 5346 |
|
|
in4_ter192,
|
| 5347 |
|
|
in_Sfirst_ter192,
|
| 5348 |
|
|
in_Ssecond_ter192,
|
| 5349 |
|
|
in_Sthird_ter192,
|
| 5350 |
|
|
in_key_up_ter192,
|
| 5351 |
|
|
in_key_down_ter192 : in std_logic_vector(31 downto 0);
|
| 5352 |
|
|
out1_ter192,
|
| 5353 |
|
|
out2_ter192,
|
| 5354 |
|
|
out3_ter192,
|
| 5355 |
|
|
out4_ter192 : out std_logic_vector(31 downto 0)
|
| 5356 |
|
|
);
|
| 5357 |
|
|
end twofish_encryption_round192;
|
| 5358 |
|
|
|
| 5359 |
|
|
architecture twofish_encryption_round192_arch of twofish_encryption_round192 is
|
| 5360 |
|
|
|
| 5361 |
|
|
-- we declare internal signals
|
| 5362 |
|
|
signal to_left_shift,
|
| 5363 |
|
|
from_right_shift,
|
| 5364 |
|
|
to_xor_with3,
|
| 5365 |
|
|
to_xor_with4 : std_logic_vector(31 downto 0);
|
| 5366 |
|
|
|
| 5367 |
|
|
component f_192
|
| 5368 |
|
|
port (
|
| 5369 |
|
|
up_in_f192,
|
| 5370 |
|
|
low_in_f192,
|
| 5371 |
|
|
S0_in_f192,
|
| 5372 |
|
|
S1_in_f192,
|
| 5373 |
|
|
S2_in_f192,
|
| 5374 |
|
|
up_key_f192,
|
| 5375 |
|
|
low_key_f192 : in std_logic_vector(31 downto 0);
|
| 5376 |
|
|
up_out_f192,
|
| 5377 |
|
|
low_out_f192 : out std_logic_vector(31 downto 0)
|
| 5378 |
|
|
);
|
| 5379 |
|
|
end component;
|
| 5380 |
|
|
|
| 5381 |
|
|
-- begin architecture description
|
| 5382 |
|
|
begin
|
| 5383 |
|
|
|
| 5384 |
|
|
-- we declare f_192
|
| 5385 |
|
|
function_f: f_192
|
| 5386 |
|
|
port map (
|
| 5387 |
|
|
up_in_f192 => in1_ter192,
|
| 5388 |
|
|
low_in_f192 => in2_ter192,
|
| 5389 |
|
|
S0_in_f192 => in_Sfirst_ter192,
|
| 5390 |
|
|
S1_in_f192 => in_Ssecond_ter192,
|
| 5391 |
|
|
S2_in_f192 => in_Sthird_ter192,
|
| 5392 |
|
|
up_key_f192 => in_key_up_ter192,
|
| 5393 |
|
|
low_key_f192 => in_key_down_ter192,
|
| 5394 |
|
|
up_out_f192 => to_xor_with3,
|
| 5395 |
|
|
low_out_f192 => to_xor_with4
|
| 5396 |
|
|
);
|
| 5397 |
|
|
|
| 5398 |
|
|
-- we perform the exchange
|
| 5399 |
|
|
-- in1_ter128 -> out3_ter128
|
| 5400 |
|
|
-- in2_ter128 -> out4_ter128
|
| 5401 |
|
|
-- in3_ter128 -> out1_ter128
|
| 5402 |
|
|
-- in4_ter128 -> out2_ter128
|
| 5403 |
|
|
|
| 5404 |
|
|
-- we perform the left xor between the upper f function and
|
| 5405 |
|
|
-- the third input (input 3)
|
| 5406 |
|
|
to_left_shift <= to_xor_with3 XOR in3_ter192;
|
| 5407 |
|
|
|
| 5408 |
|
|
-- we perform the left side rotation to the right by 1 and
|
| 5409 |
|
|
-- we perform the exchange too
|
| 5410 |
|
|
out1_ter192(30 downto 0) <= to_left_shift(31 downto 1);
|
| 5411 |
|
|
out1_ter192(31) <= to_left_shift(0);
|
| 5412 |
|
|
|
| 5413 |
|
|
-- we perform the right side rotation to the left by 1
|
| 5414 |
|
|
from_right_shift(0) <= in4_ter192(31);
|
| 5415 |
|
|
from_right_shift(31 downto 1) <= in4_ter192(30 downto 0);
|
| 5416 |
|
|
|
| 5417 |
|
|
-- we perform the right xor between the lower f function and
|
| 5418 |
|
|
-- the fourth input (input 4)
|
| 5419 |
|
|
out2_ter192 <= from_right_shift XOR to_xor_with4;
|
| 5420 |
|
|
|
| 5421 |
|
|
-- we perform the last exchanges
|
| 5422 |
|
|
out3_ter192 <= in1_ter192;
|
| 5423 |
|
|
out4_ter192 <= in2_ter192;
|
| 5424 |
|
|
|
| 5425 |
|
|
end twofish_encryption_round192_arch;
|
| 5426 |
|
|
|
| 5427 |
|
|
|
| 5428 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 5429 |
|
|
-- --
|
| 5430 |
|
|
-- new component --
|
| 5431 |
|
|
-- --
|
| 5432 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
|
| 5433 |
|
|
|
| 5434 |
|
|
--
|
| 5435 |
|
|
-- twofish decryption round with 128 bit key input
|
| 5436 |
|
|
--
|
| 5437 |
|
|
|
| 5438 |
|
|
library ieee;
|
| 5439 |
|
|
use ieee.std_logic_1164.all;
|
| 5440 |
|
|
|
| 5441 |
|
|
entity twofish_decryption_round192 is
|
| 5442 |
|
|
port (
|
| 5443 |
|
|
in1_tdr192,
|
| 5444 |
|
|
in2_tdr192,
|
| 5445 |
|
|
in3_tdr192,
|
| 5446 |
|
|
in4_tdr192,
|
| 5447 |
|
|
in_Sfirst_tdr192,
|
| 5448 |
|
|
in_Ssecond_tdr192,
|
| 5449 |
|
|
in_Sthird_tdr192,
|
| 5450 |
|
|
in_key_up_tdr192,
|
| 5451 |
|
|
in_key_down_tdr192 : in std_logic_vector(31 downto 0);
|
| 5452 |
|
|
out1_tdr192,
|
| 5453 |
|
|
out2_tdr192,
|
| 5454 |
|
|
out3_tdr192,
|
| 5455 |
|
|
out4_tdr192 : out std_logic_vector(31 downto 0)
|
| 5456 |
|
|
);
|
| 5457 |
|
|
end twofish_decryption_round192;
|
| 5458 |
|
|
|
| 5459 |
|
|
architecture twofish_decryption_round192_arch of twofish_decryption_round192 is
|
| 5460 |
|
|
|
| 5461 |
|
|
signal to_xor_with3,
|
| 5462 |
|
|
to_xor_with4,
|
| 5463 |
|
|
to_xor_with_up_f,
|
| 5464 |
|
|
from_xor_with_down_f : std_logic_vector(31 downto 0);
|
| 5465 |
|
|
|
| 5466 |
|
|
component f_192
|
| 5467 |
|
|
port (
|
| 5468 |
|
|
up_in_f192,
|
| 5469 |
|
|
low_in_f192,
|
| 5470 |
|
|
S0_in_f192,
|
| 5471 |
|
|
S1_in_f192,
|
| 5472 |
|
|
S2_in_f192,
|
| 5473 |
|
|
up_key_f192,
|
| 5474 |
|
|
low_key_f192 : in std_logic_vector(31 downto 0);
|
| 5475 |
|
|
up_out_f192,
|
| 5476 |
|
|
low_out_f192 : out std_logic_vector(31 downto 0)
|
| 5477 |
|
|
);
|
| 5478 |
|
|
end component;
|
| 5479 |
|
|
|
| 5480 |
|
|
begin
|
| 5481 |
|
|
|
| 5482 |
|
|
-- we instantiate f function
|
| 5483 |
|
|
function_f: f_192
|
| 5484 |
|
|
port map (
|
| 5485 |
|
|
up_in_f192 => in1_tdr192,
|
| 5486 |
|
|
low_in_f192 => in2_tdr192,
|
| 5487 |
|
|
S0_in_f192 => in_Sfirst_tdr192,
|
| 5488 |
|
|
S1_in_f192 => in_Ssecond_tdr192,
|
| 5489 |
|
|
S2_in_f192 => in_Sthird_tdr192,
|
| 5490 |
|
|
up_key_f192 => in_key_up_tdr192,
|
| 5491 |
|
|
low_key_f192 => in_key_down_tdr192,
|
| 5492 |
|
|
up_out_f192 => to_xor_with3,
|
| 5493 |
|
|
low_out_f192 => to_xor_with4
|
| 5494 |
|
|
);
|
| 5495 |
|
|
|
| 5496 |
|
|
-- output 1: input3 with upper f
|
| 5497 |
|
|
-- we first rotate the input3 by 1 bit leftwise
|
| 5498 |
|
|
to_xor_with_up_f(0) <= in3_tdr192(31);
|
| 5499 |
|
|
to_xor_with_up_f(31 downto 1) <= in3_tdr192(30 downto 0);
|
| 5500 |
|
|
|
| 5501 |
|
|
-- we perform the XOR with the upper output of f and the result
|
| 5502 |
|
|
-- is ouput 1
|
| 5503 |
|
|
out1_tdr192 <= to_xor_with_up_f XOR to_xor_with3;
|
| 5504 |
|
|
|
| 5505 |
|
|
-- output 2: input4 with lower f
|
| 5506 |
|
|
-- we perform the XOR with the lower output of f
|
| 5507 |
|
|
from_xor_with_down_f <= in4_tdr192 XOR to_xor_with4;
|
| 5508 |
|
|
|
| 5509 |
|
|
-- we perform the rotation by 1 bit rightwise and the result
|
| 5510 |
|
|
-- is output2
|
| 5511 |
|
|
out2_tdr192(31) <= from_xor_with_down_f(0);
|
| 5512 |
|
|
out2_tdr192(30 downto 0) <= from_xor_with_down_f(31 downto 1);
|
| 5513 |
|
|
|
| 5514 |
|
|
-- we assign outputs 3 and 4
|
| 5515 |
|
|
out3_tdr192 <= in1_tdr192;
|
| 5516 |
|
|
out4_tdr192 <= in2_tdr192;
|
| 5517 |
|
|
|
| 5518 |
|
|
end twofish_decryption_round192_arch;
|
| 5519 |
|
|
|
| 5520 |
|
|
|
| 5521 |
|
|
-- =============================================== --
|
| 5522 |
|
|
-- =============================================== --
|
| 5523 |
|
|
-- --
|
| 5524 |
|
|
-- fourth part: 256 key input dependent components --
|
| 5525 |
|
|
-- --
|
| 5526 |
|
|
-- =============================================== --
|
| 5527 |
|
|
-- =============================================== --
|
