OpenCores
URL https://opencores.org/ocsvn/twofish/twofish/trunk

Subversion Repositories twofish

[/] [twofish/] [trunk/] [vhdl/] [twofish_ecb_tbl_testbench_192bits.vhd] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 spyros
-- Twofish_ecb_tbl_testbench_192bits.vhd
2
-- Copyright (C) 2006 Spyros Ninos
3
--
4
-- This program is free software; you can redistribute it and/or modify 
5
-- it under the terms of the GNU General Public License as published by
6
-- the Free Software Foundation; either version 2 of the License, or
7
-- (at your option) any later version.
8
-- 
9
-- This program is distributed in the hope that it will be useful,
10
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
-- GNU General Public License for more details.
13
-- 
14
-- You should have received a copy of the GNU General Public License
15
-- along with this library; see the file COPYING.  If not, write to:
16
-- 
17
-- Free Software Foundation
18
-- 59 Temple Place - Suite 330
19
-- Boston, MA  02111-1307, USA.
20
--
21
-- description  :       this file is the testbench for the TABLES KAT of the twofish cipher with 192 bit key 
22
--
23
 
24
library ieee;
25
use ieee.std_logic_1164.all;
26
use ieee.std_logic_unsigned.all;
27
use ieee.std_logic_textio.all;
28
use ieee.std_logic_arith.all;
29
use std.textio.all;
30
 
31
entity tbl_testbench192 is
32
end tbl_testbench192;
33
 
34
architecture tbl_encryption192_testbench_arch of tbl_testbench192 is
35
 
36
        component       reg128
37
        port (
38
                        in_reg128       : in std_logic_vector(127 downto 0);
39
                        out_reg128 : out std_logic_vector(127 downto 0);
40
                        enable_reg128, reset_reg128, clk_reg128 : in std_logic
41
                        );
42
        end component;
43
 
44
        component twofish_keysched192
45
        port    (
46
                        odd_in_tk192,
47
                        even_in_tk192           : in std_logic_vector(7 downto 0);
48
                        in_key_tk192            : in std_logic_vector(191 downto 0);
49
                        out_key_up_tk192,
50
                        out_key_down_tk192      : out std_logic_vector(31 downto 0)
51
                        );
52
        end component;
53
 
54
        component twofish_whit_keysched192
55
        port    (
56
                        in_key_twk192           : in std_logic_vector(191 downto 0);
57
                        out_K0_twk192,
58
                        out_K1_twk192,
59
                        out_K2_twk192,
60
                        out_K3_twk192,
61
                        out_K4_twk192,
62
                        out_K5_twk192,
63
                        out_K6_twk192,
64
                        out_K7_twk192                   : out std_logic_vector(31 downto 0)
65
                        );
66
        end component;
67
 
68
        component twofish_encryption_round192
69
        port    (
70
                        in1_ter192,
71
                        in2_ter192,
72
                        in3_ter192,
73
                        in4_ter192,
74
                        in_Sfirst_ter192,
75
                        in_Ssecond_ter192,
76
                        in_Sthird_ter192,
77
                        in_key_up_ter192,
78
                        in_key_down_ter192              : in std_logic_vector(31 downto 0);
79
                        out1_ter192,
80
                        out2_ter192,
81
                        out3_ter192,
82
                        out4_ter192                     : out std_logic_vector(31 downto 0)
83
                        );
84
        end component;
85
 
86
        component twofish_data_input
87
        port    (
88
                        in_tdi  : in std_logic_vector(127 downto 0);
89
                        out_tdi : out std_logic_vector(127 downto 0)
90
                        );
91
        end component;
92
 
93
        component twofish_data_output
94
        port    (
95
                        in_tdo  : in std_logic_vector(127 downto 0);
96
                        out_tdo : out std_logic_vector(127 downto 0)
97
                        );
98
        end component;
99
 
100
        component demux128
101
        port    ( in_demux128 : in std_logic_vector(127 downto 0);
102
                        out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
103
                        selection_demux128 : in std_logic
104
                );
105
        end component;
106
 
107
        component mux128
108
        port ( in1_mux128, in2_mux128   : in std_logic_vector(127 downto 0);
109
                        selection_mux128        : in std_logic;
110
                        out_mux128 : out std_logic_vector(127 downto 0)
111
                );
112
        end component;
113
 
114
        component twofish_S192
115
        port    (
116
                        in_key_ts192            : in std_logic_vector(191 downto 0);
117
                        out_Sfirst_ts192,
118
                        out_Ssecond_ts192,
119
                        out_Sthird_ts192                        : out std_logic_vector(31 downto 0)
120
                        );
121
        end component;
122
 
123
        FILE input_file : text is in "twofish_ecb_tbl_testvalues_192bits.txt";
124
        FILE output_file : text is out "twofish_ecb_tbl_192bits_results.txt";
125
 
126
        -- we create the functions that transform a number to text
127
        -- transforming a signle digit to a character
128
        function digit_to_char(number : integer range 0 to 9) return character is
129
        begin
130
                case number is
131
                        when 0 => return '0';
132
                        when 1 => return '1';
133
                        when 2 => return '2';
134
                        when 3 => return '3';
135
                        when 4 => return '4';
136
                        when 5 => return '5';
137
                        when 6 => return '6';
138
                        when 7 => return '7';
139
                        when 8 => return '8';
140
                        when 9 => return '9';
141
                end case;
142
        end;
143
 
144
        -- transforming multi-digit number to text
145
        function to_text(int_number : integer range 1 to 50) return string is
146
                variable        our_text : string (1 to 3) := (others => ' ');
147
                variable hundreds,
148
                                                tens,
149
                                                ones            : integer range 0 to 9;
150
        begin
151
                ones := int_number mod 10;
152
                tens := ((int_number mod 100) - ones) / 10;
153
                hundreds := (int_number - (int_number mod 100)) / 100;
154
                our_text(1) := digit_to_char(hundreds);
155
                our_text(2) := digit_to_char(tens);
156
                our_text(3) := digit_to_char(ones);
157
                return our_text;
158
        end;
159
 
160
        signal                  odd_number,
161
                                even_number                                     : std_logic_vector(7 downto 0);
162
 
163
        signal                  input_data,
164
                                output_data,
165
                                to_encr_reg128,
166
                                from_tdi_to_xors,
167
                                to_output_whit_xors,
168
                                from_xors_to_tdo,
169
                                to_mux, to_demux,
170
                                from_input_whit_xors,
171
                                to_round,
172
                                to_input_mux                                                    : std_logic_vector(127 downto 0) ;
173
 
174
        signal                  twofish_key                             : std_logic_vector(191 downto 0);
175
 
176
        signal                  key_up,
177
                                key_down,
178
                                Sfirst,
179
                                Ssecond,
180
                                Sthird,
181
                                from_xor0,
182
                                from_xor1,
183
                                from_xor2,
184
                                from_xor3,
185
                                K0,K1,K2,K3,
186
                                K4,K5,K6,K7                                                             :  std_logic_vector(31 downto 0);
187
 
188
        signal                  clk                     : std_logic := '0';
189
        signal                  mux_selection   : std_logic := '0';
190
        signal                  demux_selection: std_logic := '0';
191
        signal                  enable_encr_reg : std_logic := '0';
192
        signal                  reset : std_logic := '0';
193
        signal                  enable_round_reg : std_logic := '0';
194
 
195
-- begin the testbench arch description
196
begin
197
 
198
 
199
        -- getting data to encrypt
200
        data_input: twofish_data_input
201
        port map        (
202
                                in_tdi  => input_data,
203
                                out_tdi => from_tdi_to_xors
204
                                );
205
 
206
        -- producing whitening keys K0..7
207
        the_whitening_step: twofish_whit_keysched192
208
        port    map (
209
                        in_key_twk192           => twofish_key,
210
                        out_K0_twk192 => K0,
211
                        out_K1_twk192 => K1,
212
                        out_K2_twk192 => K2,
213
                        out_K3_twk192 => K3,
214
                        out_K4_twk192 => K4,
215
                        out_K5_twk192 => K5,
216
                        out_K6_twk192 => K6,
217
                        out_K7_twk192 => K7
218
                        );
219
 
220
        -- performing the input whitening XORs
221
        from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
222
        from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
223
        from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
224
        from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
225
 
226
        from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
227
 
228
        round_reg: reg128
229
        port map ( in_reg128 => from_input_whit_xors,
230
                                out_reg128 => to_input_mux,
231
                                enable_reg128 => enable_round_reg,
232
                                reset_reg128 => reset,
233
                                clk_reg128 => clk );
234
 
235
        input_mux: mux128
236
        port map ( in1_mux128 => to_input_mux,
237
                                in2_mux128 => to_mux,
238
                                out_mux128 => to_round,
239
                                selection_mux128 => mux_selection
240
                                );
241
 
242
 
243
        -- creating a round
244
        the_keysched_of_the_round: twofish_keysched192
245
        port    map     (
246
                                odd_in_tk192 => odd_number,
247
                                even_in_tk192   => even_number,
248
                                in_key_tk192 => twofish_key,
249
                                out_key_up_tk192 => key_up,
250
                                out_key_down_tk192 => key_down
251
                                );
252
 
253
        producing_the_Skeys: twofish_S192
254
        port     map (
255
                                in_key_ts192            => twofish_key,
256
                                out_Sfirst_ts192 => Sfirst,
257
                                out_Ssecond_ts192 => Ssecond,
258
                                out_Sthird_ts192 => Sthird
259
                                );
260
 
261
        the_encryption_circuit: twofish_encryption_round192
262
        port map        (
263
                                in1_ter192 => to_round(127 downto 96),
264
                                in2_ter192 => to_round(95 downto 64),
265
                                in3_ter192 => to_round(63 downto 32),
266
                                in4_ter192 => to_round(31 downto 0),
267
                                in_Sfirst_ter192 => Sfirst,
268
                                in_Ssecond_ter192 => Ssecond,
269
                                in_Sthird_ter192 => Sthird,
270
                                in_key_up_ter192 => key_up,
271
                                in_key_down_ter192              => key_down,
272
                                out1_ter192 => to_encr_reg128(127 downto 96),
273
                                out2_ter192 => to_encr_reg128(95 downto 64),
274
                                out3_ter192 => to_encr_reg128(63 downto 32),
275
                                out4_ter192     => to_encr_reg128(31 downto 0)
276
                                );
277
 
278
        encr_reg: reg128
279
        port map ( in_reg128 => to_encr_reg128,
280
                                out_reg128 => to_demux,
281
                                enable_reg128 => enable_encr_reg,
282
                                reset_reg128 => reset,
283
                                clk_reg128 => clk );
284
 
285
        output_demux: demux128
286
        port map ( in_demux128 => to_demux,
287
                                        out1_demux128 => to_output_whit_xors,
288
                                        out2_demux128 => to_mux,
289
                                        selection_demux128 => demux_selection );
290
 
291
        -- don't forget the last swap !!!
292
        from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
293
        from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
294
        from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
295
        from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
296
 
297
        taking_the_output: twofish_data_output
298
        port    map (
299
                                in_tdo  => from_xors_to_tdo,
300
                                out_tdo => output_data
301
                                );
302
 
303
        -- we create the clock 
304
        clk <= not clk after 50 ns; -- period 100 ns
305
 
306
 
307
        tbl_proc: process
308
 
309
                variable key_f,  -- key input from file
310
                                        pt_f,  -- plaintext from file
311
                                        ct_f    : line; -- ciphertext from file
312
                variable        pt_v , -- plaintext vector
313
                                        ct_v    : std_logic_vector(127 downto 0); -- ciphertext vector
314
                variable key_v : std_logic_vector(191 downto 0);  -- key vector input
315
 
316
 
317
                variable counter : integer range 1 to 50 := 1;
318
                variable round : integer range 0 to 16 := 0;
319
 
320
        begin
321
                while not endfile(input_file) loop
322
                        readline(input_file, key_f);
323
                        readline(input_file, pt_f);
324
                        readline(input_file,ct_f);
325
                        hread(key_f,key_v);
326
                        hread(pt_f,pt_v);
327
                        hread(ct_f,ct_v);
328
                        twofish_key <= key_v;
329
                        input_data <= pt_v;
330
                        wait for 25 ns;
331
                        reset <= '1';
332
                        wait for 50 ns;
333
                        reset <= '0';
334
                        mux_selection <= '0';
335
                        demux_selection <= '1';
336
                        enable_encr_reg <= '0';
337
                        enable_round_reg <= '0';
338
                        wait for 50 ns;
339
                        enable_round_reg <= '1';
340
                        wait for 50 ns;
341
                        enable_round_reg <= '0';
342
 
343
                        -- the first round
344
                        even_number <= "00001000"; -- 8
345
                        odd_number <= "00001001"; -- 9
346
                        wait for 50 ns;
347
                        enable_encr_reg <= '1';
348
                        wait for 50 ns;
349
                        enable_encr_reg <= '0';
350
                        demux_selection <= '1';
351
                        mux_selection <= '1';
352
 
353
                        -- the rest 15 rounds
354
                        for round in 1 to 15 loop
355
                                even_number <= conv_std_logic_vector(((round*2)+8), 8);
356
                                odd_number <= conv_std_logic_vector(((round*2)+9), 8);
357
                                wait for 50 ns;
358
                                enable_encr_reg <= '1';
359
                                wait for 50 ns;
360
                                enable_encr_reg <= '0';
361
                        end loop;
362
 
363
                        -- taking final results
364
                        demux_selection <= '0';
365
                        wait for 25 ns;
366
                        assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
367
                        assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
368
                        counter := counter+1;
369
                        hwrite(pt_f,input_data);
370
                        hwrite(ct_f,output_data);
371
                        hwrite(key_f,key_v);
372
                        writeline(output_file,key_f);
373
                        writeline(output_file,pt_f);
374
                        writeline(output_file,ct_f);
375
                end loop;
376
                assert false    report  "***** Tables Known Answer Test with 192 bits key size ended succesfully! :) *****"     severity failure;
377
        end process tbl_proc;
378
 
379
end tbl_encryption192_testbench_arch;
380
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.