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gorban |
// UART core define
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//
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// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)
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// Company: Flextronics Semiconductor
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//
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// Filename: UART_defines.v
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//
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// Releases:
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// 1.1 First release
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//
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`define ADDR_WIDTH 3
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// Register addresses
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`define REG_RB 0 // receiver buffer
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`define REG_TR 0 // transmitter
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`define REG_IE 1 // Interrupt enable
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`define REG_II 2 // Interrupt identification
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`define REG_FC 2 // FIFO control
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`define REG_LC 3 // Line Control
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`define REG_MC 4 // Modem control
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`define REG_LS 5 // Line status
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`define REG_MS 6 // Modem status
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`define REG_DL1 0 // Divisor latch bytes (1-4)
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`define REG_DL2 1
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`define REG_DL3 4
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`define REG_DL4 5
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// Interrupt Enable register bits
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`define IE_RDA 0 // Received Data available interrupt
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`define IE_THRE 1 // Transmitter Holding Register empty interrupt
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`define IE_RLS 2 // Receiver Line Status Interrupt
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`define IE_MS 3 // Modem Status Interrupt
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// Interrupt Identification register bits
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`define II_IP 0 // Interrupt pending when 0
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`define II_II 3:1 // Interrupt identification
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// Interrupt identification values for bits 3:1
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`define II_RLS 3b`011 // Receiver Line Status
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`define II_RDA 3b`010 // Receiver Data available
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`define II_TI 3b`110 // Timeout Indication
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`define II_THRE 3b`001 // Transmitter Holding Register empty
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`define II_MS 3b`000 // Modem Status
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// FIFO Control Register bits
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`define FC_CR 0 // Clear receiver
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`define FC_CT 1 // Clear transmitter
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`define FC_TL 3:2 // Trigger level
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// FIFO trigger level values
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`define FC_1 2b`00
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`define FC_4 2b`01
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`define FC_8 2b`10
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`define FC_14 2b`11
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// Line Control register bits
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`define LC_BITS 1:0 // bits in character
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`define LC_SB 2 // stop bits
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`define LC_PE 3 // parity enable
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`define LC_EP 4 // even parity
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`define LC_SP 5 // stick parity
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`define LC_BC 6 // Break control
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`define LC_DL 7 // Divisor Latch access bit
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// Modem Control register bits
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`define MC_DTR 0
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`define MC_RTS 1
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`define MC_OUT1 2
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`define MC_OUT2 3
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`define MC_LB 4 // Loopback mode
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// Line Status Register bits
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`define LS_DR 0 // Data ready
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`define LS_OE 1 // Overrun Error
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`define LS_PE 2 // Parity Error
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`define LS_FE 3 // Framing Error
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`define LS_BI 4 // Break interrupt
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`define LS_TFE 5 // Transmit FIFO is empty
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`define LS_TE 6 // Transmitter Empty indicator
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`define LS_EI 7 // Error indicator
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// Modem Status Register bits
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`define MS_DCTS 0 // Delta signals
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`define MS_DDSR 1
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`define MS_TERI 2
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`define MS_DDCD 3
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`define MS_CCTS 4 // Complement signals
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`define MS_CDSR 5
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`define MS_CRI 6
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`define MS_CDCD 7
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// FIFO parameter defines
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`define FIFO_WIDTH 8
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`define FIFO_DEPTH 16
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`define FIFO_POINTER_W 4
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`define FIFO_COUNTER_W 5
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// receiver fifo has width 10 because it has parity and framing error bits
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`define FIFO_REC_WIDTH 10
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