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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_transmitter.v                                          ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter logic                                 ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5  2001/06/02 14:28:14  gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.1  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
 
`include "timescale.v"
`include "uart_defines.v"
 
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset);
 
input                           clk;
input                           wb_rst_i;
input   [7:0]                    lcr;
input                           tf_push;
input   [7:0]                    wb_dat_i;
input                           enable;
input                           tx_reset;
output                          stx_pad_o;
output  [2:0]                    state;
output  [`UART_FIFO_COUNTER_W-1:0]       tf_count;
 
reg     [2:0]    state;
reg     [4:0]    counter;
reg     [2:0]    bit_counter;   // counts the bits to be sent
reg     [6:0]    shift_out;      // output shift register
reg             stx_o_tmp;
reg             parity_xor;  // parity of the word
reg             tf_pop;
reg             bit_out;
 
// TX FIFO instance
//
// Transmitter FIFO signals
wire    [`UART_FIFO_WIDTH-1:0]   tf_data_in;
wire    [`UART_FIFO_WIDTH-1:0]   tf_data_out;
wire                            tf_push;
wire                            tf_underrun;
wire                            tf_overrun;
wire    [`UART_FIFO_COUNTER_W-1:0]       tf_count;
 
assign tf_data_in = wb_dat_i;
 
uart_fifo fifo_tx(      // error bit signal is not used in transmitter FIFO
        .clk(           clk             ),
        .wb_rst_i(      wb_rst_i        ),
        .data_in(       tf_data_in      ),
        .data_out(      tf_data_out     ),
        .push(          tf_push         ),
        .pop(           tf_pop          ),
        .underrun(      tf_underrun     ),
        .overrun(       tf_overrun      ),
        .count(         tf_count        ),
        .error_bit(),                 // Ta ni priklopljen. Prej je manjkal, dodal Igor
        .fifo_reset(    tx_reset        ),
        .reset_status(1'b0)
);
 
// TRANSMITTER FINAL STATE MACHINE
 
parameter s_idle        = 3'd0;
parameter s_send_start  = 3'd1;
parameter s_send_byte   = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop   = 3'd4;
parameter s_pop_byte    = 3'd5;
 
always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
        state       <= #1 s_idle;
        stx_o_tmp       <= #1 1'b1;
        counter   <= #1 5'b0;
        shift_out   <= #1 7'b0;
        bit_out     <= #1 1'b0;
        parity_xor  <= #1 1'b0;
        tf_pop      <= #1 1'b0;
        bit_counter <= #1 3'b0;
  end
  else
  if (enable)
  begin
        case (state)
        s_idle   :      if (~|tf_count) // if tf_count==0
                        begin
                                state <= #1 s_idle;
                                stx_o_tmp <= #1 1'b1;
                        end
                        else
                        begin
                                tf_pop <= #1 1'b0;
                                stx_o_tmp  <= #1 1'b1;
                                state  <= #1 s_pop_byte;
                        end
        s_pop_byte :    begin
                                tf_pop <= #1 1'b1;
                                case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
                                2'b00 : begin
                                        bit_counter <= #1 3'b100;
                                        parity_xor  <= #1 ^tf_data_out[4:0];
                                     end
                                2'b01 : begin
                                        bit_counter <= #1 3'b101;
                                        parity_xor  <= #1 ^tf_data_out[5:0];
                                     end
                                2'b10 : begin
                                        bit_counter <= #1 3'b110;
                                        parity_xor  <= #1 ^tf_data_out[6:0];
                                     end
                                2'b11 : begin
                                        bit_counter <= #1 3'b111;
                                        parity_xor  <= #1 ^tf_data_out[7:0];
                                     end
                                endcase
                                {shift_out[6:0], bit_out} <= #1 tf_data_out;
                                state <= #1 s_send_start;
                        end
        s_send_start :  begin
                                tf_pop <= #1 1'b0;
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 0;
                                        state <= #1 s_send_byte;
                                end
                                else
                                        counter <= #1 counter - 5'b00001;
                                stx_o_tmp <= #1 1'b0;
                        end
        s_send_byte :   begin
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        if (bit_counter > 3'b0)
                                        begin
                                                bit_counter <= #1 bit_counter - 1;
                                                {shift_out[5:0],bit_out  } <= #1 {shift_out[6:1], shift_out[0]};
                                                state <= #1 s_send_byte;
                                        end
                                        else   // end of byte
                                        if (~lcr[`UART_LC_PE])
                                        begin
                                                state <= #1 s_send_stop;
                                        end
                                        else
                                        begin
                                                case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
                                                2'b00:  bit_out <= #1 parity_xor;
                                                2'b01:  bit_out <= #1 1'b1;
                                                2'b10:  bit_out <= #1 ~parity_xor;
                                                2'b11:  bit_out <= #1 1'b0;
                                                endcase
                                                state <= #1 s_send_parity;
                                        end
                                        counter <= #1 0;
                                end
                                else
                                        counter <= #1 counter - 5'b00001;
                                stx_o_tmp <= #1 bit_out; // set output pin
                        end
        s_send_parity : begin
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 4'b0;
                                        state <= #1 s_send_stop;
                                end
                                else
                                        counter <= #1 counter - 5'b00001;
                                stx_o_tmp <= #1 bit_out;
                        end
        s_send_stop :  begin
                                if (~|counter)
                                  begin
                                                casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
                                                3'b0xx:   counter <= #1 5'b01101;     // 1 stop bit ok igor
                                                3'b100:   counter <= #1 5'b10101;     // 1.5 stop bit
                                                3'b1xx:   counter <= #1 5'b11101;     // 2 stop bits
                                                endcase
                                        end
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 0;
                                        state <= #1 s_idle;
                                end
                                else
                                        counter <= #1 counter - 5'b00001;
                                stx_o_tmp <= #1 1'b1;
                        end
 
                default : // should never get here
                        state <= #1 s_idle;
        endcase
  end // end if enable
end // transmitter logic
 
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;    // Break condition
 
endmodule

Line No.	Rev	Author	Line
1	27	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_transmitter.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core transmitter logic ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// None known ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// Thourough testing. ////`
25			`//// ////`
26			`//// Author(s): ////`
27			`//// - gorban@opencores.org ////`
28			`//// - Jacob Gorban ////`
29	29	mohor	`//// - Igor Mohor (igorm@opencores.org) ////`
30	27	mohor	`//// ////`
31			`//// Created: 2001/05/12 ////`
32			`//// Last Updated: 2001/05/17 ////`
33			`//// (See log for the revision history) ////`
34			`//// ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38	29	mohor	`//// Copyright (C) 2000, 2001 Authors ////`
39	27	mohor	`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	29	mohor	`// Revision 1.8 2001/08/23 16:05:05 mohor`
67			`// Stop bit bug fixed.`
68			`// Parity bug fixed.`
69			`// WISHBONE read cycle bug fixed,`
70			`// OE indicator (Overrun Error) bug fixed.`
71			`// PE indicator (Parity Error) bug fixed.`
72			`// Register read bug fixed.`
73			`//`
74	27	mohor	`// Revision 1.6 2001/06/23 11:21:48 gorban`
75			`// DL made 16-bit long. Fixed transmission/reception bugs.`
76			`//`
77			`// Revision 1.5 2001/06/02 14:28:14 gorban`
78			`// Fixed receiver and transmitter. Major bug fixed.`
79			`//`
80			`// Revision 1.4 2001/05/31 20:08:01 gorban`
81			`// FIFO changes and other corrections.`
82			`//`
83			`// Revision 1.3 2001/05/27 17:37:49 gorban`
84			`// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.`
85			`//`
86			`// Revision 1.2 2001/05/21 19:12:02 gorban`
87			`// Corrected some Linter messages.`
88			`//`
89			`// Revision 1.1 2001/05/17 18:34:18 gorban`
90			`// First 'stable' release. Should be sythesizable now. Also added new header.`
91			`//`
92			`// Revision 1.0 2001-05-17 21:27:12+02 jacob`
93			`// Initial revision`
94			`//`
95			`//`
96
97			`include "timescale.v"
98			`include "uart_defines.v"
99
100			`module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset);`
101
102			`input clk;`
103			`input wb_rst_i;`
104			`input [7:0] lcr;`
105			`input tf_push;`
106			`input [7:0] wb_dat_i;`
107			`input enable;`
108			`input tx_reset;`
109			`output stx_pad_o;`
110			`output [2:0] state;`
111			output [`UART_FIFO_COUNTER_W-1:0] tf_count;
112
113			`reg [2:0] state;`
114			`reg [4:0] counter;`
115			`reg [2:0] bit_counter; // counts the bits to be sent`
116			`reg [6:0] shift_out; // output shift register`
117			`reg stx_o_tmp;`
118			`reg parity_xor; // parity of the word`
119			`reg tf_pop;`
120			`reg bit_out;`
121
122			`// TX FIFO instance`
123			`//`
124			`// Transmitter FIFO signals`
125			wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
126			wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
127			`wire tf_push;`
128			`wire tf_underrun;`
129			`wire tf_overrun;`
130			wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
131
132			`assign tf_data_in = wb_dat_i;`
133
134			`uart_fifo fifo_tx( // error bit signal is not used in transmitter FIFO`
135			`.clk( clk ),`
136			`.wb_rst_i( wb_rst_i ),`
137			`.data_in( tf_data_in ),`
138			`.data_out( tf_data_out ),`
139			`.push( tf_push ),`
140			`.pop( tf_pop ),`
141			`.underrun( tf_underrun ),`
142			`.overrun( tf_overrun ),`
143			`.count( tf_count ),`
144			`.error_bit(), // Ta ni priklopljen. Prej je manjkal, dodal Igor`
145			`.fifo_reset( tx_reset ),`
146			`.reset_status(1'b0)`
147			`);`
148
149			`// TRANSMITTER FINAL STATE MACHINE`
150
151			`parameter s_idle = 3'd0;`
152			`parameter s_send_start = 3'd1;`
153			`parameter s_send_byte = 3'd2;`
154			`parameter s_send_parity = 3'd3;`
155			`parameter s_send_stop = 3'd4;`
156			`parameter s_pop_byte = 3'd5;`
157
158			`always @(posedge clk or posedge wb_rst_i)`
159			`begin`
160			`if (wb_rst_i)`
161			`begin`
162			`state <= #1 s_idle;`
163			`stx_o_tmp <= #1 1'b1;`
164			`counter <= #1 5'b0;`
165			`shift_out <= #1 7'b0;`
166			`bit_out <= #1 1'b0;`
167			`parity_xor <= #1 1'b0;`
168			`tf_pop <= #1 1'b0;`
169			`bit_counter <= #1 3'b0;`
170			`end`
171			`else`
172			`if (enable)`
173			`begin`
174			`case (state)`
175			`s_idle : if (~\|tf_count) // if tf_count==0`
176			`begin`
177			`state <= #1 s_idle;`
178			`stx_o_tmp <= #1 1'b1;`
179			`end`
180			`else`
181			`begin`
182			`tf_pop <= #1 1'b0;`
183			`stx_o_tmp <= #1 1'b1;`
184			`state <= #1 s_pop_byte;`
185			`end`
186			`s_pop_byte : begin`
187			`tf_pop <= #1 1'b1;`
188			case (lcr[/`UART_LC_BITS/1:0]) // number of bits in a word
189			`2'b00 : begin`
190			`bit_counter <= #1 3'b100;`
191			`parity_xor <= #1 ^tf_data_out[4:0];`
192			`end`
193			`2'b01 : begin`
194			`bit_counter <= #1 3'b101;`
195			`parity_xor <= #1 ^tf_data_out[5:0];`
196			`end`
197			`2'b10 : begin`
198			`bit_counter <= #1 3'b110;`
199			`parity_xor <= #1 ^tf_data_out[6:0];`
200			`end`
201			`2'b11 : begin`
202			`bit_counter <= #1 3'b111;`
203			`parity_xor <= #1 ^tf_data_out[7:0];`
204			`end`
205			`endcase`
206			`{shift_out[6:0], bit_out} <= #1 tf_data_out;`
207			`state <= #1 s_send_start;`
208			`end`
209			`s_send_start : begin`
210			`tf_pop <= #1 1'b0;`
211			`if (~\|counter)`
212			`counter <= #1 5'b01111;`
213			`else`
214			`if (counter == 5'b00001)`
215			`begin`
216			`counter <= #1 0;`
217			`state <= #1 s_send_byte;`
218			`end`
219			`else`
220			`counter <= #1 counter - 5'b00001;`
221			`stx_o_tmp <= #1 1'b0;`
222			`end`
223			`s_send_byte : begin`
224			`if (~\|counter)`
225			`counter <= #1 5'b01111;`
226			`else`
227			`if (counter == 5'b00001)`
228			`begin`
229			`if (bit_counter > 3'b0)`
230			`begin`
231			`bit_counter <= #1 bit_counter - 1;`
232			`{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};`
233			`state <= #1 s_send_byte;`
234			`end`
235			`else // end of byte`
236			if (~lcr[`UART_LC_PE])
237			`begin`
238			`state <= #1 s_send_stop;`
239			`end`
240			`else`
241			`begin`
242			case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
243			`2'b00: bit_out <= #1 parity_xor;`
244			`2'b01: bit_out <= #1 1'b1;`
245			`2'b10: bit_out <= #1 ~parity_xor;`
246			`2'b11: bit_out <= #1 1'b0;`
247			`endcase`
248			`state <= #1 s_send_parity;`
249			`end`
250			`counter <= #1 0;`
251			`end`
252			`else`
253			`counter <= #1 counter - 5'b00001;`
254			`stx_o_tmp <= #1 bit_out; // set output pin`
255			`end`
256			`s_send_parity : begin`
257			`if (~\|counter)`
258			`counter <= #1 5'b01111;`
259			`else`
260			`if (counter == 5'b00001)`
261			`begin`
262			`counter <= #1 4'b0;`
263			`state <= #1 s_send_stop;`
264			`end`
265			`else`
266			`counter <= #1 counter - 5'b00001;`
267			`stx_o_tmp <= #1 bit_out;`
268			`end`
269			`s_send_stop : begin`
270			`if (~\|counter)`
271			`begin`
272			casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
273			`3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor`
274			`3'b100: counter <= #1 5'b10101; // 1.5 stop bit`
275			`3'b1xx: counter <= #1 5'b11101; // 2 stop bits`
276			`endcase`
277			`end`
278			`else`
279			`if (counter == 5'b00001)`
280			`begin`
281			`counter <= #1 0;`
282			`state <= #1 s_idle;`
283			`end`
284			`else`
285			`counter <= #1 counter - 5'b00001;`
286			`stx_o_tmp <= #1 1'b1;`
287			`end`
288
289			`default : // should never get here`
290			`state <= #1 s_idle;`
291			`endcase`
292			`end // end if enable`
293			`end // transmitter logic`
294
295			assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
296
297			`endmodule`

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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Blame information for rev 29