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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_transmitter.v                                          ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter logic                                 ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11  2001/10/29 17:00:46  gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5  2001/06/02 14:28:14  gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.1  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "uart_defines.v"
 
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset, lsr_mask);
 
input                                                                           clk;
input                                                                           wb_rst_i;
input [7:0]                                                              lcr;
input                                                                           tf_push;
input [7:0]                                                              wb_dat_i;
input                                                                           enable;
input                                                                           tx_reset;
input                                                                           lsr_mask; //reset of fifo
output                                                                          stx_pad_o;
output [2:0]                                                             state;
output [`UART_FIFO_COUNTER_W-1:0]        tf_count;
 
reg [2:0]                                                                        state;
reg [4:0]                                                                        counter;
reg [2:0]                                                                        bit_counter;   // counts the bits to be sent
reg [6:0]                                                                        shift_out;      // output shift register
reg                                                                                     stx_o_tmp;
reg                                                                                     parity_xor;  // parity of the word
reg                                                                                     tf_pop;
reg                                                                                     bit_out;
 
// TX FIFO instance
//
// Transmitter FIFO signals
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_in;
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_out;
wire                                                                                    tf_push;
wire                                                                                    tf_underrun;
wire                                                                                    tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0]          tf_count;
 
assign                                                                          tf_data_in = wb_dat_i;
 
uart_fifo fifo_tx(      // error bit signal is not used in transmitter FIFO
        .clk(           clk             ),
        .wb_rst_i(      wb_rst_i        ),
        .data_in(       tf_data_in      ),
        .data_out(      tf_data_out     ),
        .push(          tf_push         ),
        .pop(           tf_pop          ),
        .underrun(      tf_underrun     ),
        .overrun(       tf_overrun      ),
        .count(         tf_count        ),
        .error_bit(),                 // Ta ni priklopljen. Prej je manjkal, dodal Igor
        .fifo_reset(    tx_reset        ),
        .reset_status(lsr_mask)
);
 
// TRANSMITTER FINAL STATE MACHINE
 
parameter s_idle        = 3'd0;
parameter s_send_start  = 3'd1;
parameter s_send_byte   = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop   = 3'd4;
parameter s_pop_byte    = 3'd5;
 
always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
        state       <= #1 s_idle;
        stx_o_tmp       <= #1 1'b1;
        counter   <= #1 5'b0;
        shift_out   <= #1 7'b0;
        bit_out     <= #1 1'b0;
        parity_xor  <= #1 1'b0;
        tf_pop      <= #1 1'b0;
        bit_counter <= #1 3'b0;
  end
  else
  if (enable)
  begin
        case (state)
        s_idle   :      if (~|tf_count) // if tf_count==0
                        begin
                                state <= #1 s_idle;
                                stx_o_tmp <= #1 1'b1;
                        end
                        else
                        begin
                                tf_pop <= #1 1'b0;
                                stx_o_tmp  <= #1 1'b1;
                                state  <= #1 s_pop_byte;
                        end
        s_pop_byte :    begin
                                tf_pop <= #1 1'b1;
                                case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
                                2'b00 : begin
                                        bit_counter <= #1 3'b100;
                                        parity_xor  <= #1 ^tf_data_out[4:0];
                                     end
                                2'b01 : begin
                                        bit_counter <= #1 3'b101;
                                        parity_xor  <= #1 ^tf_data_out[5:0];
                                     end
                                2'b10 : begin
                                        bit_counter <= #1 3'b110;
                                        parity_xor  <= #1 ^tf_data_out[6:0];
                                     end
                                2'b11 : begin
                                        bit_counter <= #1 3'b111;
                                        parity_xor  <= #1 ^tf_data_out[7:0];
                                     end
                                endcase
                                {shift_out[6:0], bit_out} <= #1 tf_data_out;
                                state <= #1 s_send_start;
                        end
        s_send_start :  begin
                                tf_pop <= #1 1'b0;
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 0;
                                        state <= #1 s_send_byte;
                                end
                                else
                                        counter <= #1 counter - 1'b1;
                                stx_o_tmp <= #1 1'b0;
                        end
        s_send_byte :   begin
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        if (bit_counter > 3'b0)
                                        begin
                                                bit_counter <= #1 bit_counter - 1'b1;
                                                {shift_out[5:0],bit_out  } <= #1 {shift_out[6:1], shift_out[0]};
                                                state <= #1 s_send_byte;
                                        end
                                        else   // end of byte
                                        if (~lcr[`UART_LC_PE])
                                        begin
                                                state <= #1 s_send_stop;
                                        end
                                        else
                                        begin
                                                case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
                                                2'b00:  bit_out <= #1 ~parity_xor;
                                                2'b01:  bit_out <= #1 1'b1;
                                                2'b10:  bit_out <= #1 parity_xor;
                                                2'b11:  bit_out <= #1 1'b0;
                                                endcase
                                                state <= #1 s_send_parity;
                                        end
                                        counter <= #1 0;
                                end
                                else
                                        counter <= #1 counter - 1'b1;
                                stx_o_tmp <= #1 bit_out; // set output pin
                        end
        s_send_parity : begin
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 4'b0;
                                        state <= #1 s_send_stop;
                                end
                                else
                                        counter <= #1 counter - 1'b1;
                                stx_o_tmp <= #1 bit_out;
                        end
        s_send_stop :  begin
                                if (~|counter)
                                  begin
                                                casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
                                                3'b0xx:   counter <= #1 5'b01101;     // 1 stop bit ok igor
                                                3'b100:   counter <= #1 5'b10101;     // 1.5 stop bit
                                                3'b1xx:   counter <= #1 5'b11101;     // 2 stop bits
                                                endcase
                                        end
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 0;
                                        state <= #1 s_idle;
                                end
                                else
                                        counter <= #1 counter - 1'b1;
                                stx_o_tmp <= #1 1'b1;
                        end
 
                default : // should never get here
                        state <= #1 s_idle;
        endcase
  end // end if enable
end // transmitter logic
 
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;    // Break condition
 
endmodule

Line No.	Rev	Author	Line
1	27	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_transmitter.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core transmitter logic ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// None known ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// Thourough testing. ////`
25			`//// ////`
26			`//// Author(s): ////`
27			`//// - gorban@opencores.org ////`
28			`//// - Jacob Gorban ////`
29	29	mohor	`//// - Igor Mohor (igorm@opencores.org) ////`
30	27	mohor	`//// ////`
31			`//// Created: 2001/05/12 ////`
32			`//// Last Updated: 2001/05/17 ////`
33			`//// (See log for the revision history) ////`
34			`//// ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38	29	mohor	`//// Copyright (C) 2000, 2001 Authors ////`
39	27	mohor	`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	39	mohor	`// Revision 1.12 2001/11/07 17:51:52 gorban`
67			`// Heavily rewritten interrupt and LSR subsystems.`
68			`// Many bugs hopefully squashed.`
69			`//`
70	37	gorban	`// Revision 1.11 2001/10/29 17:00:46 gorban`
71			`// fixed parity sending and tx_fifo resets over- and underrun`
72			`//`
73	34	gorban	`// Revision 1.10 2001/10/20 09:58:40 gorban`
74			`// Small synopsis fixes`
75			`//`
76	33	gorban	`// Revision 1.9 2001/08/24 21:01:12 mohor`
77			`// Things connected to parity changed.`
78			`// Clock devider changed.`
79			`//`
80	29	mohor	`// Revision 1.8 2001/08/23 16:05:05 mohor`
81			`// Stop bit bug fixed.`
82			`// Parity bug fixed.`
83			`// WISHBONE read cycle bug fixed,`
84			`// OE indicator (Overrun Error) bug fixed.`
85			`// PE indicator (Parity Error) bug fixed.`
86			`// Register read bug fixed.`
87			`//`
88	27	mohor	`// Revision 1.6 2001/06/23 11:21:48 gorban`
89			`// DL made 16-bit long. Fixed transmission/reception bugs.`
90			`//`
91			`// Revision 1.5 2001/06/02 14:28:14 gorban`
92			`// Fixed receiver and transmitter. Major bug fixed.`
93			`//`
94			`// Revision 1.4 2001/05/31 20:08:01 gorban`
95			`// FIFO changes and other corrections.`
96			`//`
97			`// Revision 1.3 2001/05/27 17:37:49 gorban`
98			`// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.`
99			`//`
100			`// Revision 1.2 2001/05/21 19:12:02 gorban`
101			`// Corrected some Linter messages.`
102			`//`
103			`// Revision 1.1 2001/05/17 18:34:18 gorban`
104			`// First 'stable' release. Should be sythesizable now. Also added new header.`
105			`//`
106			`// Revision 1.0 2001-05-17 21:27:12+02 jacob`
107			`// Initial revision`
108			`//`
109			`//`
110
111	33	gorban	`// synopsys translate_off`
112	27	mohor	`include "timescale.v"
113	33	gorban	`// synopsys translate_on`
114
115	27	mohor	`include "uart_defines.v"
116
117	37	gorban	`module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset, lsr_mask);`
118	27	mohor
119	34	gorban	`input clk;`
120			`input wb_rst_i;`
121			`input [7:0] lcr;`
122			`input tf_push;`
123			`input [7:0] wb_dat_i;`
124			`input enable;`
125			`input tx_reset;`
126	37	gorban	`input lsr_mask; //reset of fifo`
127	34	gorban	`output stx_pad_o;`
128			`output [2:0] state;`
129			output [`UART_FIFO_COUNTER_W-1:0] tf_count;
130	27	mohor
131	34	gorban	`reg [2:0] state;`
132			`reg [4:0] counter;`
133			`reg [2:0] bit_counter; // counts the bits to be sent`
134			`reg [6:0] shift_out; // output shift register`
135			`reg stx_o_tmp;`
136			`reg parity_xor; // parity of the word`
137			`reg tf_pop;`
138			`reg bit_out;`
139	27	mohor
140			`// TX FIFO instance`
141			`//`
142			`// Transmitter FIFO signals`
143	34	gorban	wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
144			wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
145			`wire tf_push;`
146			`wire tf_underrun;`
147			`wire tf_overrun;`
148			wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
149	27	mohor
150	34	gorban	`assign tf_data_in = wb_dat_i;`
151	27	mohor
152			`uart_fifo fifo_tx( // error bit signal is not used in transmitter FIFO`
153			`.clk( clk ),`
154			`.wb_rst_i( wb_rst_i ),`
155			`.data_in( tf_data_in ),`
156			`.data_out( tf_data_out ),`
157			`.push( tf_push ),`
158			`.pop( tf_pop ),`
159			`.underrun( tf_underrun ),`
160			`.overrun( tf_overrun ),`
161			`.count( tf_count ),`
162			`.error_bit(), // Ta ni priklopljen. Prej je manjkal, dodal Igor`
163			`.fifo_reset( tx_reset ),`
164	37	gorban	`.reset_status(lsr_mask)`
165	27	mohor	`);`
166
167			`// TRANSMITTER FINAL STATE MACHINE`
168
169			`parameter s_idle = 3'd0;`
170			`parameter s_send_start = 3'd1;`
171			`parameter s_send_byte = 3'd2;`
172			`parameter s_send_parity = 3'd3;`
173			`parameter s_send_stop = 3'd4;`
174			`parameter s_pop_byte = 3'd5;`
175
176			`always @(posedge clk or posedge wb_rst_i)`
177			`begin`
178			`if (wb_rst_i)`
179			`begin`
180			`state <= #1 s_idle;`
181			`stx_o_tmp <= #1 1'b1;`
182			`counter <= #1 5'b0;`
183			`shift_out <= #1 7'b0;`
184			`bit_out <= #1 1'b0;`
185			`parity_xor <= #1 1'b0;`
186			`tf_pop <= #1 1'b0;`
187			`bit_counter <= #1 3'b0;`
188			`end`
189			`else`
190			`if (enable)`
191			`begin`
192			`case (state)`
193			`s_idle : if (~\|tf_count) // if tf_count==0`
194			`begin`
195			`state <= #1 s_idle;`
196			`stx_o_tmp <= #1 1'b1;`
197			`end`
198			`else`
199			`begin`
200			`tf_pop <= #1 1'b0;`
201			`stx_o_tmp <= #1 1'b1;`
202			`state <= #1 s_pop_byte;`
203			`end`
204			`s_pop_byte : begin`
205			`tf_pop <= #1 1'b1;`
206			case (lcr[/`UART_LC_BITS/1:0]) // number of bits in a word
207			`2'b00 : begin`
208			`bit_counter <= #1 3'b100;`
209			`parity_xor <= #1 ^tf_data_out[4:0];`
210			`end`
211			`2'b01 : begin`
212			`bit_counter <= #1 3'b101;`
213			`parity_xor <= #1 ^tf_data_out[5:0];`
214			`end`
215			`2'b10 : begin`
216			`bit_counter <= #1 3'b110;`
217			`parity_xor <= #1 ^tf_data_out[6:0];`
218			`end`
219			`2'b11 : begin`
220			`bit_counter <= #1 3'b111;`
221			`parity_xor <= #1 ^tf_data_out[7:0];`
222			`end`
223			`endcase`
224			`{shift_out[6:0], bit_out} <= #1 tf_data_out;`
225			`state <= #1 s_send_start;`
226			`end`
227			`s_send_start : begin`
228			`tf_pop <= #1 1'b0;`
229			`if (~\|counter)`
230			`counter <= #1 5'b01111;`
231			`else`
232			`if (counter == 5'b00001)`
233			`begin`
234			`counter <= #1 0;`
235			`state <= #1 s_send_byte;`
236			`end`
237			`else`
238	39	mohor	`counter <= #1 counter - 1'b1;`
239	27	mohor	`stx_o_tmp <= #1 1'b0;`
240			`end`
241			`s_send_byte : begin`
242			`if (~\|counter)`
243			`counter <= #1 5'b01111;`
244			`else`
245			`if (counter == 5'b00001)`
246			`begin`
247			`if (bit_counter > 3'b0)`
248			`begin`
249	39	mohor	`bit_counter <= #1 bit_counter - 1'b1;`
250	27	mohor	`{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};`
251			`state <= #1 s_send_byte;`
252			`end`
253			`else // end of byte`
254			if (~lcr[`UART_LC_PE])
255			`begin`
256			`state <= #1 s_send_stop;`
257			`end`
258			`else`
259			`begin`
260			case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
261	34	gorban	`2'b00: bit_out <= #1 ~parity_xor;`
262	27	mohor	`2'b01: bit_out <= #1 1'b1;`
263	34	gorban	`2'b10: bit_out <= #1 parity_xor;`
264	27	mohor	`2'b11: bit_out <= #1 1'b0;`
265			`endcase`
266			`state <= #1 s_send_parity;`
267			`end`
268			`counter <= #1 0;`
269			`end`
270			`else`
271	39	mohor	`counter <= #1 counter - 1'b1;`
272	27	mohor	`stx_o_tmp <= #1 bit_out; // set output pin`
273			`end`
274			`s_send_parity : begin`
275			`if (~\|counter)`
276			`counter <= #1 5'b01111;`
277			`else`
278			`if (counter == 5'b00001)`
279			`begin`
280			`counter <= #1 4'b0;`
281			`state <= #1 s_send_stop;`
282			`end`
283			`else`
284	39	mohor	`counter <= #1 counter - 1'b1;`
285	27	mohor	`stx_o_tmp <= #1 bit_out;`
286			`end`
287			`s_send_stop : begin`
288			`if (~\|counter)`
289			`begin`
290			casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
291			`3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor`
292			`3'b100: counter <= #1 5'b10101; // 1.5 stop bit`
293			`3'b1xx: counter <= #1 5'b11101; // 2 stop bits`
294			`endcase`
295			`end`
296			`else`
297			`if (counter == 5'b00001)`
298			`begin`
299			`counter <= #1 0;`
300			`state <= #1 s_idle;`
301			`end`
302			`else`
303	39	mohor	`counter <= #1 counter - 1'b1;`
304	27	mohor	`stx_o_tmp <= #1 1'b1;`
305			`end`
306
307			`default : // should never get here`
308			`state <= #1 s_idle;`
309			`endcase`
310			`end // end if enable`
311			`end // transmitter logic`
312
313			assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
314
315			`endmodule`

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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Blame information for rev 39