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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_wb.v] - Blame information for rev 50

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_wb.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core WISHBONE interface.                               ////
////                                                              ////
////  Known problems (limits):                                    ////
////  Inserts one wait state on all transfers.                    ////
////  Note affected signals and the way they are affected.        ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.9  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.8  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.7  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/21 19:12:01  gorban
// Corrected some Linter messages.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:13+02  jacob
// Initial revision
//
//
 
// UART core WISHBONE interface 
//
// Author: Jacob Gorban   (jacob.gorban@flextronicssemi.com)
// Company: Flextronics Semiconductor
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
 
module uart_wb (clk, wb_rst_i,
        wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
        wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
        we_o, re_o // Write and read enable output for the core
);
 
input             clk;
 
// WISHBONE interface   
input             wb_rst_i;
input             wb_we_i;
input             wb_stb_i;
input             wb_cyc_i;
input [3:0]   wb_sel_i;
input [`UART_ADDR_WIDTH-1:0]     wb_adr_i; //WISHBONE address line
 
`ifdef DATA_BUS_WIDTH_8
input [7:0]  wb_dat_i; //input WISHBONE bus 
output [7:0] wb_dat_o;
reg [7:0]         wb_dat_o;
wire [7:0]        wb_dat_i;
reg [7:0]         wb_dat_is;
`else // for 32 data bus mode
input [31:0]  wb_dat_i; //input WISHBONE bus 
output [31:0] wb_dat_o;
reg [31:0]         wb_dat_o;
wire [31:0]   wb_dat_i;
reg [31:0]         wb_dat_is;
`endif // !`ifdef DATA_BUS_WIDTH_8
 
output [`UART_ADDR_WIDTH-1:0]    wb_adr_int; // internal signal for address bus
input [7:0]   wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
output [7:0]  wb_dat8_i;
input [31:0]  wb_dat32_o; // 32 bit data output (for debug interface)
output            wb_ack_o;
output            we_o;
output            re_o;
 
wire                      we_o;
reg                       wb_ack_o;
reg [7:0]          wb_dat8_i;
wire [7:0]         wb_dat8_o;
wire [`UART_ADDR_WIDTH-1:0]      wb_adr_int; // internal signal for address bus
reg [`UART_ADDR_WIDTH-1:0]       wb_adr_is;
reg                                                             wb_we_is;
reg                                                             wb_cyc_is;
reg                                                             wb_stb_is;
reg [3:0]                                                wb_sel_is;
wire [3:0]   wb_sel_i;
reg                      wb_ack; // wb_ack is sampled to make 2 clock wait state between transfers 
reg                      wre ;// timing control signal for write or read enable
 
// wb_ack_o FSM
reg [1:0]         wbstate;
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) begin
                wb_ack_o <= #1 1'b0;
                wbstate <= #1 0;
        end else
                case (wbstate)
                        0: begin
                                if (wb_stb_is & wb_cyc_is) begin
                                        wre <= #1 0;
                                        wbstate <= #1 1;
                                        wb_ack_o <= #1 1;
                                end else begin
                                        wre <= #1 1;
                                        wb_ack_o <= #1 0;
                                end
                        end
                        1: begin
                           wb_ack_o <= #1 0;
                                wbstate <= #1 2;
                                wre <= #1 0;
                        end
                        2,3: begin
                                wb_ack_o <= #1 0;
                                wbstate <= #1 0;
                                wre <= #1 0;
                        end
                endcase
 
assign we_o =  wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers      
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers      
 
// Sample input signals
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) begin
                wb_adr_is <= #1 0;
                wb_we_is <= #1 0;
                wb_cyc_is <= #1 0;
                wb_stb_is <= #1 0;
                wb_dat_is <= #1 0;
                wb_sel_is <= #1 0;
        end else begin
                wb_adr_is <= #1 wb_adr_i;
                wb_we_is <= #1 wb_we_i;
                wb_cyc_is <= #1 wb_cyc_i;
                wb_stb_is <= #1 wb_stb_i;
                wb_dat_is <= #1 wb_dat_i;
                wb_sel_is <= #1 wb_sel_i;
        end
 
assign wb_adr_int = wb_adr_is;
 
`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 0;
        else
                wb_dat_o <= #1 wb_dat8_o;
 
always @(wb_dat_is)
        wb_dat8_i = wb_dat_is;
 
`else // 32-bit bus
// put output to the correct byte in 32 bits using select line
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                wb_dat_o <= #1 0;
        else if (re_o)
                case (wb_sel_is)
                        4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};
                        4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};
                        4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};
                        4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};
                        4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output
                        default: wb_dat_o <= #1 0;
                endcase // case(wb_sel_i)
 
always @(wb_sel_is or wb_dat_is)
        case (wb_sel_is)
                4'b0001 : wb_dat8_i = wb_dat_is[7:0];
                4'b0010 : wb_dat8_i = wb_dat_is[15:8];
                4'b0100 : wb_dat8_i = wb_dat_is[23:16];
                4'b1000 : wb_dat8_i = wb_dat_is[31:24];
                default : wb_dat8_i = wb_dat_is[7:0];
        endcase // case(wb_sel_i)
 
`endif // !`ifdef DATA_BUS_WIDTH_8
 
endmodule
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	27	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	33	gorban	`//// uart_wb.v ////`
4	27	mohor	`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core WISHBONE interface. ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// Inserts one wait state on all transfers. ////`
22			`//// Note affected signals and the way they are affected. ////`
23			`//// ////`
24			`//// To Do: ////`
25			`//// Nothing. ////`
26			`//// ////`
27			`//// Author(s): ////`
28			`//// - gorban@opencores.org ////`
29			`//// - Jacob Gorban ////`
30	29	mohor	`//// - Igor Mohor (igorm@opencores.org) ////`
31	27	mohor	`//// ////`
32			`//// Created: 2001/05/12 ////`
33			`//// Last Updated: 2001/05/17 ////`
34			`//// (See log for the revision history) ////`
35			`//// ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39	29	mohor	`//// Copyright (C) 2000, 2001 Authors ////`
40	27	mohor	`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: not supported by cvs2svn $`
67	50	gorban	`// Revision 1.10 2001/12/03 21:44:29 gorban`
68			`// Updated specification documentation.`
69			`// Added full 32-bit data bus interface, now as default.`
70			`// Address is 5-bit wide in 32-bit data bus mode.`
71			`// Added wb_sel_i input to the core. It's used in the 32-bit mode.`
72			`// Added debug interface with two 32-bit read-only registers in 32-bit mode.`
73			`// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.`
74			`// My small test bench is modified to work with 32-bit mode.`
75			`//`
76	48	gorban	`// Revision 1.9 2001/10/20 09:58:40 gorban`
77			`// Small synopsis fixes`
78			`//`
79	33	gorban	`// Revision 1.8 2001/08/24 21:01:12 mohor`
80			`// Things connected to parity changed.`
81			`// Clock devider changed.`
82			`//`
83	29	mohor	`// Revision 1.7 2001/08/23 16:05:05 mohor`
84			`// Stop bit bug fixed.`
85			`// Parity bug fixed.`
86			`// WISHBONE read cycle bug fixed,`
87			`// OE indicator (Overrun Error) bug fixed.`
88			`// PE indicator (Parity Error) bug fixed.`
89			`// Register read bug fixed.`
90			`//`
91	27	mohor	`// Revision 1.4 2001/05/31 20:08:01 gorban`
92			`// FIFO changes and other corrections.`
93			`//`
94			`// Revision 1.3 2001/05/21 19:12:01 gorban`
95			`// Corrected some Linter messages.`
96			`//`
97			`// Revision 1.2 2001/05/17 18:34:18 gorban`
98			`// First 'stable' release. Should be sythesizable now. Also added new header.`
99			`//`
100			`// Revision 1.0 2001-05-17 21:27:13+02 jacob`
101			`// Initial revision`
102			`//`
103			`//`
104
105			`// UART core WISHBONE interface`
106			`//`
107			`// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)`
108			`// Company: Flextronics Semiconductor`
109			`//`
110
111	33	gorban	`// synopsys translate_off`
112	27	mohor	`include "timescale.v"
113	33	gorban	`// synopsys translate_on`
114	50	gorban	`include "uart_defines.v"
115
116	48	gorban	`module uart_wb (clk, wb_rst_i,`
117	50	gorban	`wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,`
118			`wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,`
119	27	mohor	`we_o, re_o // Write and read enable output for the core`
120	48	gorban	`);`
121	27	mohor
122	48	gorban	`input clk;`
123	27	mohor
124			`// WISHBONE interface`
125	48	gorban	`input wb_rst_i;`
126			`input wb_we_i;`
127			`input wb_stb_i;`
128			`input wb_cyc_i;`
129			`input [3:0] wb_sel_i;`
130	50	gorban	input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line
131
132	48	gorban	`ifdef DATA_BUS_WIDTH_8
133			`input [7:0] wb_dat_i; //input WISHBONE bus`
134			`output [7:0] wb_dat_o;`
135			`reg [7:0] wb_dat_o;`
136			`wire [7:0] wb_dat_i;`
137	50	gorban	`reg [7:0] wb_dat_is;`
138	48	gorban	`else // for 32 data bus mode
139			`input [31:0] wb_dat_i; //input WISHBONE bus`
140			`output [31:0] wb_dat_o;`
141			`reg [31:0] wb_dat_o;`
142			`wire [31:0] wb_dat_i;`
143	50	gorban	`reg [31:0] wb_dat_is;`
144			`endif // !`ifdef DATA_BUS_WIDTH_8
145
146			output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
147	48	gorban	`input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o`
148			`output [7:0] wb_dat8_i;`
149			`input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)`
150			`output wb_ack_o;`
151			`output we_o;`
152			`output re_o;`
153	27	mohor
154	48	gorban	`wire we_o;`
155			`reg wb_ack_o;`
156			`reg [7:0] wb_dat8_i;`
157			`wire [7:0] wb_dat8_o;`
158	50	gorban	wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
159			reg [`UART_ADDR_WIDTH-1:0] wb_adr_is;
160			`reg wb_we_is;`
161			`reg wb_cyc_is;`
162			`reg wb_stb_is;`
163			`reg [3:0] wb_sel_is;`
164			`wire [3:0] wb_sel_i;`
165			`reg wb_ack; // wb_ack is sampled to make 2 clock wait state between transfers`
166			`reg wre ;// timing control signal for write or read enable`
167	27	mohor
168	50	gorban	`// wb_ack_o FSM`
169			`reg [1:0] wbstate;`
170			`always @(posedge clk or posedge wb_rst_i)`
171			`if (wb_rst_i) begin`
172	27	mohor	`wb_ack_o <= #1 1'b0;`
173	50	gorban	`wbstate <= #1 0;`
174			`end else`
175			`case (wbstate)`
176			`0: begin`
177			`if (wb_stb_is & wb_cyc_is) begin`
178			`wre <= #1 0;`
179			`wbstate <= #1 1;`
180			`wb_ack_o <= #1 1;`
181			`end else begin`
182			`wre <= #1 1;`
183			`wb_ack_o <= #1 0;`
184			`end`
185			`end`
186			`1: begin`
187			`wb_ack_o <= #1 0;`
188			`wbstate <= #1 2;`
189			`wre <= #1 0;`
190			`end`
191			`2,3: begin`
192			`wb_ack_o <= #1 0;`
193			`wbstate <= #1 0;`
194			`wre <= #1 0;`
195			`end`
196			`endcase`
197	27	mohor
198	50	gorban	`assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers`
199			`assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers`
200	27	mohor
201	50	gorban	`// Sample input signals`
202			`always @(posedge clk or posedge wb_rst_i)`
203			`if (wb_rst_i) begin`
204			`wb_adr_is <= #1 0;`
205			`wb_we_is <= #1 0;`
206			`wb_cyc_is <= #1 0;`
207			`wb_stb_is <= #1 0;`
208			`wb_dat_is <= #1 0;`
209			`wb_sel_is <= #1 0;`
210			`end else begin`
211			`wb_adr_is <= #1 wb_adr_i;`
212			`wb_we_is <= #1 wb_we_i;`
213			`wb_cyc_is <= #1 wb_cyc_i;`
214			`wb_stb_is <= #1 wb_stb_i;`
215			`wb_dat_is <= #1 wb_dat_i;`
216			`wb_sel_is <= #1 wb_sel_i;`
217			`end`
218
219			`assign wb_adr_int = wb_adr_is;`
220
221	48	gorban	`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
222			`always @(posedge clk or posedge wb_rst_i)`
223			`if (wb_rst_i)`
224			`wb_dat_o <= #1 0;`
225			`else`
226			`wb_dat_o <= #1 wb_dat8_o;`
227
228	50	gorban	`always @(wb_dat_is)`
229			`wb_dat8_i = wb_dat_is;`
230	48	gorban
231			`else // 32-bit bus
232			`// put output to the correct byte in 32 bits using select line`
233			`always @(posedge clk or posedge wb_rst_i)`
234			`if (wb_rst_i)`
235			`wb_dat_o <= #1 0;`
236			`else if (re_o)`
237	50	gorban	`case (wb_sel_is)`
238	48	gorban	`4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};`
239			`4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};`
240			`4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};`
241			`4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};`
242			`4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output`
243			`default: wb_dat_o <= #1 0;`
244			`endcase // case(wb_sel_i)`
245
246	50	gorban	`always @(wb_sel_is or wb_dat_is)`
247			`case (wb_sel_is)`
248			`4'b0001 : wb_dat8_i = wb_dat_is[7:0];`
249			`4'b0010 : wb_dat8_i = wb_dat_is[15:8];`
250			`4'b0100 : wb_dat8_i = wb_dat_is[23:16];`
251			`4'b1000 : wb_dat8_i = wb_dat_is[31:24];`
252			`default : wb_dat8_i = wb_dat_is[7:0];`
253	48	gorban	`endcase // case(wb_sel_i)`
254
255			`endif // !`ifdef DATA_BUS_WIDTH_8
256
257	27	mohor	`endmodule`
258	48	gorban
259
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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_wb.v] - Blame information for rev 50