URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [sim/] [rtl_sim/] [log/] [uart_interrupts_report.log] - Blame information for rev 106

Line No.	Rev	Author	Line
1	96	tadejm
2			`---------------------------------------------------------------------------`
3
4			`Initialization of UART.`
5			`PASSED!`
6			`Simulation Time: 621000`
7
8			`---------------------------------------------------------------------------`
9
10			`Interrupt test.`
11			`FAILED!`
12			`Failure message: Bit 5 of LSR register not '1'!.`
13			`Simulation Time: 5734521200`
14
15			`---------------------------------------------------------------------------`
16
17			`TEST CASE execution summary:`
18			`Number of tests PASSED=1`
19			`Number of tests FAILED=1`
20			`Simulation End Time: 5834521200`
21
22			`---------------------------------------------------------------------------`
23