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96 |
tadejm |
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---------------------------------------------------------------------------
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- Initialization of UART.
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---------------------------------------------------------------------------
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Time: 200 (testbench_utilities.do_reset)
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*N, RESET signal asynchronously set.
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Time: 200 (testbench_utilities.disable_clk_generators)
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*N, Following clocks are DISABLED:
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Time: 200 (testbench_utilities.disable_clk_generators)
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*N, - WB_clk
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Time: 200 (testbench_utilities.disable_clk_generators)
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*N, - RX_clk
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Time: 200 (testbench_utilities.disable_clk_generators)
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*N, - TX_clk
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Time: 200 (testbench_utilities.disable_clk_generators)
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*N, - TX_clk_divided
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Time: 200 (testbench_utilities.set_device_tx_rx_clk_divisor)
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*N, UART DEVICE TX/RX clock divisor: 1000.
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Time: 200 (testbench_utilities.set_wb_clock_period)
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*N, WB & UART DEVICE TX/RX clock period: 64.
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Time: 200 (testbench_utilities.enable_clk_generators)
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*N, Following clocks are ENABLED:
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Time: 200 (testbench_utilities.enable_clk_generators)
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*N, - WB_clk
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Time: 200 (testbench_utilities.enable_clk_generators)
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*N, - RX_clk
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Time: 200 (testbench_utilities.enable_clk_generators)
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*N, - TX_clk
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Time: 200 (testbench_utilities.enable_clk_generators)
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*N, - TX_clk_divided
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Time: 11100 (testbench_utilities.release_reset)
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*N, RESET signal released synchronously to WB clk.
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Time: 11100 (uart_wb_utilities.write_dlr)
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*N, DLAB in LC Register is going to be 1.
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Time: 11100 (uart_wb_utilities.write_dlr)
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*N, Current LCR = 3.
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Time: 11100 (uart_wb_utilities.write_lcr)
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*N, WRITING UART's LC Register.
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Time: 101000 (uart_wb_utilities.write_lcr)
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*N, Write LCR = 83.
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Time: 101000 (uart_wb_utilities.write_dlr)
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*N, WRITING UART's DL Register [15:8].
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Time: 161000 (uart_wb_utilities.write_dlr)
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*N, Write DLR [15:8] = 10.
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Time: 161000 (uart_wb_utilities.write_dlr)
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*N, WRITING UART's DL Register [ 7:0].
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Time: 281000 (uart_wb_utilities.write_dlr)
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*N, Write DLR [ 7:0] = 0.
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Time: 281000 (uart_wb_utilities.write_dlr)
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*N, DLAB in LC Register is going to be 0.
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Time: 281000 (uart_wb_utilities.write_lcr)
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*N, WRITING UART's LC Register.
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Time: 371000 (uart_wb_utilities.write_lcr)
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*N, Write LCR = 3.
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Time: 371000 (uart_wb_utilities.write_ier)
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*N, WRITING UART's IE Register.
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Time: 411000 (uart_wb_utilities.write_ier)
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*N, Write IER = 7.
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Time: 411000 (uart_wb_utilities.write_fcr)
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*N, WRITING UART's FC Register.
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Time: 511000 (uart_wb_utilities.write_fcr)
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*N, Write FCR = c0.
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Time: 511000 (uart_wb_utilities.write_lcr)
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*N, WRITING UART's LC Register.
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Time: 621000 (uart_wb_utilities.write_lcr)
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*N, Write LCR = 3.
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Time: 621000 (uart_device_utilities.set_rx_length)
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*N, SETTING RX CHAR length.
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Time: 621000 (uart_device_utilities.set_rx_length)
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*N, Length: 8.
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Time: 621000 (uart_device_utilities.disable_rx_parity)
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*N, DISABLING RX CHAR parity.
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Time: 621000 (uart_device_utilities.set_rx_second_stop_bit)
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*N, SETTING RX CHAR 1 stop bit.
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Time: 621000 (uart_device_utilities.set_tx_length)
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*N, SETTING TX CHAR length.
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Time: 621000 (uart_device_utilities.set_tx_length)
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*N, Length: 8.
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Time: 621000 (uart_device_utilities.disable_tx_parity)
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*N, DISABLING TX CHAR parity.
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Time: 621000 (uart_device_utilities.correct_tx_parity)
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*N, DISABLING WRONG parity generation.
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Time: 621000 (uart_device_utilities.correct_tx_frame)
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*N, DISABLING WRONG frame generation.
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Time: 621000 (uart_device_utilities.generate_tx_glitch)
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*N, DISABLING 1 TIME glitch generation with CLKs delay.
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Time: 621000 (uart_device_utilities.generate_tx_glitch)
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*N, CLKs delay from start bit edge: 0.
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---------------------------------------------------------------------------
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- Interrupt test.
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---------------------------------------------------------------------------
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| 95 |
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Time: 621000 (testbench_utilities.wait_for_num_of_wb_clk)
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*N, Waiting for following number of WB CLK periods:
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Time: 621000 (testbench_utilities.wait_for_num_of_wb_clk)
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*N, Waiting for following number of WB CLK periods: 450000.
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Time: 701000 (uart_wb_utilities.write_char)
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*N, Write TRR = aa.
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Time: 5734501000 (testbench.write_tx_shift_reg_read_tx_fifo)
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*N, TX FIFO is empty!
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Time: 5734521200 (testbench.tx_fifo_status_changing)
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*E, Bit 5 of LSR register not '1'!
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