1 |
95 |
tadejm |
#!/bin/csh -f
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# GLOBAL VARIABLES
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###################
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set sim_top = testbench;
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set arg_tool = "NCSim"; # By default NCSim is used as simulation tool
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set arg_wave = 0; # By default waveform is not recorded
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set arg_verb = 0; # By default basic display on monitor (no verbose)
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set arg_test = 0; # By default all testcases are simulated
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# GETTING PARAMETERS FROM COMMAND LINE
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#######################################
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set cur_arg = 1;
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if ($#argv < 1) then
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echo ""
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echo " Verification without any argument:"
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else
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while ($cur_arg <= $#argv)
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switch ("$argv[$cur_arg]")
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# HELP ARGUMENT
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case "-h":
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goto help
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breaksw
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case "help":
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goto help
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breaksw
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# TOOL ARGUMENT
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case "-m":
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set arg_tool = "ModelSim";
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echo " $argv[$cur_arg] - ModelSim tool"
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breaksw
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case "modelsim"
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set arg_tool = "ModelSim";
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echo " $argv[$cur_arg] - ModelSim tool"
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breaksw
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# WAVEFORM ARGUMENT
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case "-w":
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@ arg_wave = 1;
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echo " $argv[$cur_arg] - Waveform"
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breaksw
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case "waveform":
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@ arg_wave = 1;
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echo " $argv[$cur_arg] - Waveform"
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breaksw
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# VERBOSE ARGUMENT
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case "-v":
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@ arg_verb = 1;
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echo " $argv[$cur_arg] - Verbose"
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breaksw
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case "verbose":
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@ arg_verb = 1;
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echo " $argv[$cur_arg] - Verbose"
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breaksw
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# TESTCASE ARGUMENT
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default:
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if (-e ../../../bench/verilog/testcases/$argv[$cur_arg].v) then
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set arg_test = $argv[$cur_arg];
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echo " $argv[$cur_arg] - Testcase"
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# INVALID ARGUMENT
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else
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echo ""
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echo " Invalid verification argument: $argv[$cur_arg]"
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goto help
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endif
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breaksw
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endsw
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@ cur_arg++
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end
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endif
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# SIMULATION LOOP
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##################
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set cur_test_num = 0;
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simulate:
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# DELETING FILES
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#################
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# Prepared files
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if (-e ./file_list.lst) then
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rm -rf ./file_list.lst
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endif
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if (-e ../bin/cds.lib) then
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rm -rf ../bin/cds.lib
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endif
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if (-e ../bin/hdl.var) then
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rm -rf ../bin/hdl.var
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endif
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if (-e ./compile.args) then
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rm -rf ./compile.args
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endif
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if (-e ./elab.args) then
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rm -rf ./elab.args
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endif
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if (-e ./sim.args) then
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rm -rf ./sim.args
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endif
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if (-e ./sim.tcl) then
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rm -rf ./sim.tcl
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endif
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if (-e ./sim.do) then
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rm -rf ./sim.do
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endif
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# Projects, Libraries and Logs
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if (-e ./uart.mpf) then
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rm -rf ./uart.mpf
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endif
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if (-e ./work) then
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rm -rf ./work
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endif
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if (-e ./INCA_libs/worklib) then
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rm -rf ./INCA_libs/worklib
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endif
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# PREPARING FILE LIST
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######################
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# Design files
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echo "../../../rtl/verilog/uart_top.v" >> ./file_list.lst
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echo "../../../rtl/verilog/uart_wb.v" >> ./file_list.lst
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echo "../../../rtl/verilog/uart_transmitter.v" >> ./file_list.lst
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echo "../../../rtl/verilog/uart_receiver.v" >> ./file_list.lst
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echo "../../../rtl/verilog/uart_tfifo.v" >> ./file_list.lst
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echo "../../../rtl/verilog/uart_rfifo.v" >> ./file_list.lst
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echo "../../../rtl/verilog/uart_regs.v" >> ./file_list.lst
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echo "../../../rtl/verilog/uart_debug_if.v" >> ./file_list.lst
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# Testcase file
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if ($arg_test == 0) then
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set i = 0;
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foreach testcase (../../../bench/verilog/testcases/uart*.v)
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if ($i == $cur_test_num) then
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set testcase_i = $testcase:t:r
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endif
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@ i++
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end
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set max_test_num = $i;
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else
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set testcase_i = $arg_test;
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set max_test_num = 1;
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endif
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echo "//////////////////////////////////////////////////" > ./file_list.lst
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echo "// File created within script ${0}" >> ./file_list.lst
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echo "// path: $cwd" >> ./file_list.lst
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echo "// user: $user" >> ./file_list.lst
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echo "//////////////////////////////////////////////////" >> ./file_list.lst
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echo "../../../bench/verilog/testcases/$testcase_i.v" >> ./file_list.lst
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# Delete vawe out file for this testcase, if it already exists
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if (-e ../out/$testcase_i.wlf) then
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rm -rf ../out/$testcase_i.wlf
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endif
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# Delete log out file for this testcase, if it already exists
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if (-e ../log/$testcase_i.log) then
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rm -rf ../log/$testcase_i.log
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endif
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# Testbench files
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echo "../../../bench/verilog/uart_testbench.v" >> ./file_list.lst
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echo "../../../bench/verilog/wb_master_model.v" >> ./file_list.lst
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echo "../../../bench/verilog/uart_device.v" >> ./file_list.lst
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echo "../../../bench/verilog/uart_testbench_utilities.v" >> ./file_list.lst
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echo "../../../bench/verilog/uart_wb_utilities.v" >> ./file_list.lst
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echo "../../../bench/verilog/uart_device_utilities.v" >> ./file_list.lst
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# COMPILING & ELABORATING
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##########################
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if ("$arg_tool" == "NCSim") then
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# cds.lib library file
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echo "//////////////////////////////////////////////////" > ../bin/cds.lib
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echo "// File created within script ${0}" >> ../bin/cds.lib
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echo "// path: $cwd" >> ../bin/cds.lib
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echo "// user: $0" >> ../bin/cds.lib
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echo "//////////////////////////////////////////////////" >> ../bin/cds.lib
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echo "DEFINE worklib ./INCA_libs/worklib" >> ../bin/cds.lib
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# hdl.var variable file
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echo "//////////////////////////////////////////////////" > ../bin/hdl.var
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echo "// File created within script ${0}" >> ../bin/hdl.var
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echo "// path: $cwd" >> ../bin/hdl.var
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echo "// user: $0" >> ../bin/hdl.var
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echo "//////////////////////////////////////////////////" >> ../bin/hdl.var
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echo "INCLUDE \$CDS_INST_DIR/tools/inca/files/hdl.var" >> ../bin/hdl.var
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echo "DEFINE WORK worklib" >> ../bin/hdl.var
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# compile.args argument file
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echo "//////////////////////////////////////////////////" > ./compile.args
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echo "// File created within script ${0}" >> ./compile.args
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echo "// path: $cwd" >> ./compile.args
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echo "// user: $0" >> ./compile.args
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echo "//////////////////////////////////////////////////" >> ./compile.args
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echo "-CDSLIB ../bin/cds.lib" >> ./compile.args
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echo "-HDLVAR ../bin/hdl.var" >> ./compile.args
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echo "-MESSAGES" >> ./compile.args
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echo "-NOCOPYRIGHT" >> ./compile.args
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echo "-INCDIR ../../../rtl/verilog" >> ./compile.args
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echo "-INCDIR ../../../bench/verilog" >> ./compile.args
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echo "-INCDIR ../../../bench/verilog/testcases" >> ./compile.args
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216 |
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if ($arg_verb == 1) then
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echo "-DEFINE VERBOSE" >> ./compile.args
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endif
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cat ./file_list.lst >> ./compile.args
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# compiling
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ncvlog -LOGFILE ../log/$testcase_i.compile.log -f ./compile.args #> /dev/null
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# elab.args argument file
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echo "//////////////////////////////////////////////////" > ./elab.args
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echo "// File created within script ${0}" >> ./elab.args
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echo "// path: $cwd" >> ./elab.args
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228 |
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echo "// user: $0" >> ./elab.args
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229 |
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echo "//////////////////////////////////////////////////" >> ./elab.args
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230 |
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echo "-CDSLIB ../bin/cds.lib" >> ./elab.args
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231 |
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echo "-HDLVAR ../bin/hdl.var" >> ./elab.args
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232 |
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echo "-MESSAGES" >> ./elab.args
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233 |
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echo "-NOCOPYRIGHT" >> ./elab.args
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234 |
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echo "-NOTIMINGCHECKS" >> ./elab.args
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235 |
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echo "-SNAPSHOT worklib.testbench:rtl" >> ./elab.args
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236 |
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echo "-NO_TCHK_MSG" >> ./elab.args
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237 |
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echo "-ACCESS +RWC" >> ./elab.args
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238 |
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echo "worklib.$sim_top" >> ./elab.args
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239 |
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240 |
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# elaborating
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ncelab -LOGFILE ../log/$testcase_i.elab.log -f ./elab.args #> /dev/null
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else
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# compile.args argument file
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245 |
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echo "+libext+.v" >> ./compile.args
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246 |
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echo "-y ../../../rtl/verilog" >> ./compile.args
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247 |
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echo "-y ../../../bench/verilog" >> ./compile.args
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248 |
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echo "-y ../../../bench/verilog/testcases" >> ./compile.args
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249 |
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echo "-work ./work" >> ./compile.args
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250 |
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echo "+incdir+../../../rtl/verilog" >> ./compile.args
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251 |
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echo "+incdir+../../../bench/verilog" >> ./compile.args
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252 |
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echo '+define+LOG_DIR=\"../log/$testcase_i\"' >> ./compile.args
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253 |
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if ($arg_verb == 1) then
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254 |
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echo "+define+VERBOSE" >> ./compile.args
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255 |
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endif
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256 |
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cat ./file_list.lst >> ./compile.args
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257 |
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258 |
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# open project
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259 |
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# echo "project new ./ testbench ./work" >> ./sim.do
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260 |
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vlib -dos ./work
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261 |
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262 |
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# compiling
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263 |
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# echo "vlog -f ./compile.args" >> ./sim.do
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264 |
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vlog -f ./compile.args
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endif
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266 |
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267 |
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268 |
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# SIMULATING
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#############
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270 |
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if ("$arg_tool" == "NCSim") then
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272 |
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273 |
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# sim.args argument file
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274 |
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echo "//////////////////////////////////////////////////" > ./sim.args
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275 |
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echo "// File created within script ${0}" >> ./sim.args
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276 |
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echo "// path: $cwd" >> ./sim.args
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277 |
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echo "// user: $0" >> ./sim.args
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278 |
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echo "//////////////////////////////////////////////////" >> ./sim.args
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279 |
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echo "-CDSLIB ../bin/cds.lib" >> ./sim.args
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280 |
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echo "-HDLVAR ../bin/hdl.var" >> ./sim.args
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281 |
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echo "-MESSAGES" >> ./sim.args
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282 |
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echo "-NOCOPYRIGHT" >> ./sim.args
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283 |
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echo "-INPUT ./sim.tcl" >> ./sim.args
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284 |
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echo "worklib.testbench:rtl" >> ./sim.args
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285 |
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286 |
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# sim.tcl file
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287 |
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echo "//////////////////////////////////////////////////" > ./sim.tcl
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288 |
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echo "// File created within script ${0}" >> ./sim.tcl
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289 |
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echo "// path: $cwd" >> ./sim.tcl
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290 |
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echo "// user: $0" >> ./sim.tcl
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291 |
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echo "//////////////////////////////////////////////////" >> ./sim.tcl
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292 |
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if ($arg_wave) then
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293 |
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echo "database -open waves -shm -into ../out/waves.shm" >> ./sim.tcl
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294 |
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echo "probe -create -database waves $sim_top -shm -all -depth all" >> ./sim.tcl
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295 |
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echo "run" >> ./sim.tcl
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296 |
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else
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297 |
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echo "run" >> ./sim.tcl
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298 |
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endif
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299 |
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echo "quit" >> ./sim.tcl
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300 |
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301 |
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# simulating
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302 |
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ncsim -LICQUEUE -LOGFILE ../log/$testcase_i.sim.log -f ./sim.args
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303 |
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else
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304 |
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305 |
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# sim.do do file
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306 |
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echo "vsim work.testbench work.testbench_utilities work.uart_wb_utilities work.uart_device_utilities work.testcase -wlf ../out/$testcase_i.wlf" >> ./sim.do
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307 |
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if ($arg_wave) then
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308 |
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echo "log -r -internal -ports /testbench/*" >> ./sim.do
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309 |
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endif
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310 |
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echo "run -all" >> ./sim.do
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311 |
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|
312 |
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vsim -c -do ./sim.do
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313 |
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314 |
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endif
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315 |
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|
316 |
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@ cur_test_num++
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317 |
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|
318 |
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if ($cur_test_num < $max_test_num) then
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319 |
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goto simulate
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320 |
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endif
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321 |
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322 |
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exit
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323 |
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|
324 |
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|
325 |
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# HELP DISPLAY
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326 |
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###############
|
327 |
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|
328 |
|
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help:
|
329 |
|
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echo ""
|
330 |
|
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echo " Valid verification arguments:"
|
331 |
|
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echo " 'help' / '-h' : This help is displayed"
|
332 |
|
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echo " 'modelsim' / '-m' : ModelSim simulation tool is used, otherwise"
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333 |
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echo " NCSim is used (default)"
|
334 |
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echo " 'waveform' / '-w' : Waveform output is recorded, otherwise"
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335 |
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echo " NO waveform is recorded (default)"
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336 |
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echo " 'verbose' / '-v' : Verbose display on monitor, otherwise"
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337 |
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echo " basic display on monitor (default)"
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338 |
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echo " '\042testcase\042' : Testcase which is going to be simulated, otherwise"
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339 |
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echo " ALL testcases are simulated - regression (default);"
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340 |
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echo " Available testcases:"
|
341 |
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foreach testcase (../../../bench/verilog/testcases/uart*.v)
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342 |
|
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echo " "$testcase:t:r
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343 |
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end
|
344 |
|
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echo ""
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345 |
|
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exit
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