Subversion Repositories uart16550

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<b><font size=+2 face="Helvetica, Arial"

color=#bf0000>Project Name: uart16550 core</font></b>

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<font size=+1><b>Description</b></font>

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uart16550 is a 16550 compatible (mostly) UART core.

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The bus interface is WISHBONE SoC bus Rev. B.<BR>

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Features all the standard options of the 16550 UART:<BR>

FIFO based operation, interrupt requests and other.

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The datasheet can be downloaded from the CVS tree along with the source code.

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<font size=+1><B>Current Status</B></font><p>

[Aug 2001]<br>

Core updated and some more bugs fixed.<BR>

It is now being verified more thoroughly but it is mostly usable.<P>

[27.05.2001]<br>

Documentation and core code are updated.<br>

[17.05.2001]:

<ul>

<li>The core is finished unless more bugs are found.</li>

<li>The test bench is very basic yet and is asking for your help to expand it. :-)</li>

</ul>

<p>Maintainer(s):

<ul>Jacob Gorban (<a href="mailto:gorban@opencores.org_NOSPAM">gorban@opencores.org_NOSPAM)</a></ul>

<p>Mailing-list:

<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</A></ul>

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